| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-09-26 | mb/lowrisc: Remove the Nexys4DDR port | Jonathan Neuschäfer |
| 2016-11-07 | riscv: Unify SBI call implementations under arch/riscv/ | Jonathan Neuschäfer |
| 2016-11-07 | mb/lowrisc/nexys4ddr: Actually fix the UART clock setup | Jonathan Neuschäfer |
| 2016-10-28 | riscv: add the lowrisc/nexys4ddr mainboard | Ronald G. Minnich |
 |
index : coreboot.git | |
| my copy of coreboot | gitea |
| aboutsummaryrefslogtreecommitdiff |