coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-01-21	mb/intel/kblrvp: do UART pad configuration at board-level	Michael Niewöhner
2020-11-13	soc/intel/{skl,cnl}: replace PM ACPI timer dt option by Kconfig	Michael Niewöhner
2020-10-21	soc/intel,mb/*: get rid of legacy pad macros	Michael Niewöhner
2020-09-21	mb/intel: Drop unneeded empty lines	Elyes HAOUAS
2020-08-08	soc/intel/skylake: Enable SDXC depending on devicetree configuration	Felix Singer
2020-08-07	mb/intel/kblrvp: Factor out `HeciEnabled`	Angel Pons
2020-07-29	soc/intel/skylake: Enable eMMC depending on devicetree configuration	Felix Singer
2020-07-29	soc/intel/skylake: Enable SATA depending on devicetree configuration	Felix Singer
2020-05-18	skylake: update processor power limits configuration	Sumeet R Pawnikar
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-04-06	mainboard/intel: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-18	mainboard/[g-p]*: Remove copyright notices	Patrick Georgi
2019-12-09	mb/intel/kblrvp: Remove hex values from VR settings	Wim Vervoorn
2019-03-01	soc/intel/skylake: Unify serial IRQ options	Nico Huber
2019-01-09	mb/intel/kblrvp: Enable overridetree support for variants	Praveen hodagatta pranesh
2018-06-05	soc/intel/skylake: Add option to skip coreboot MP init	Subrata Banik
2018-02-08	mb/intel/kblrvp: Enable Kabylake RVP8	V Sowmya