diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-26 17:17:24 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-08-07 10:12:17 +0000 |
| commit | defdc8539ba11207a7b2a330cc4b6d0474b6f1fb (patch) | |
| tree | 34434bb454dbda715d01789bb441a08a9f88d1e8 /src/mainboard/intel/kblrvp/variants/rvp8 | |
| parent | 33aa115574ef70c3ae5baf1a2e489a9a7573052e (diff) | |
mb/intel/kblrvp: Factor out `HeciEnabled`
RVP8 does not set it, and the other variants set it to zero. So, factor
it out.
Tested with BUILD_TIMELESS=1, all four variants do not change.
Change-Id: I67c958af2dc955d07b895dc93fbe2232dbd48d34
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43908
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/kblrvp/variants/rvp8')
| -rw-r--r-- | src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 18d764bf13..25dc49ea51 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -7,7 +7,6 @@ chip soc/intel/skylake # FSP Configuration register "ScsEmmcHs400Enabled" = "0" register "ScsSdCardEnabled" = "0" - register "HeciEnabled" = "0" register "PmTimerDisabled" = "0" register "serirq_mode" = "SERIRQ_CONTINUOUS" |