From defdc8539ba11207a7b2a330cc4b6d0474b6f1fb Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 26 Jul 2020 17:17:24 +0200 Subject: mb/intel/kblrvp: Factor out `HeciEnabled` RVP8 does not set it, and the other variants set it to zero. So, factor it out. Tested with BUILD_TIMELESS=1, all four variants do not change. Change-Id: I67c958af2dc955d07b895dc93fbe2232dbd48d34 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43908 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb | 1 - 1 file changed, 1 deletion(-) (limited to 'src/mainboard/intel/kblrvp/variants/rvp8') diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 18d764bf13..25dc49ea51 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -7,7 +7,6 @@ chip soc/intel/skylake # FSP Configuration register "ScsEmmcHs400Enabled" = "0" register "ScsSdCardEnabled" = "0" - register "HeciEnabled" = "0" register "PmTimerDisabled" = "0" register "serirq_mode" = "SERIRQ_CONTINUOUS" -- cgit v1.2.3