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2024-02-19soc/intel/alderlake: Include ADL-N ID 5 0x4618Sean Rhodes
This patch adds support for using ADL N 4-core MCH ID 0x4618. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3e4855ce93666c54ab35def9b58e4b13bc9a8672 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-18mb/getac to mb/intel: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: Id859c981d0bf5dcf90bf6858607a9fe726516309 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-24mb/hp to mb/kontron: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Icfdadfa6705a64655b38aca25be0818ec26429f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80110 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-01mb/{google,intel}: Update FMD to support CBFS verificationAnil Kumar
This patch adds the required FMD changes to support the change in cse_lite 'commit Ie0266e50463926b8d377825 ("remove cbfs_unverified_area_map() API in cse_lite")' for CBFS verification. With the change in cse_lite the ME_RW_A/B blobs are now part of FW_MAIN_A/B and corresponding entries in FMD can be removed for boards that currently use them. BUG=b:284382452 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I3ca88fee181f059852923d50292b24c0e5b9fd6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/78502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-09-26soc/intel/alderlake: Move C State Demotion to mainboard configSean Rhodes
Rather than disabling C State demotions for every single Raptor Lake board due to an issue with S0ix, regardless of if they even use S0ix, configure it in the mainboard. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4f941a549bc717ae2f8ec961ead7ac7668347c99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-18clean-up: Remove the no more necessary `ENV_HAS_DATA_SECTION` flagJeremy Compostella
With commit b7832de0260b042c25bf8f53abcb32e20a29ae9c ("x86: Add .data section support for pre-memory stages"), the `ENV_HAS_DATA_SECTION' flag and its derivatives can now be removed from the code. Change-Id: Ic0afac76264a9bd4a9c93ca35c90bd84e9b747a2 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77291 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-12treewide: Drop the suffixes from ADL and RPL CPUID macros and stringsMichał Żygowski
CPUID is the same for Alder Lake and Raptor Lake S and HX variants. To reduce the confusion and concerns how to name the macros, remove the suffixes from macros and platform reporting strings. Thankfully the stepping names are unique across mobile (P suffixed) and desktop (S and HX suffixed) SKUs. Distinguishing the S from HX is possible via host bridge PCI ID. Change-Id: Ib08fb0923481541dd6f358cf60da44d90bd75ae2 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2023-06-21mb/intel/adlrvp_rpl: Add initial code for adlrvp_rpl variantHarsha B R
This patch adds the initial code for adlrvp_rpl variant board which includes 1. Add overridetree.cb to corresponding variant directory 2. Update mainboard name in Kconfig and Kconfig.name 3. Add config option to select corresponding overridetree.cb BUG=b:286030718 BRANCH=firmware-brya-14505.B TEST=Able to build with the patch and boot the adlrvp_rpl platform to ChromeOS on Windows SKU. Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ifb95ff705189863d23894769ff450f9528e73b14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73962 Reviewed-by: Usha P <usha.p@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-04-21mb/intel/adlrvp: Enable RTD3 root port mutex for WWANCliff Huang
This adds RTD3 RPMX mutex to the root port. It is shared between RTD3 and WWAN. The purpose of using this mutex is to prevent OSPM from calling _ON and _OFF methods while WWAN kernel driver is calling _RST, which accesses the GPIO pins. BUG=NA BRANCH=firmware-brya-14505.B TEST=boot to OS and check the generated SSDT table for the root port. The RPMX mutex should be generated under the root port. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I809eb84cb1a09deb168040e83041b65237a1b576 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73383 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2023-03-21mb/intel/adlrvp: Enable onboard GBEPatrick Rudolph
The ADL RVP has an i219 PHY connected to the PCH internal MAC. Enable it to have working ethernet on the board. Test: Added GBE region and verified that the PCI device 00:1f.6 is working. Change-Id: I2ca1af00ae4564a04f5388cd3734bb735d87352e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-02-23intel/alderlake: remove skip_mbp_hob SOC chip configKapil Porwal
Introduce at new config option CONFIG_FSP_PUBLISH_MBP_HOB to control the creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. This new option is hooked with `SkipMbpHob` UPD and is always disabled for RPL & ADL-N based ChromeOS platforms. It is not disabled for ADL-P based platforms because ADL-P FSP relies on MBP HOB for ChipsetInit version for ChipsetInit sync. As ChipsetInit sync doesn't occur if no MBP HOB, so it results S0ix issue. This limitation is addressed in the later platforms so creation of MBP HOB can be skipped for ADL-N and RPL based platforms. This made skip_mbp_hob SOC chip config variable redundant which is also removed as part of this change. BUG=none TEST=Build and boot to Google/Taniks. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ia396b633a71aedf592c45b69063ee0528840fd2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-02-16mb/intel/adlrvp: Fix RTD3 timing for PCIe slot1Cliff Huang
Fix RTD3 timing for adlrvp_p_ext_ec and adlrvp_rpl_ext_ec. BUG=none BRANCH=firmware-brya-14505.B TEST=Insert a SD card or NIC AIC on PCIe slot1 and run 'suspend_stress_test -c 1'. The RP8 should not cause suspend issue. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I792c55a6361d1eae55cc6f668a03dc2503120fe1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72422 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-30mb/*: Remove lapic from devicetreeArthur Heymans
The parallel mp code picks up lapics at runtime, so remove it from all devicetrees that use this codebase. Change-Id: I5258a769c0f0ee4bbc4facc19737eed187b68c73 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69303 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-20mb/intel/adlrvp/spd/Makefile.inc: Remove spaces before tabsElyes Haouas
Change-Id: I7bd29bab2c77da2ffe86167d54e87c9941355ea7 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-01-15drivers/i2c/generic: Drop 'disable_gpio_export_in_crs' flagMatt DeVillier
Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the OS driver and ACPI thinking they own the GPIO. This can cause timing problems because it's not clear which system should be controlling the GPIO. Previously, we flagged as an error any device which set the 'has_power_resource' flag but did not set 'disable_gpio_export_in_crs.' There's no reason to require explicit disablement however, so drop the superfluous 'disable' flag, and change the _CRS generation to check if the GPIOs will be exported via the 'has_power_resource' flag instead. BUG=b:265055477 TEST=build/boot skyrim, dump SSDT and verify touchscreen GPIOs only listed under PRx, not under _CRS. Change-Id: I837ae6c6fe4b8e1c4e10686406cba06bdb7759d2 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-12-05mb/intel/adlrvp: Add RTD3 support for PCIe slot1Cliff Huang
Add RTD3 support for adlrvp_p_ext_ec and adlrvp_rpl_ext_ec BUG=none BRANCH=firmware-brya-14505.B TEST=Insert a SD card or NIC AIC on PCIe slot1 and run 'suspend_stress_test -c 1'. The RP8 should not cause suspend issue. Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: Ieb7d207a7ec3763bad3e82522e86a825c1ed00b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70119 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com>
2022-11-07mb/intel/adlrvp: Fix expected statementArthur Heymans
Switch cases expect a statement so move the default label. TEST: With BUILD_TIMELESS=1 binary remains identical. Change-Id: I9a5d39bb3cbde64f82fc90186b0f2fb64bcde595 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66266 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-04mainboard: Include <cpu/cpu.h> instead of <arch/cpu.h>Elyes Haouas
Also sort includes. Change-Id: Iccb7f28a2c913ae0983bf224a03610d7fdd13c68 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-30mb/intel/adlrvp_n: Disable the External 1.05v VR in S0V Sowmya
Disable the external 1.05v VR in S0 as a fix for the display flicker issue in ADL-N. Please refer the Doc with ID 742988 for more details. BUG=b:248249033, b:245970842 TEST=Verified that the display flicker issue is fixed. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: If9f40e6c37e80caceb726a8e5f4d4b14dc479858 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67654 Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-09-20mb/intel/adlrvp: enable ECT for LP5 memoryZhixing Ma
On ADLRVP with LP5 memory, MRC team recommends enabling ECT(Early Command Training) to avoid hang during boot process. BRANCH=firmware-brya-14505.B TEST=Booted to OS on ADLRVP with LP5 memory. Signed-off-by: Zhixing Ma <zhixing.ma@intel.com> Change-Id: I2472707825bbbdd8e5c12a714e0d40ea0b458838 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-09-13mb/intel/adlrvp: Correct HWIDs for ChromeOS devicesVictor Ding
The current HWIDs for ADL RVP are reported as invalid by Chrome on ChromeOS; fix it by generating new valid HWIDs with the following commands: ``` ./util/chromeos/gen_test_hwid.sh ADLRVPM ./util/chromeos/gen_test_hwid.sh ADLRVPN ./util/chromeos/gen_test_hwid.sh ADLRVPP ``` BUG=b:243899466 Change-Id: Iad6f47e67c2d35363b042aabec8b3317d5bfc111 Signed-off-by: Victor Ding <victording@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67532 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-09mb/intel/adlrvp: Enable Cr50 TPM over SPI for adlrvp_rplBora Guvendik
Configure GPIO pins, add Kconfig options and enable TPM device in devicetree. Add H1 TPM IRQ GPIO pin in gpio.c BUG=none BRANCH=firmware-brya-14505.B Cq-Depend: chromium:3774914 TEST=Boot the image and check the successful TPM communication in verstage,romstage & ramstage from coreboot logs. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I1b4119373f69954d620dc09e637a7571312a5fc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-09-09mb/*/{device,override}tree: Set touchpads to use detect (vs probed) flagMatt DeVillier
Historically, ChromeOS devices have worked around the problem of OEMs using several different parts for touchpads/touchscreens by using a ChromeOS kernel-specific 'probed' flag (rejected by the upstream kernel) to indicate that the device may or may not be present, and that the driver should probe to confirm device presence. Since c636142b, coreboot now supports detection for i2c devices at runtime when creating the device entries for the ACPI/SSDT tables, rendering the 'probed' flag obsolete for touchpads. Switch all touchpads in the tree from using the 'probed' flag to the 'detect' flag. Touchscreens require more involved power sequencing, which will be done at some future time, after which they will switch over as well. TEST: build/boot at least one variant for each baseboard in the tree. Verify touchpad works under Linux and Windows. Verify only a single touchpad device is present in the ACPI tables. Change-Id: I47c6eed37eb34c044e27963532e544d3940a7c15 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67305 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-07mb/intel/adlrvp: Make SOC_INTEL_CSE_LITE_SKU configurableMaximilian Brune
Having a CSE Lite SKU's firmware is not necessarily depending on the underlying hardware nor on having ChromeOS installed as already mentioned in commit f3419b29b7e0 ("soc/intel/common/cse: Drop dependency on CHROMEOS for SOC_INTEL_CSE_LITE_SKU"). For example RVP Boards sometimes have a CSE LITE FW, if Chrome board related stuff is tested, which doesn't necessarily imply a ChromeOS being used. It is therefore changed to an option, which can be changed in menuconfig. Change-Id: I4da7feab881ae43528c9d852cc842ac93fa9c6de Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67078 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-29soc/intel/alderlake: Rename pcie5 aliasBora Guvendik
Rename pcie5 alias as pcie5_0 since raptorlake is adding a new pcie5 RC. BRANCH=firmware-brya-14505.B TEST=none Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Iee669e68e3607b7ffec9f0800e9f0a916defd498 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-21Revert "mb/intel/adlrvp: Set EPP to 45% for all Adl RVP variants"V Sowmya
This reverts commit 2b19d547c0866fef84bdb7b226ce7a4ac81af64f. A power and performance analysis performed on Alder Lake demonstrated that with an EPP (Energy Performance Preference) at 50% along with EET (Energy Efficient Turbo) disabled, the overall SoC performance are similar or better and the SoC uses less power. For instance some browser benchmark results improved by 2% and some multi-core tests by 4% while at the same time power consumption lowered by approximately 7.6%. BUG=b:240669428 TEST=verify that EPP is back to the by default 50% setting `iotools rdmsr 0 0x774' Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I76d3914e51c5320af4c202558e1e7c57b7c0de54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com> Reviewed-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-by: Usha P <usha.p@intel.com>
2022-08-19mb/intel/adlnrvp: Skip sending the MBP HOB to save boot timeV Sowmya
This change is to skip sending the MBP HOB since coreboot doesn't use it and also helps to reduce the boot time by ~40msec on ADL-N. Boot time data: Before: * 955:returning from FspSiliconInit 956,832 (110,268) After: * 955:returning from FspSiliconInit 944,528 (74,213) BUG=b:241850107 TEST=Verified that boot time is reduced by ~40msec and also S0i3 is working. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I05d226fb5f05463341358cd20655f06376778bac Reviewed-on: https://review.coreboot.org/c/coreboot/+/66676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-08-16mb/**/dsdt.asl: Drop misleading "OEM revision" commentAngel Pons
It is highly unlikely that the "OEM revision" of the DSDT is 0x20110725 on mainboards with a chipset not yet released on 2011-07-25. Since this comment is most likely to have been copy-pasted from other boards, drop it from boards which use a chipset newer than Sandy/Ivy Bridge. Change-Id: If2f61d09082806b461878a76b286204ae56bf0eb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2022-08-16mb/**/dsdt.asl: Drop superfluous commentsAngel Pons
These comments don't add much value, so remove them. Change-Id: I7e9692e3fe82345cb7ddcb11c32841c69768cd36 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66713 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2022-08-04mb/intel/adlrvp: shorten MAINBOARD_PART_NUMBER to fix buildNick Vaccaro
Building firmware for Brya is currently broken due to the RO_FWID region for adlrvp_m_ext_ec bloating past 64 characters. The CONFIG_MAINBOARD_PART_NUMBER is catenated onto the CONFIG_MAINBOARD_VENDOR string, which for Intel, makes for a very long trunk string that the kernel version will then be added to form the RO_FWID string. For Intel, that trunk string is already pretty long at : "Intel Corporation_Alder Lake Client Platform". Shortening the CONFIG_MAINBOARD_PART_NUMBER should address this issue for now. BUG=b:241273391 TEST="emerge-brya coreboot chromeos-bootimage" and verify it builds successfully Change-Id: Ie862c87dd9a24743f249f1b10862ca6f3295db23 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2022-07-14mb/intel/adlrvp: remove I2S2 GPIO settingsCliff Huang
It turns out that there is no device connected to I2S2. This patch clarifies the GPIO settings device association and remove unnecessary configuration. GPP_A8 -> default: GP-in ; set to NF1: SRCCLKREQ7# GPP_A9 -> default: NF1: ESPI_CLK GPP_A10 -> default: NF1: ESPI_RESET# BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I7a575f495d841fe0bf6fd86a84caeee064f6904b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2022-07-04treewide: Unify Google brandingJon Murphy
Branding changes to unify and update Chrome OS to ChromeOS (removing the space). This CL also includes changing Chromium OS to ChromiumOS as well. BUG=None TEST=N/A Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-06-22mb/intel/adlrvp: Enable early EC sync for ADL-NUsha P
Enable VBOOT_EARLY_EC_SYNC in coreboot. EC Sync was failing on ADL-N RVP since the ec image was not getting stitched into coreboot during emerge build. This is now fixed with https://crrev.com/c/3705002 and hence enabling the EC sync for ADL-N RVP BUG=b:232875824 TEST=Build and boot adlrvp-n. Ensure EC Software sync is complete. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: Ibea37825abd0f13a5184cbbe96c38d44474782f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2022-06-21mb/intel/adlrvp: Select the right Kconfig for raptorlakeUsha P
CL 64619 adds the required initial code for raptorlake. Select BOARD_INTEL_ADLRVP_RPL_EXT_EC for VBOOT_MOCK_SECDATA which is mistakenly not selected. BUG=None BRANCH=firmware-brya-14505.B Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I5da561cb31b0cb0d574a8091cc346d6b321ac6fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/65165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-16mb/intel/adlrvp: Add 5G WWAN ACPI support for ADL-P RVPCliff Huang
Add FM350GL 5G WWAN support using drivers/wwan/fm and additional PM features from RTD3. PCIe root port: 6 (1 based) clock source & request: 5 (0 based) GPIOs: WWAN_PERST_N: GPPC_C5 WWAN_RST_N: GPPC_F14 WWAN_FCP_OFF_N: GPPC_F15 WWAN_WAKE_N: GPPC_D18 WWAN_PWREN: GPPC_F21 WWAN_DISABLE_N: GPPC_D15 CLKREQ5_WWAN_N: GPPC_H23 TEST=Check SSDT table to see if the PXSX device and PowerResource RTD3 are generated under the root port. BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I10902245e3a5e05cd2af9030394933e936c25396 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63941 Reviewed-by: Jeremy Compostella <jeremy.compostella@intel.corp-partner.google.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2022-06-14mb/intel/adlrvp: Add new upd setting for ADL RVP with Raptor LakeBora Guvendik
Currently, ADL FSP headers and RPL FSP headers differ. Set a RPL only upd for adlrvp with Raptor Lake silicon. This code can be removed once ADL and RPL start using the same FSP. BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=build adlrvp_rpl_ext_ec Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I4e69323949233aa8c325a757b28b9d80cbdf4322 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-10mb/intel/adlrvp: Add 5G WWAN ACPI support for adlrvp_rpl_ext_ecCliff Huang
Add FM350GL 5G WWAN support using drivers/wwan/fm and additional PM features from RTD3. TEST=Check SSDT table to see if the PXSX device and PowerResource RTD3 are generated under the root port. BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: I74434d833086f639927d8369f8a6e3af31dd99e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64648 Reviewed-by: Jeremy Compostella <jeremy.compostella@intel.corp-partner.google.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-10mb/intel/adlrvp: Select SOC_INTEL_RAPTORLAKE adlrvp_rpl_ext_ec variantBora Guvendik
BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=build adlrvp_rpl_ext_ec Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I12eab0fe2a3c21011f50c72718514fbc90cbe658 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-10mb/intel/adlrvp: disable unused root port 1, 3, 4 for Adl-P RVPCliff Huang
In Adl-P RVP, those interfaces are used as USB ports. BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: I322280ab02361e3a2a5925d69f33b23453d36dbf Reviewed-on: https://review.coreboot.org/c/coreboot/+/63946 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Jeremy Compostella <jeremy.compostella@intel.corp-partner.google.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-10mb/intel/adlrvp: x4 slot support (SD card support) for Adl-P RVPCliff Huang
Use clock src and clock req to 7 for x4 slot. Remove free running clock setting for clock 6. Configure gpio for source clock OEB native function going to x4 slot. BUG=b:233252409 BRANCH=firmware-brya-14505.B TEST=insert SD AIC to x4 slot. boot to OS and use 'lspci' to check the device. ex: 58:00.0 SD Host controller: O2 Micro, Inc. Device 8621 (rev 01) NOTE: The bus number varies. Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: Iba5d83d133b6ae8cd389ddd971db308170094300 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2022-06-07mb/intel/adlrvp: Add VBT for adlrvp with Raptor Lake siliconBora Guvendik
Board id is same so use cpuid to decide to use ADL or RPL VBT. BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=build adlrvp_rpl_ext_ec Change-Id: I954c228f82110c3e7c8474e47cabab8220ff19b9 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64672 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Jeremy Compostella <jeremy.compostella@intel.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-07mb/intel/adlrvp: Add initial code for adlrvp with raptorlake siliconBora Guvendik
Take adlrvp_p as a baseline code and add a new variant of ADL RVP with Raptor Lake silicon. BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=build adlrvp_rpl_ext_ec Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I880abe0f300118f461523173cc0d50a2fbc99e72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-02mb/intel/adlrvp: Enable DPTF for ADL-N RVPVidya Gopalakrishnan
BUG=None BRANCH=None TEST=Build FW and test on adln_rvp board Verified thermal throttling successfully when participant reaches temp threshold as per Passive Policy. Verified fan control successfully when participant reaches temp threshold as per Active Policy. Also, verified system shutdown when Temperature of participants are reaching threshold as per Critical policy. Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Change-Id: Icafacfca6a026ec3b42906790831f11fd2f1b085 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-06-02mb/intel/adlrvp: Set power limits dynamically for ADL-N SKUsVidya Gopalakrishnan
This patch adds support for the ADL-N SKUs based on the PCH ID. Document reference: 645548 (ADL-N EDS Volume 1). BUG=None BRANCH=None TEST=Build FW and test on adln_rvp board Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Change-Id: Ie49398b8a7de8d8cff3536eae6a5e893980f9c26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-05-20mb/intel/adlrvp: Configure the external V1p05/Vnn/VnnSx railsV Sowmya
This patch configures external V1p05/Vnn/VnnSx rails for adlrvp-n to achieve the better power savings. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 , S0 states. * Set the supported voltage states. * Set the voltage for v1p05 and vnn. * Set the ICC max for v1p05 and vnn. Kit: 646929 - ADL N Platform Design Guide BUG=b:223102016 TEST=Verified all the UPD values are updated with these configs. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I06298eb1aec07eae34420c5736e912c707fefbc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-04-21tpm: Refactor TPM Kconfig dimensionsJes B. Klinke
Break TPM related Kconfig into the following dimensions: TPM transport support: config CRB_TPM config I2C_TPM config SPI_TPM config MEMORY_MAPPED_TPM (new) TPM brand, not defining any of these is valid, and result in "generic" support: config TPM_ATMEL (new) config TPM_GOOGLE (new) config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE) config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE) What protocol the TPM chip supports: config MAINBOARD_HAS_TPM1 config MAINBOARD_HAS_TPM2 What the user chooses to compile (restricted by the above): config NO_TPM config TPM1 config TPM2 The following Kconfigs will be replaced as indicated: config TPM_CR50 -> TPM_GOOGLE config MAINBOARD_HAS_CRB_TPM -> CRB_TPM config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE Signed-off-by: Jes B. Klinke <jbk@chromium.org> Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-21mb/intel/adlrvp: Set half_populated true for ADL-NUsha P
Alder Lake-N has single memory controller with 64-bit bus width. Alder Lake common meminit block driver considers bus width to be 128-bit and populates the meminit data accordingly. By setting half_populated to true, only the bottom half is populated. Ideally, half_populated is used in platforms with multiple channels to enable only one half of the channel. Alder Lake N has single channel, and it would require for new structures to be defined in meminit block driver for LPx memory configurations. In order to avoid adding new structures, set half_populated to true. This has the same effect as having single channel with 64-bit width. BRANCH=NONE TEST=Build and boot ADL-N RVP. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I2ecc3018a1ab039990ba47898ff0e0e2ede695cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/62913 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-20mb/intel/adlrvp: Enable UFS and ISH for ADL-N RVPMeera Ravindranath
In order to enable the UFS controller (PCI device 12.7), the PCI specification says that the device at function 0 in the same slot must also be enabled, which is the ISH. Therefore, this CL enables both the UFS controller and ISH. TEST=Boot to kernel and check lspci output 00:12.0 Serial controller: Intel Corporation Device 54fc 00:12.7 Mass storage controller [0109]: Intel Corporation Device 54ff Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Change-Id: If15bcaffc8fd3bbbe4b181820993ab2d882bbbe1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62662 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-20ChromeEC boards: Drop `IGNORE_IASL_MISSING_DEPENDENCY`Angel Pons
This should no longer be needed because the ASL has been fixed. Change-Id: I4d1500217bef54fa3d2be397e5e2a155da3f965d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-20mb/intel/adlrvp_n: Disable SATA controllerUsha P
Disable SATA config from devicetree for ADL-N RVP, since we are not planning to use it in chrome config. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: Ic9dce3a0b06e1a0d0d9fa495aa406eb12557d842 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-04-13mb/intel/adlrvp: Disable PM Timer for ADL-NUsha P
Keeping the PM timer enabled will disqualify an ADL system from entering S0i3, and will also cause an increase in power during suspend states. The PM timer is not required for ADL-N boards, therefore disabling it. BRANCH=NONE TEST=Build and boot ADL-N RVP. Verify system is entering S0i3 state. localhost ~ # cat /sys/kernel/debug/pmc_core/substate_residencies Substate Residency S0i2.0 0 S0i3.0 13196801 Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I44651bf55df8e71a0a5a9a33ecbb8322ecd18575 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-04-07ChromeOS: Add DECLARE_x_CROS_GPIOS()Kyösti Mälkki
Change-Id: I88406fa1b54312616e6717af3d924436dc4ff1a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-06ChromeOS: Promote variant_cros_gpio()Kyösti Mälkki
The only purpose of mainboard_chromeos_acpi_generate() was to pass cros_gpio array for ACPI \\OIPG package generation. Promote variant_cros_gpio() from baseboards to ChromeOS declaration. Change-Id: I5c2ac1dcea35f1f00dea401528404bc6ca0ab53c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30mb/intel/adlrvp: Deselect ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTORSridhar Siricilla
The patch deselects ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR Kconfig for ADL RVP board. The flag updates PMC settings in the IFD for Alder Lake A0 silicon. As Alder Lake A0 is intermediate stepping, and the IFD is locked in the production systems, so the Kconfig is deselected. TEST=Build the coreboot for adlrvp Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I966be42ba662861f4a6933d7275ecc13860220f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-27mb/intel/adlrvp: Select VBOOT_MOCK_SECDATA for ADL-NUsha P
Use MOCK TPM in vboot, since TPM is not enabled in ADLN RVP. BRANCH:NONE TEST=build and boot ADL-N RVP. Verify no TPM errors in depthcharge. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: Ibc0112545dbd80921d89d48eff58c512729243af Reviewed-on: https://review.coreboot.org/c/coreboot/+/62957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-03-18mb/intel/adlrvp: Set EPP to 45% for all Adl RVP variantsCliff Huang
This sets EPP value to be 45% for all Adl RVP variants. Historically, EPP Ratio has always been 50% (128) on Chrome platforms. But on Intel Alderlake EPP ratio of 45% is recommended for optimal power and performance on Chrome platforms. TEST= Use 'iotools rdmsr [cpu id] 0x774' command and check field 32:24 = 0x73. Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: If83a2148d596efccd2e50cc82f1afcbfb9ebb935 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2022-03-15soc/intel/adl/chip.h: Convert all camel case variables to snake caseMAULIK V VAGHELA
coreboot chip.h files mainly contains variable which allows board to fill platform configuration through devicetree. Since many of this configuration involves FSP UPDs, variable names were in camel case which aligned with UPD naming convention. By default coreboot follow snake case variable naming, so cleaning up file to align all variable names as per coreboot convention. During renaming process, this patch also removes unused variables listed below: -> SataEnable // Checked in SoC code based on PCI dev enabled status -> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used Note: Since separating out changes into smaller CL might break the compilation for the patch set, this is being pushed as a single big CL. BUG=None BRANCH=firmware-brya-14505.B TEST=All boards using ADL SoC compiles with the CL. Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-03-15{mb, soc}: Move mrc_cache invalidating logic into `memory` common codeSubrata Banik
Commit hash b8b40964 ( mb, soc: Add the SPD_CACHE_ENABLE) introduced per mainboard logic to invalidate the mrc_cache. This patch moves mrc_cache invalidating logic into IA common code and cleans up the code to remove unused argument `dimms_changed` from SoC and mainboard directory. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6f18e18adc6572571871dd6da1698186e4e3d671 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-15{mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototypeSubrata Banik
This patch modifies `memcfg_init` and `variant_memory_init`functions argument from FSP_M_CONFIG to FSPM_UPD. This change in `memcfg_init()` argument will help to update the architectural FSP-M UPDs from common code blocks rather than going into SoC and/or mainboard implementation. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-07src: Make PCI ID define names shorterFelix Singer
Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with PCI_{DID,VID}_ using the commands below, which also take care of some spacing issues. An additional clean up of pci_ids.h is done in CB:61531. Used commands: * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g' * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g' Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-03-02mb, soc: Add the SPD_CACHE_ENABLEZhuohao Lee
In order to cache the spd data which reads from the memory module, we add SPD_CACHE_ENABLE option to enable the cache for the spd data. If this option is enabled, the RW_SPD_CACHE region needs to be added to the flash layout for caching the data. Since the user may remove the memory module after the bios caching the data, we need to add the invalidate flag to invalidate the mrc cache. Otherwise, the bios will use the mrc cache and can make the device malfunction. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=build pass and enable this feature to the brask the device could speed up around 150ms with this feature. Change-Id: If7625a00c865dc268e2a22efd71b34b40c40877b Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62294 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-01mb/intel/adlrvp: Enable eMMC device for ADL-N RVPKrishna Prasad Bhat
Add eMMC related GPIO pins in gpio_n.c and enable eMMC device for Alder Lake N RVP from devicetree. Change-Id: I66e015aa921383cfc21cfe261377ae6b3b58cbab Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-02-25mb, soc: change mainboard_memory_init_params prototypeZhuohao Lee
The mainboard_memory_init_params takes the struct FSP_M_CONFIG as the input which make the board has no chance to modify data in the FSPM_UPD, for example, set FspmArchUpd.NvsBufferPtr = 0. After changing the FSP_M_CONFIG to FSPM_UPD, the board can modify the value based on its requirement. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=build pass Change-Id: Id552b1f4662f5300f19a3fa2c1f43084ba846706 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-25mb/intel/adlrvp: Add support for MAX98373 codecUsha P
- Add configurability using FW_CONFIG field in CBI, to enable/disable I2S codec support for MAX98373 codecs - AUDIO=ADL_MAX98373_ALC5682I_I2S: enable max98373 codec using expansion board Bug=None Test=With CBI FW_CONFIG set to 0x100, check I2S audio output on expansion card Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I94dfe500b99a669e9b981cdf15e360f22f33d2ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/61544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-02-21mb/intel/adlrvp_n: Update devicetreeKrishna Prasad Bhat
Update devicetree according to schematics. TEST=Build and boot Alder Lake N RVP. Change-Id: I9faee1cb3539a0246fc6a87e15b3150533de1ee5 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-02-10mb/intel/adlrvp: Fix vbt loading errorLean Sheng Tan
When booting ADL RVP, coreboot is unable to load VBT binary as makefile will rename VBT binary to "vbt.bin" when building coreboot.rom. The reason for having this function is that chromeOS has emerge tool to streamline the VBT stitching process to support multiple VBTs for different RVP boards; while we only need 1 vbt for generic non-chromeOS usage. Hence add a chomeos kconfig to guard this. TEST=Able to boot ADL RVP DDR5 with DP display. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I5f6f9554b75f4d62198aac9938e65c71c3e7cee9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-31mb/**/Kconfig: Properly override `IGNORE_IASL_MISSING_DEPENDENCY`Angel Pons
Don't unconditionally override `IGNORE_IASL_MISSING_DEPENDENCY`. Change-Id: I02081d0f04be4af9cd765aa3b29295af40f9ca99 Fixes: commit 28fa297901ffd158631cfc9f562f38119eff628e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-01-28IASL: Ignore IASL's "Missing dependency" warningElyes HAOUAS
IASL compiler check for usage of _CRS, _DIS, _PRS, and _SRS objects: 1) If _PRS is present, must have _CRS and _SRS 2) If _SRS is present, must have _PRS (_PRS requires _CRS and _SRS) 3) If _DIS is present, must have _SRS (_SRS requires _PRS, _PRS requires _CRS and _SRS) 4) If _SRS is present, probably should have a _DIS (Remark only) IASL will issue a warning for each missing dependency. Ignore this warnings for existing ASL code and issue a message when the build is complete. Change-Id: I28b437194f08232727623009372327fec15215dd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-01-25soc/intel/adl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
Since Tiger Lake platform, the HECI1 device can be disabled on Alder Lake platform using two different mechanism: A. Using PMC IPC command 0xA9. B. Sending SBI message under SMM. In current scope of Alder Lake the default implementation is using (B) sending sbi message under SMM. A follow up patch to add the possible options and let platform to choose the applicable one. List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. 3. Default enable HECI1 device in `chipset.cb` to ensure the HECI1 device can undergo the PCI enumeration and later based on the mainboard policy the HECI1 device can be disabled. Mainboards that choose to make HECI1 enable during boot don't override `DISABLE_HECI1_AT_PRE_BOOT` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie673e634fbc0bdece419c379d417b08dfb4819e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-22mb/intel/adlrvp: Add missing CAM1 RST GPIO for ADL-NUsha P
Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I79f2206bee5403c3fb1c999918fbd2177d0d07ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/61163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-01-18mb/intel/adlrvp: Add wake events for AC connect/disconnectKrishna Prasad Bhat
Enable S3/S0ix wake events for AC connect/disconnect on Alder Lake RVP. BUG=None BRANCH=None TEST=Verify board wakes from S0ix on AC connect/disconnect. Change-Id: Iaf92821fd69a59624e58cb8af3896e2b6998723f Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-18mb/intel/adlrvp_n: Configure EC in RW GPIOKrishna Prasad Bhat
EC_IN_RW signal from EC GPIO is connected to GPIO E7 of SOC. This GPIO can be used to check EC status trusted (LOW: in RO) or untrusted (HIGH: in RW). BRANCH=None BUG=None TEST=Issue manual recovery and confirm DUT is entering recovery mode. Change-Id: Ib8b6be9fcda24bd2bb479b5b6c01f24a6e9c7b1f Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-01-17mb/google/brya/variants/*: Add cpu pcie rp flagsTracy Wu
Along with commit f94405219c (soc/intel/alderlake: Hook up FSP-S CPU PCIe UPDs), we need to set cpu pcie rp flags in devicetree now. This CL is to add proper cpu pcie flags (PCIE_RP_LTR and PCIE_RP_AER) in all intel projects or system will be blocked at PKGC2R with root port LTR not enable. BUG=b:214009181 TEST=Build and DUT (Kano) can enter deeper PKGC state normally. Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com> Change-Id: I0d8721bf1454448b7fc14655f0e4513001469a18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-11soc/intel/alderlake: Factor out A0 stepping workaroundAngel Pons
Move the `configure_pmc_descriptor()` function to SoC scope instead of having two identical copies in mainboard scope. Add a Kconfig option to allow mainboards to decide whether to implement this workaround. Change-Id: Ib99073d8da91a93fae9c0cebdfd73e39456cdaa8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-01src: Drop duplicated includesElyes HAOUAS
<types.h> already provides <commonlib/bsd/cb_err.h>, <limits.h>, <stdbool.h>, <stdint.h> and <stddef.h> headers. Change-Id: I700b3f0e864ecce3f8b3b66f3bf6c8f1040acee1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-12-24mb/google/taniks,vell;mb/intel/adlrvp_n_ext_ec: fix build errorFelix Held
Commit d448f8ce0fe9955e7792f54cc278897152d53590 (drivers/intel/pmc_mux/ conn: Change usb{23}_port_number fields to device pointers) changed the way the pmc_mux/conn driver gets the corresponding USB ports from the devicetree. This change didn't include the corresponding change for the Taniks and Vell variants of the Google Brya project and the Intel adlrvp_n_ext_ec board which probably weren't in the tree at the time the patch referenced above was created. This patch ports the needed change forward to those boards to fix the build of the upstream tree. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id295cd11fbbfe038534b154215a6de7c1ac13e0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/60329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-12-24mb/intel/adlrvp: Configure GPIOs for Alder Lake-NUsha P
List of changes: 1. Add separate file for ADL-N GPIOs 2. Configure GPIOs as per the schematics of ADL-N RVP Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I0c0ca52d0cc73acfd8503007d5f3d2ad9a48f8ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/59937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2021-12-23mb: Add space before closing comment block keywordPaul Menzel
Run the command below to fix all occurrences. $ git grep -l 'ramstage\*/' | xargs sed -i 's,ramstage\*/,ramstage */,' Change-Id: Ied155d325846fc0ef3e823e5708c6f74e3d7998f Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-23ChromeOS: Refactor ACPI CNVS generationKyösti Mälkki
Remove chromeos_dsdt_generator() calls under mainboard, it is possible to make the single call to fill \CNVS and \OIPG without leveraging device operations. Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-23mb/intel/adlrvp_n: Add support for ADL-N LP5 RVPKrishna Prasad Bhat
Add support for Alder lake N LP5 RVP with board ID 0x7. Since SPD index 7 is unused earlier, ADL-N will use it. Change-Id: Ib2f53e65f75e23793d8c85ee924827446fd9fea7 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-12-23drivers/intel/pmc_mux/conn: Change usb{23}_port_number fields to device pointersReka Norman
Currently, the pmc_mux/conn driver uses integer fields to store the USB-2 and USB-3 port numbers from the SoC's point of view. Specifying these as integers in the devicetree is error-prone, and this information can instead be represented using pointers to the USB-2 and USB-3 devices. The port numbers can then be obtained from the paths of the linked devices, i.e. dev->path.usb.port_id. Modify the driver to store device pointers instead of integer port numbers, and update all devicetrees using the driver. These are the mainboards affected (all are Intel TGL or ADL based): google/brya google/volteer intel/adlrvp intel/shadowmountain intel/tglrvp system76/darp7 system76/galp5 system76/lemp10 Command used to update the devicetrees: git grep -l "usb._port_number" src/mainboard/ | \ xargs sed -i \ -e 's/register "usb2_port_number" = "\(.*\)"/use usb2_port\1 as usb2_port/g' \ -e 's/register "usb3_port_number" = "\(.*\)"/use tcss_usb3_port\1 as usb3_port/g' BUG=b:208502191 TEST=Build test all affected boards. On brya0, boot device and check that the ACPI tables generated with and without the change are the same. Change-Id: I5045b8ea57e8ca6f9ebd7d68a19486736b7e2809 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-12-23mb/intel/{adlrvp,sm}: Remove unused header `helpers.h`Subrata Banik
This patch removes unused header inclusion as <commonlib/helpers.h> from several mainboard gpio definition files. Change-Id: I36758089a4981bba916f4d9cf485f64fca2f81ae Signed-off-by: subratabanik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-12-15mb/intel/adlrvp_n: Add initial code for adl-n variant boardKrishna Prasad Bhat
This patch adds the following list of changes: 1. Create a new devicetree for adlrvp-n and copy contents of adlrvp-p devictree. 2. Add support for 2 mainboards as ADL-N board with default EC (Windows SKU) and Chrome EC (Chrome SKU) and copy overridetree contents from adlrvp-p. 3. Add mainboard Kconfig to Kconfig.name file 4. Handle mainboard names in Kconfig file for ADLRVP N 5. Add config options to pick the adlrvp_n devicetree Change-Id: I4abf3bf62ec0398ae75e21575a2fab0d44b5c7ad Signed-off-by: Usha P <usha.p@intel.com> Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-10mb/intel/adlrvp: Add support for external clock bufferSubrata Banik
ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals. Out of 7 SRCCLK's 3 will be used for CPU, the rest are for PCH. If more than 4 PCH devices are connected on the platform, an external differential buffer chip needs to be placed at the platform level. A mainboard designer can choose to add an external clock chip, and select the SRC CLK using CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER. CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER provides the CLKSRC that feed clock to discrete buffer for further distribution to platform. TEST=Able to detect SD card connected at x4 PCIe Gen 3 Slot. localhost ~ # dmesg | grep mmc [ 4.997840] mmc0: SDHCI controller on PCI [0000:ae:00.0] using ADMA [ 5.460902] mmc0: new ultra high speed DDR50 SDHC card at address aaaa [ 5.473555] mmcblk0: mmc0:aaaa SS08G 7.40 GiB [ 5.494268] mmcblk0: p1 Change-Id: I21f1155374049c90aa45db25d4128b39aa5898bb Signed-off-by: Subrata Banik <subi.banik@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03mb/google/brya/var/brask: Set vGPIO reset typeKane Chen
Due to the vGPIO is not reset when we power on through S5, we would met MCA when PCIE send L1 request without following Ack BUG=b:207625007 TEST=S0->S3->S5->power key->S3->S0, see if boot up normal Change-Id: I20cdd1650d1ca774065a6c051006dfd0b7a3fd79 Signed-off-by: Curtis Chen <curtis.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-02soc/intel/alderlake: Add Kconfigs for all PCH typesAngel Pons
The Alder Lake code currently supports the PCH-M and PCH-P types, which have some differences (so far, only the amount of PCIe I/O). Mainboards can use the `SOC_INTEL_ALDERLAKE_PCH_M` Kconfig option to specify which PCH type they use: select the option to choose PCH-M, do not select the option to choose PCH-P. While this works, it can be confusing once more PCH types are added. Introduce the `SOC_INTEL_ALDERLAKE_PCH_P` Kconfig option so that boards have to explicitly choose a PCH type. Also, use this option to restrict the PCH-P defaults for PCH-dependent settings to avoid unintended reuse of the PCH-P defaults when adding a new PCH type. To make sure only one PCH type is selected, add some preprocessor in `bootblock.h` to provoke a build-time error if this requirement is not met. Kconfig doesn't seem to have a mechanism to describe sets of mutually-exclusive bool options that allows said options to be selected (a `choice` block doesn't allow its elements to be selected). Finally, adapt the ADL boards accordingly. Change-Id: I7deca820e08ce2b5a220f3c97a511a4f3464a976 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-11-22mb/intel/adlrvp: Use dedicated VBT files for ADL-MBernardo Perez Priego
ADL-M has its own set of VBT files to pick during execution, this will avoid any conflict with other ADL variants. VBT files added at chrome-internal:4138272 BUG=None TEST= Boot device on LP5/LP4, corresponding VBT file should be loaded. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Ibbf3f11c9277f5dcb3e12f9020f54ec843444c3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/58202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2021-11-19mb/intel/adlrvp: Enable CPU PCIe RP 2Meera Ravindranath
Disabling CPU PCIe RP 2 (commit:3fd39467b Fix S0ix regression) causes regression in NVMe boot on ADL-P RVP boards. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I0b8b76a5537d8b80777cb7588ce6b22281af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59392 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-17mb/intel/adlrvp: Fix sagv point3 clipping to 4800MhzBora Guvendik
Update board type to 4 as per MRC team's input. This fixes LP5 sagv point 3 being clipped from the expected 5200Mhz to 4800Mhz. TEST=Boot to OS, verify frequency locked. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I9472aec41537425c1ed648b949f484939ee9ff99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17mb/intel/adlrvp: Fix S0ix regressionMeera Ravindranath
The following changes are needed to fix S0ix regression on RVP 1) Disable Clk src 3 2) Disable Ext FIVR settings TEST=Boot adlrvp to OS, confirm S0ix is working. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I0b8b76b5527d8b80776cb7588ce6b12281af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-11-15Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"Hsuan-ting Chen
This reverts commit adb393bdd6cd6734fa2672bd174aca4588a68016. This relands commit 6260bf712a836762b18d80082505e981e040f4bc. Reason for revert: The original CL did not handle some devices correctly. With the fixes: * commit 36721a4 (mb/google/brya: Add GPIO_IN_RW to all variants' early GPIO tables) * commit 3bfe46c (mb/google/guybrush: Add GPIO EC in RW to early GPIO tables) * commit 3a30cf9 (mb/google/guybrush: Build chromeos.c in verstage This CL also fix the following platforms: * Change to always trusted: cyan. * Add to early GPIO table: dedede, eve, fizz, glados, hatch, octopus, poppy, reef, volteer. * Add to both Makefile and early GPIO table: zork. For mb/intel: * adlrvp: Add support for get_ec_is_trusted(). * glkrvp: Add support for get_ec_is_trusted() with always trusted. * kblrvp: Add support for get_ec_is_trusted() with always trusted. * kunimitsu: Add support for get_ec_is_trusted() and initialize it as early GPIO. * shadowmountain: Add support for get_ec_is_trusted() and initialize it as early GPIO. * tglrvp: Add support for get_ec_is_trusted() with always trusted. For qemu-q35: Add support for get_ec_is_trusted() with always trusted. We could attempt another land. Change-Id: I66b8b99d6e6bf259b18573f9f6010f9254357bf9 Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-11ChromeOS: Replace with or add <types.h>Kyösti Mälkki
It's commented in <types.h> that it shall provide <commonlib/helpers.h>. Fix for ARRAY_SIZE() in bulk, followup works will reduce the number of other includes these files have. Change-Id: I2572aaa2cf4254f0dea6698cba627de12725200f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-09mb/intel/adlrvp: Set same size for CSE_RW and ME_RW_A/BReka Norman
During CSE firmware updates, the CSE RW firmware from ME_RW_A/B is copied to CSE_RW, so the sizes of these regions need to match. BUG=b:189177538 TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I94e0615088349af34020fb8a126fce9e72df9ee2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-11-09ChromeOS: Fix <vc/google/chromeos/chromeos.h>Kyösti Mälkki
Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-05mb/google,intel: Fix indirect include bootmode.hKyösti Mälkki
Change-Id: I9e7200d60db4333551e34a615433fa21c3135db6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-02mb/intel/adlrvp: Configure EC in RW GPIOAnil Kumar
EC_IN_RW signal from EC GPIO is connected to GPIO E7 of SOC. This GPIO can be used to check EC status trusted (LOW: in RO) or untrusted (HIGH: in RW). Branch=none Bug=none Test=Issue manual recovery and confirm DUT is entering recovery mode on ADL-M RVP. Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I20804db450ab0b3ebe19c51ba2b294a0137d81a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-29Revert "mb/intel/adlrvp: Remove EC region"Bernardo Perez Priego
This reverts commit 0a1602217fd0d60c59a497cb83a23b44cf4973d9. EC region is required in order to provide unified coreboot image for Chrome and Windows SKU RVP's. Also removing EC region causes a regression for ADL-P platforms. With this patch EC region is included back into flash map. Change-Id: I0f7f2b5dd392b08e1978a3b3f3236eac0dab1f12 Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-10-26intel/adlrvp: Add sub-regions to SI_ME in chromeos.fmdFurquan Shaikh
This change adds sub-regions to SI_ME in chromeos.fmd. These are required to support stitching of CSE components. BUG=b:189177538 Change-Id: Ife48aafcec43555175aad44f8b6307beeaea9184 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58592 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-20mb/intel/adlrvp: Rework KconfigFelix Singer
Rework Kconfig file that each variant has its own config option with their specific selects / configuration and move common selects to `BOARD_INTEL_ADLRVP_COMMON`, which is used as base for each variant. Also, move selects from Kconfig.name to Kconfig that the configuration is at one place and not distributed over two files. Built each variant with `BUILD_TIMELESS=1` and all generated coreboot.rom files remain identical. Excluded the .config file by disabling `INCLUDE_CONFIG_FILE` to make this reproducible. Change-Id: If68c118f22579cc0a3db570119798f0f535f9804 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56221 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-20mb/intel/adlrvp_m: Enable touchpadBernardo Perez Priego
These changes include ELAN touchpad to ACPI tables and configure GPIO's. BUG=None Test=Boot board, touchpad should be functional Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I78e5e133f7d3af47395819a79638a90fee4fd19e Reviewed-on: https://review.coreboot.org/c/coreboot/+/57863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-21 01:26:02 +0000