diff options
| author | Kapil Porwal <kapilporwal@google.com> | 2023-01-16 16:07:48 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-02-23 12:15:35 +0000 |
| commit | 23ef60de984bb67e90cc08edb2852d989d47c616 (patch) | |
| tree | b145429a19680424848405c54c9f79fc8e19f217 /src/mainboard/intel/adlrvp | |
| parent | c071652a4e6ad8deb319663f400fd46cf9114947 (diff) | |
intel/alderlake: remove skip_mbp_hob SOC chip config
Introduce at new config option CONFIG_FSP_PUBLISH_MBP_HOB to control
the creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP.
This new option is hooked with `SkipMbpHob` UPD and is always disabled
for RPL & ADL-N based ChromeOS platforms.
It is not disabled for ADL-P based platforms because ADL-P FSP relies
on MBP HOB for ChipsetInit version for ChipsetInit sync. As ChipsetInit
sync doesn't occur if no MBP HOB, so it results S0ix issue. This
limitation is addressed in the later platforms so creation of MBP HOB
can be skipped for ADL-N and RPL based platforms.
This made skip_mbp_hob SOC chip config variable redundant which is also
removed as part of this change.
BUG=none
TEST=Build and boot to Google/Taniks.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ia396b633a71aedf592c45b69063ee0528840fd2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/mainboard/intel/adlrvp')
| -rw-r--r-- | src/mainboard/intel/adlrvp/devicetree_n.cb | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb index b54a134530..6776284fe0 100644 --- a/src/mainboard/intel/adlrvp/devicetree_n.cb +++ b/src/mainboard/intel/adlrvp/devicetree_n.cb @@ -150,8 +150,6 @@ chip soc/intel/alderlake .vnn_icc_max_ma = 500, }" - register "skip_mbp_hob" = "1" - device domain 0 on device ref igpu on end device ref dtt on |