diff options
| author | Zhixing Ma <zhixing.ma@intel.com> | 2022-09-14 15:31:29 -0700 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-09-20 08:05:41 +0000 |
| commit | c9933b2c277258fdb1a5359b426c5089af0e3cf8 (patch) | |
| tree | 9583e4bf7caef8b4b69309c33b2711bd7345eb47 /src/mainboard/intel/adlrvp | |
| parent | 69b00c6f1bd30ab3233d701d133cc600b5cec878 (diff) | |
mb/intel/adlrvp: enable ECT for LP5 memory
On ADLRVP with LP5 memory, MRC team recommends enabling ECT(Early
Command Training) to avoid hang during boot process.
BRANCH=firmware-brya-14505.B
TEST=Booted to OS on ADLRVP with LP5 memory.
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Change-Id: I2472707825bbbdd8e5c12a714e0d40ea0b458838
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/mainboard/intel/adlrvp')
| -rw-r--r-- | src/mainboard/intel/adlrvp/memory.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c index b917d98e10..160059921b 100644 --- a/src/mainboard/intel/adlrvp/memory.c +++ b/src/mainboard/intel/adlrvp/memory.c @@ -137,7 +137,7 @@ static const struct mb_cfg lp5_mem_config = { .ddr7 = { .dqs0 = 0, .dqs1 = 1 } }, - .ect = false, /* Early Command Training */ + .ect = true, /* Early Command Training */ .LpDdrDqDqsReTraining = 1, |