From c9933b2c277258fdb1a5359b426c5089af0e3cf8 Mon Sep 17 00:00:00 2001 From: Zhixing Ma Date: Wed, 14 Sep 2022 15:31:29 -0700 Subject: mb/intel/adlrvp: enable ECT for LP5 memory On ADLRVP with LP5 memory, MRC team recommends enabling ECT(Early Command Training) to avoid hang during boot process. BRANCH=firmware-brya-14505.B TEST=Booted to OS on ADLRVP with LP5 memory. Signed-off-by: Zhixing Ma Change-Id: I2472707825bbbdd8e5c12a714e0d40ea0b458838 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67651 Tested-by: build bot (Jenkins) Reviewed-by: Nick Vaccaro --- src/mainboard/intel/adlrvp/memory.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/intel/adlrvp') diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c index b917d98e10..160059921b 100644 --- a/src/mainboard/intel/adlrvp/memory.c +++ b/src/mainboard/intel/adlrvp/memory.c @@ -137,7 +137,7 @@ static const struct mb_cfg lp5_mem_config = { .ddr7 = { .dqs0 = 0, .dqs1 = 1 } }, - .ect = false, /* Early Command Training */ + .ect = true, /* Early Command Training */ .LpDdrDqDqsReTraining = 1, -- cgit v1.2.3