summaryrefslogtreecommitdiff
path: root/src/mainboard/intel/adlrvp
AgeCommit message (Collapse)Author
2021-08-10mb/*/brya/adlrvp: Remove hardcoding of BSP APIC IDMAULIK V VAGHELA
coreboot always assumes that BSP APIC ID will be 0 and core enumeration logic will look for lapic id from the mainboard. As per Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 3: 8.4.1 BSP and AP Processors, this assumption might not hold true and we may have any other core as BSP. To handle this, we need to remove hardcoding of APIC ID 0 from mainboard. BUG=None BRANCH=None TEST=Check if there is no functional impact on the board. Change-Id: Ibc60494b0032a3139c1e6c79251fb2da750c8de8 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-08-09mb/intel/adlrvp: Support VBT binaries for LP4 and LP5Bernardo Perez Priego
This will enable to include multiple VBT binaries in a single image and load corresponding file according to HW configuration. BUG=None TEST= Boot device on LP5/LP4, corresponding VBT file should be loaded. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Iace0e5e0783b2074393a537da8cc645102d2acda Reviewed-on: https://review.coreboot.org/c/coreboot/+/55969 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-05mb/intel/adlrvp: Add probed fw_configs to SMBIOS OEM stringsAnil Kumar
This feature was added in ADL-M RVP for discovering correct audio topology using OEM string e.g., "ADL_MAX98373_ALC5682I_I2S" for discovering boards having audio expansion card Bug=None Test= With CBI FW_CONFIG set to 0x100 localhost /home/root # dmidecode -t 11 Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x0009, DMI type 11, 5 bytes OEM Strings String 1: ADL_MAX98373_ALC5682I_I2S Change-Id: I05887d9d654eae6d9d2da731d8ab4cf4a05c287f Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55368 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-05mb/intel/adlrvp_m: Enable SaGv supportBora Guvendik
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I80f11b8f0c2a1fdccbc322c3c4783c61684ff37a Reviewed-on: https://review.coreboot.org/c/coreboot/+/55634 Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `VARIANT_DIR` onceAngel Pons
Specify the type of the `VARIANT_DIR` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: Iea2f992a59e41e00fec3cdc9d6a13b5f3ab0a437 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56558 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `OVERRIDE_DEVICETREE` onceAngel Pons
Specify the type of the `OVERRIDE_DEVICETREE` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I4cbf4e318a30f0cf75aa8690e7454b9caa115c9d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56556 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `DEVICETREE` onceAngel Pons
Specify the type of the `DEVICETREE` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: If68f11a5ceaa67a3e8218f89e1138c247ebb9a25 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56555 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `MAINBOARD_PART_NUMBER` onceAngel Pons
Specify the type of the `MAINBOARD_PART_NUMBER` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I3692f9e82fe90af4d0da1d037018a20aa1b45793 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56554 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `MAINBOARD_DIR` onceAngel Pons
Specify the type of the `MAINBOARD_DIR` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: If1cc538b0c4938dac193699897b690e402b3c1e8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56553 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21mb/intel/adlrvp: Enable I2S audio codecs on ADL-M RVPAnil Kumar
- Add configurability using FW_CONFIG field in CBI, to enable/disable I2S codec support for MAX98373 codecs - AUDIO=ADL_MAX98373_ALC5682I_I2S: enable max98373 codec using expansion board Bug=None Test=With CBI FW_CONFIG set to 0x100, check I2S audio output on expansion card Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: If2649647e58c5f30e2b539d534adf2a4e68f4fda Reviewed-on: https://review.coreboot.org/c/coreboot/+/52221 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-19mb/{google, intel}: Make use of `cpu/intel/cpu_ids.h'Subrata Banik
Remove inclusion of mp_init.h for getting CPUIDs and use dedicated cpu_ids.h file in SoC directory. Change-Id: I411f4f2c237a9e2d39038ee30f2957698ee053bd Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-07-17mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(906a0h) siliconSridhar Siricilla
The patch updates PMC Descriptor which is part of Descriptor Region if system equipped with Alder lake A0 silicon. This change allows to use unified Descriptor Region for Alder lake A0(CPU ID:0x906a0) and B0 (CPUD ID:0x906a1) silicons. The change has to be reverted before EOM is enableda on the system. BUG=B:187431859 TEST=Verified PMC Descriptor getting modified for Alder lake B0 silicon if not updated. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I2a1f60fda7575212bb694fc423bd229452515903 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-07-15mb/intel/adlrvp: Disable xDCI in devicetreeMonika A
Disable tcss_xdci as it is not used. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I94102240b13d2b96e0295f41bc2b0ba078faf342 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-07-12mb/intel/adlrvp_m: Enable EC software syncThejaswani Putta
This patch enables CONFIG_VBOOT_EARLY_EC_SYNC. EC software sync will be performed in romstage. BUG=None BRANCH=None TEST=Verify EC software sync works on adlrvp_m Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com> Change-Id: I3a13094e5da2f672a6789fe86528de44e909045e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56154 Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-05mb/intel/adlrvp_m: Remove ASL code and enable dynamic SSDT creation for ↵Varshit B Pandya
camera ACPI This change updates device tree to enable SSDT generation for world facing camera and user facing camera for ADLRVP. Also reverts DSDT changes related to both camera. TEST=Build and Boot aldrvp check i2c enumeration and output of media-ctl Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I39f82dc9eb91496d80479ae3f59ca5e03402a599 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-07-05mb/intel/adlrvp: Remove ASL code and enable dynamic SSDT creation for camera ↵Varshit B Pandya
ACPI This change updates device tree to enable SSDT generation for world facing camera and user facing camera for ADLRVP. Also reverts DSDT changes related to both camera. TEST=Build and Boot aldrvp check i2c enumeration and output of media-ctl Compared SSDT with this patch against DSDT without this patch, they are same Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I08834bbcf80dc46737de07f69a2402ed6bf93d4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-07-05mb/intel/adlrvp: Update the FIVR configurationsV Sowmya
This patch sets the optimized FIVR configuration for adlrvp cutomized based on the pnp measurements to achieve the better power savings in sleep states. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 states. * Update the supported voltage states. * Set the ICC max to 500mA for v1p05 and vnn. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I83e6910502d5cf9d4c26fa581272f59ac483ae19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-06-28mb/intel/adlrvp_m: Enable TCSS USB ports device pathBernardo Perez Priego
This provide a more consistent mechanism to enable corresponding USB TCSS port. BUG=b:182960979 TEST=Boot device, Type C port should operate correctly. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Iadc0df2e6e19a5afacbb7db1ae0bc7546dbcdc1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/55772 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-24soc/intel/alderlake: Update mainboard_memory_init_params() argumentSubrata Banik
This patch updates mainboard_memory_init_params() function argument from FSPM_UPD to FSP_M_CONFIG. Ideally mainboard_memory_init_params() function don't need to override anything other than FSP_M_CONFIG UPDs hence passing config block alone rather passing entire FSP-M UPD structure. Change-Id: I238870478a1427918abf888d71ba9c9fa80d3427 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-22mb/intel/adlrvp: Update Mainboard part number and VendorMeera Ravindranath
dmidecode output should match with the CrOS kernel updated string. TEST=dmidecode grep "Manufacturer" = Intel Corporation dmidecode grep "Product name" = Alder Lake Client Platform Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I7cce423de624e7056e88b52a1443c554fd9123bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/51408 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17mb/intel/adlrvp_m: Remove DP_HPD 1 & 2 definition from devicetreeBernardo Perez Priego
Due to latest corresponding UPD filling implementation, this is not required. This patch fixed the brokenness caused by Commit hash b10afbd2e2a8326fb21dc726a6c2bd53b06eb010. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I49e434f7bbafcb148e82202697e87c3e4268d7b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-17mb/intel/adlrvp_m: Configure DP_HPD as PAD_NC and disable DdiPortHpdBernardo Perez Priego
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function (NF1), this causes redundancy with legacy HPD interruption. This change configures GPP_A19 and GPP_A20 to be no connection and disables DdiPort1Hpd and DdiPort2Hpd. BUG=None TEST=Boot to kernel and verified no kernel HPD pins assertion message. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I80ef40a1aca19cd6ad56219175d2fd40890a393d Reviewed-on: https://review.coreboot.org/c/coreboot/+/55548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sanrio Alvares <sanrio.alvares@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2021-06-16soc/intel/alderlake/romstage: Update display UPDs based on InternalGfxSubrata Banik
Disable all display related UPDs if IGD is not enabled as FSP don't need to perform display port initialization while IGD itself is disabled else assign UPDs based on devicetree config. TEST=Dump FSP-M display related UPDs with IGD enable and disable to ensure patch integrity. Change-Id: I0479904141dfc5e707679109aa18b7ef4264cf96 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14mb/intel/adlrvp: Add board id for MR DDR5 SKUDeepti Deshatty
Add support for Maple Ridge DDR5 SKU with boardid 0x16 TEST=Verified build for ADL-P Chrome RVP Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com> Change-Id: I9f0e9072f5866b60fb8463bb90f61915c78568db Reviewed-on: https://review.coreboot.org/c/coreboot/+/52760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.corp-partner.google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2021-06-07soc/intel/adl: Add SKU specific power limits supportSumeet Pawnikar
Power limits (PL1 and PL2) depend on the specific SKU of the CPU. By expanding the SoC chip config power_limits_config member to an array indexed by ADL_*_POWER_LIMITS_*_CORE macros, the appropriate power limits are applied. Using this the correct set of power limits are being selected from the array based on system agent PCI ID. Based on this, chipset.cb file contains the set of power limits being used by varieties of ADL boards. These power limit values are as per document 619501. BUG=None BRANCH=None TEST=Built and verified the following console output on below boards On adlrvp (482): CPU PL1 = 28 Watts CPU PL2 = 64 Watts On adlrvp (682): CPU PL1 = 45 Watts CPU PL2 = 115 Watts On brya (282): CPU PL1 = 15 Watts CPU PL2 = 55 Watts Change-Id: Ic1676e2b4d611cdc85e770f131d5b6d5ecd180be Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
2021-06-05mb/intel/adlrvp: Use device aliasesSubrata Banik
Use the device aliases provided by alderlake chipset.cb instead of the raw pci device+function. Take advantage of the default states in chipset.cb and only list the devices that are enabled for all different adlrvp boards. TEST=Dump devicetree device enable list without and with this CL, no difference observed. Change-Id: Ib9e82d953416c076588974f3167d00ae96f01bb5 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55205 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-05mb/intel/{adlrvp, sm}: Remove ADL-S devices from ADL-P/M devicetree.cbSubrata Banik
Change-Id: I095394d9a79506346b8464c850d03cbd8ce2b812 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55221 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-01mb/intel/adlrvp_m: Enable LTR for PCIEBernardo Perez Priego
BUG=none TEST=Use command $ lspci -vv LTR+ is listed on DevCtl2 Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: If65d08a46b9e7304fbe4b92b7f1e6d4e08c599e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54492 Reviewed-by: Ryan A Albazzaz <ryan.a.albazzaz@intel.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-30mb/intel/adlrvp_m: add ec device entry to devicetreeBora Guvendik
TEST=Boot to OS and verify acpi tables. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I3c78ac44afa3515acef9ea2d59f22f95e6b45e90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54490 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: John Zhao <john.zhao@intel.corp-partner.google.com> Reviewed-by: John Zhao <john.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28mb/intel/adlrvp_m: Disable unused TBT ports from device treeBernardo Perez Priego
These PCIe and DMA ports are not available for adlrvp_m. BUG=none TEST=Boot device Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Ic568c692fbb82fb3fc70c0cafc2328f8fa2cd74d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-18mb/intel/adlrvp: Disable EC sync for adlrvp_ext_ecMaulik V Vaghela
Since we have TPM disabled on ADLRVP, if we enable EC sync, it keeps rebooting with hash error. Change-Id: I62a4fceb83dc6b20f699b4662e8f421aadafdee5 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-05-12mb/intel/adlrvp_m: Program CPU PCIE RP GPIOs in early GPIOBora Guvendik
We need to configure CPU PCIE root port related gpios in early boot block stage for CPU root ports to work due to the dependency on FSP-M PCIe configuration. Since we're removing this programming from FSP, coreboot needs to take care of programming this GPIOs. Also we need to enable virtual wire messaging for native gpios for CPU PCIE root ports. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I27c898943471d834bd82e3c7e8b36cceb12de099 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52865 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-12mb/intel/adlrvp: Fill CmdMirror and DqDqsRetraining for ADLRVPMaulik V Vaghela
ADL-M LP4 RVP has command mirror enabled and we need to fill correct value of this UPD to pass the MRC. Also, Value of TxDqDqsRetraining is set to 1 by default and we need to disable it for only ADL-M LP5 RVP. BUG=None BRANCH=None TEST=UPD values has been pass correctly and MRC passes on LP4/LP5 board Change-Id: I3e16b9a3d3e6a92dacba9d38782df408596ed5e1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-07mb/intel/adlrvp: Program CPU PCIE RP GPIOs in early GPIOMaulik V Vaghela
We need to configure CPU PCIE root port related gpios in early boot block stage for CPU root ports to work. Since we're removing this programming from FSP, coreboot needs to take care of programming this GPIOs. Also we need to enable virtual wire messaging for native gpios for CPU PCIE root ports. Change-Id: Ieda6b6c31ce5bd5e84e4efe544bfc659283ce6f1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52270 Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06mb/intel/adlrvp_m: Disable Type-C xDCIBernardo Perez Priego
Disabling this pci 0d.1 device since it is not required. TEST= Boot to OS. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Iccdf38111e3961ba887829abfa4146a9b37df9be Reviewed-on: https://review.coreboot.org/c/coreboot/+/52744 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-05mb/intel/adlrvp: Enable support for Chrome OS mode switchesAnil Kumar
Branch=none Test=build and boot ADL-M RVP. Test recovery mode using servo command dut-control power_state:rec Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I771f0ef14b1c273f9d1af22c96de0eabd08e9a8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52614 Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-03mb/intel/adlrvp: Increase RO/RW region size in chromeos.fmdMaulik V Vaghela
While building adlrvp board with chromeos.fmd and adding all chromeos related artifacts, RO region is running out of space. Also, we need to increase RW region size to accommodate all binaries and artifacts. Aligning chromeos.fmd with Brya will help in solving this issue, thus aligning chromeos.fmd with Brya. BUG=b:184997582 BRANCH=NONE TEST=Code compiles fine and able to boot adlrvp platform Change-Id: I644e2e5ba06d2b816d413a7cc9f5f248d8a6fee8 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52732 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-29mb/intel/adlrvp: Configure TCSS, BT and WiFi related GPIOsFrancois Toguo
This CL configures TCSS, BT and WiFi related GPIOs based on schematics. BUG=None TEST= BT, WIFI and TCSS functionalities validated with this change. Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Change-Id: Ie0e665275c281fcbad0d02ceb723cea433637711 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50516 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28mb/intel/adlrvp_m: Add UART0 GPIO config for ADL-M RVPAnil Kumar
This patch adds UART0 config in early GPIO table Branch=None Test=Build coreboot and boot on ADLRVP-M board. Check UART logs Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: Ic0cc955a02936b74f44fed55a9f4b8054646681a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52201 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23mb/intel/adlrvp: Enable DPTF functionality for adlrvp boardSumeet R Pawnikar
Enable DPTF functionality for Alder Lake based adlrvp board BRANCH=None BUG=None TEST=Built and tested on adlrvp board Change-Id: I319bb0ddb9cd9bbe48c8ee09c2742a78da230b7b Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-23mb/intel/adlrvp_m: Enable bluetoothBora Guvendik
Enable bluetooth on ADL-M RVPi. Remove 10.2 pci entry since it is not used anymore. BUG=none TEST=Check lsusb to see if BT enumerated. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I39e77dbb619235129ed894d20f24956242de3aa9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-22soc/intel/alderlake: Add enum for HDA audio configurationSugnan Prabhu S
This change adds an enum to configure the audio related UPDs used for configuring the audio over HDMI/DP and rename a variable for better readability. TEST=On shadowmountain audio sound cards are detected and listed by the Linux kernel. Audio playback and capture is working fine. Change-Id: I2834d6f4ce1651a609c5563af375f6e365d931fa Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-22soc/intel/alderlake and mb: Drop PchHdaAudioLink*Enable UPDs from chip.hFurquan Shaikh
FSP uses PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs to configure GPIO pads for audio. However, mainboard is expected to perform all GPIO configration in coreboot and hence these UPDs must be set to 0. There is no need to expose these UPDs in chip.h and provide mainboard an option to set these in devicetree. This change drops PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs from chip.h and the corresponding devicetree in mainboards. Currently, shadowmountain already set these UPDs to 0, whereas adlrvp set these to 1. But all the ADL boards are correctly configuring the GPIO pads for audio, so this change should not impact audio for any of these boards. BUG=b:183482000 TEST=adlrvp and shadowmountain build successfully. Change-Id: I90e4eb5cc242a789800f4c9f8c71e9d8c8a2becf Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52559 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21soc/intel/alderlake: Drop unused `PrmrrSize` from devicetreeAngel Pons
The `PrmrrSize` FSP-M UPD is set using `get_valid_prmrr_size()`. As the devicetree option's value is not used anywhere, drop it. Change-Id: Ib6fb77b03a4648adbd8b23c160cfba94d142a2d2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-16mb/intel/adlrvp: Enable ALC711 over SNDW0Sridhar Siricilla
The patch enables ALC711 over SNDW0. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I43891b94728c8f2d644e14da11946fea3e4515aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/50022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-04-12mb/*: drop LPC generic range for port 80Michael Niewöhner
Port 80 (actually 0x80-0x8f) is a fixed I/O range and thus does not have to be set up as generic range. Drop the entries from the devicetrees. Change-Id: I8a54d3c35a321a2d57bd846662f7339eff53e5a8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-04-09mb/intel/adlrvp: Enable HECI1 communicationSridhar Siricilla
The patch enables HECI1 interface to allow OS applications to communicate with CSE. BUG=None TEST=Build and boot ADLRVP. Run lspci and check pcie device (00:16.0) Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I34ff842481bdfc7933a76555ff0fd70f4fbbb9a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-04-06mb/intel/adlrvp: Update iDisp Link UPD settingsFrancois Toguo
This changes updates the iDisp-Link T-mode to 8T required for ADL-M. The update is made because the HW on ADL now supports 8T mode. BUG=None TEST= build and boot ADL-M RVP and verify HDMI/DP audio playback. Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Change-Id: I9d0bf7dc76348f7e184e8496f042badc30bf3211 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51353 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06mb/intel/adlrvp: Enable Camera in ADL-M RVPVarshit Pandya
1. Configure Power Enable, Reset and Clock GPIO for both camera 2. Use same ASL code as ADL-P RVP Configure RST, PWR_EN and IMGCLKOUT signals for WFC and UFC TEST=Build, Boot and Verify streaming in both Camera Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com> Change-Id: I70636eaa8d9bdf23d649e811b3ff4f33b1bc604e Reviewed-on: https://review.coreboot.org/c/coreboot/+/50265 Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-02mb/intel/adlrvp: Update VBT filenamesTim Wawrzynczak
These files were just renamed to put `adlrvp` in between `vbt` and the memory technology type. Change-Id: Icefbac462d0ec9c660541e9cf44686d6dcf82dfd Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52032 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28mb/intel/adlrvp_m: Enable ADL-M RVP LP5 memory configurationMaulik V Vaghela
List of changes: 1. Add correct board Id for ADL-M LP5 configuration 2. Add spd hex files for LP5 Micron part 3. Update memory.c file with correct Dq-dqs and byte mapping for LP5 BUG=None BRANCH=None TEST=Build is successful for ADL-M RVP Change-Id: I0bbd3f5b56bf7fbe918cc599d32a01dcae896ddd Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2021-03-28mb/intel/adlrvp_m: Enable ADL_M RVP LP4 memory configurationMaulik V Vaghela
List of changes: 1. Add board Ids for ADL-M LP4 configuration 2. Add spd hex files for LP4 configuration 3. Update memory.c file with correct Dq-dqs and byte mapping for LP4 BUG=None BRANCH=None TEST=Build and boot is successful for ADL M LP4 RVP Change-Id: Id817faee3fff2a8a911ebda35774dfb6ddc5524b Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50257 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28mb/intel/adlrvp: Configure GPIOs for ADLRVP-MVarshit Pandya
List of changes: 1. Add separate file for ADL-M GPIOs 2. Configure GPIOs as per the schematics of ADL-M RVP TEST=Able to build ADL-M Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com> Change-Id: I03a532f69f42db723b976a0f7b0acf6f4b98e354 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2021-03-28mb/intel/adlrvp: Enable CSE Lite SKUSridhar Siricilla
During the initial phases, the development and validation teams have to deal with both Consumer SKU and Lite SKU firmware. Having the support for CSE Lite enabled by default in coreboot helps in integrating both the SKUs. With this we only have to interchange the CSE region in the full BIOS image without having to worry about Kconfigs. Eases the build and integration flow. TEST= Built and booted on ADL-P LP4 RVP Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ia92c7b71c69a23104ace9fc53fd39f01120fa751 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51567 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-27mb/intel/adlrvp: Allow GPIO PM override to disable dynamic GPIO PMSubrata Banik
This patch allows overriding GPIO PM miscconfig register for each GPIO community to avoid dynamic clock gating. TEST=Dump GPIO Community MISCCFG register to ensure all Bit [7:0] are set to '0'. Change-Id: I9aca9cb0641e2731c028ea5ed76c563da3400b74 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-26mb/intel/adlrvp: Remove static VBT stitchingMaulik V Vaghela
Currently, we used to stitch extra VBT files to ADLRVP build using Makefile. With enablement of emerge build, we should be able to integrate more than 1 VBT binaries using ebuild. This removing these lines to avoid compilation issues in emerge builds BUG=None BRANCH=None TEST=Check if compilation passes on emerge build. Stitched additional VBT files using emerge and checked that coreboot picks up correct VBT. Change-Id: I69f1cc6c07415515ff85180fdd7cc5de11b4d805 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-03-26soc/intel/alderlake: Add provision to override Rcomp settingsSubrata Banik
Add function to allow overriding the RcompResistor and RcompTarget UPDs from mainboard if required. Mainboard users can pass required rcomp from memory.c file. Refactor ddr_config structure to take out rcomp related variable outside for all memory type to override if required. BUG=b:182772421 TEST=Able to override the default RcompResistor and RcompTarget values. Change-Id: Ie8528bbf0517728534d47f9adaabfc9a2c469609 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-26soc/intel/alderlake: Align RcompResistor definition as per MRCSubrata Banik
List of changes: 1. Alder Lake MRC is expecting a RcompResistor value of word width. Reference RCOMP resistors on motherboard are ~ 100 Ohms but coreboot is passing an array of RcompResistor which is not completely in use. Note: Rcomp resistor value represents rcomp resistor attached to the DDR_COMP pins on the SoC. 2. Also, remove usage of '&' with memcpy the required value into RcompTarget array. 3. Also, update RcompResistor value for ADLRVP. BUG=b:183341229 TEST=Enable FSP debug log to verify the override value for RcompResistor is reflecting correctly. Change-Id: I69c7cec55b65036fc039c33374a3fd363ef7004e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-24mb/intel/adlrvp: Enable CnviBtAudioOffloadUsha P
This change enables CnviBtAudioOffload. FSP is invoked to configure BT over USB and BT I2S pins for cAVS connection. BUG=None TEST=Verified BT offload working on ADL RVP Signed-off-by: Usha P <usha.p@intel.corp-partner.google.com> Change-Id: I1185a6c2295bae7d469be4da86502506adbeb8cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/51032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-03-15mb/intel/adlrvp: Disable non-existing BT PCI interface and add BT flagCliff Huang
Remove the CNVi Bt PCI config and add Bt flag. There is no PCI host interface in this version of CNVi. TEST: BT is checked using 'lsusb -d 8087:0026' from OS. Change-Id: I17c3e2761f91fb397d140d1954b6d4b451c4c603 Signed-off-by: Cliff Huang <cliff.huang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUsMeera Ravindranath
Add support to pick the right vbt from cbfs according to SKU-ID. Change-Id: I8795cc67d87429eddb31328f1e2a90c346b53533 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15mb/intel/adlrvp: Select ADL_ENABLE_USB4_PCIE_RESOURCESTim Wawrzynczak
This change select the Kconfig to pre-allocate the Intel-recommended bus and memory resources per-PCIe TBT root port for the adlrvp mainboard. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ic56ebab02e50a466662a07d122d8f40eaf16b54b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51461 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-12mb/intel/adlrvp: do UART pad config at board-levelMichael Niewöhner
UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Thus, add the corresponding pads to the early UART gpio table for the board as a first step. Common UART pad config code then gets dropped in CB:48829. Also switch to `bootblock_mainboard_early_init` to configure the pads in early bootblock before console initialization, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: I55815a824ea3a77e6e603ba4beb17457f37c48f5 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-03mb/*/*: Don't select PCIEXP_HOTPLUGArthur Heymans
PCIEXP_HOTPLUG has a prompt and as such is not supposed to be forced. Just change the default value to 'y'. Change-Id: Ie4248700f5ab5168bff551b740d347713273763c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-27vboot: update GBB flags to use altfw terminologyJoel Kitching
As per CL:2641346, update GBB flag names: GBB_FLAG_FORCE_DEV_BOOT_LEGACY -> GBB_FLAG_FORCE_DEV_BOOT_ALTFW GBB_FLAG_DEFAULT_DEV_BOOT_LEGACY -> GBB_FLAG_DEFAULT_DEV_BOOT_ALTFW BUG=b:179458327 TEST=make clean && make test-abuild BRANCH=none Signed-off-by: Joel Kitching <kitching@google.com> Change-Id: I0ac5c9fde5a175f8844e9006bb18f792923f4f6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-24mb/intel/adlrvp_m: Add initial code for adl-m variant boardVarshit Pandya
List of changes: 1. Add mainboard Kconfig to Kconfig.name files 2. Handle mainboard names in Kconfig file for adlrvp 3. Created a new devicetree.cb for Adlrvp-m. 3. Add override devicetree for ADL-M RVP. 4. Configure proper PCI and USB ports as per schematics for ADL-M BUG=None BRANCH=None TEST=Able to build ADL-M RVP variants adlrvp_m and adlrvp_m_ext_ec. Signed-0ff-by: Maulik Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com> Change-Id: I997b89ba87fb03dfa6a836caec51efd05baa2e8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/49871 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22mb/intel/adlrvp: Add support for LP5 SKU with boardid 0x17Subrata Banik
Change-Id: I4f17f9d58d2c07264d7d8e83a6fce832c9304c24 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-17mb/intel/adlrvp: Fix incorrect SPD address issue on DDR4/DDR5Subrata Banik
Assign 7-bit address of the targeted slave SPD. TEST=Able to read correct SPD data from SMBUS. Change-Id: If24e61b583638be7c055541c6eb126da28b542f6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-17mb/intel/adlrvp: Early program SMBUS CLOCK and DATASubrata Banik
TEST=Ensure SMBUS CLK/DATA GPIO is in NF1. Change-Id: Id615462cc21fc24e7ec6ef16274d784d41bd9bd4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-16mb/{intel,prodrive,protectli}: Remove unused <string.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<' Change-Id: Id2aa085a4762355d9fb1628df40f7b43fbc81fc0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-11src: Remove unused <arch/cpu.h>Elyes HAOUAS
Change-Id: I1112aa4635a3cf3ac1c0a0834317983b4e18135a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10mb/intel/adlrvp/bootblock.c: Remove unused includesElyes HAOUAS
Change-Id: I73234da6e77f83c6aeb5c40cf6ffdb3cccc4074c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-05soc/intel/alderlake: Refactor PCIE port configEric Lai
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b Reviewed-on: https://review.coreboot.org/c/coreboot/+/48340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-04src: Remove unused <cbfs.h>Elyes HAOUAS
Change-Id: Idc11f1e131df2e01864fedac864bda5e11f2d17b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-04mainboards: Remove default CHROMEOS=yKyösti Mälkki
Even the boards with MAINBOARD_HAS_CHROMEOS need to be build-tested with CHROMEOS=n. Change-Id: I16fcf62a23dae1b21c77cee275c867f9c1de893b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-01soc/intel/alderlake: Create separate Kconfig for CLKSRC and CLKREQSubrata Banik
As per Hardware Architecture Specification (HAS) ADL-P has 7 CLKSRC and 10 CLKREQ (7 SRCCLK is internal and 3 SRCCLK from external CLK chip). ADL-M has 6 SRCCLK and CLKREQ (no external CLK chip). Change-Id: I7d223c165f819669722cbc80245fa8ec20372352 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50130 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30mb/intel/adlrvp: Remove unnecessary whitespaceSubrata Banik
Change-Id: I46af3e789de10ca6951b9e17f286c094c08a477f Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-28mb/intel/adlrvp: Configure SATA DEVSLP as per latest schematicsSubrata Banik
1. GPP_E5 => Remove unused GPIOs 2. GPP_H12, GPP_H13 => Program the correct Native Functions for GPIO Change-Id: I588a8c1153eaa1bf818a081c6c5d18a669017d95 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-28ACPI: Move include for <vc/google/chromeos.asl>Kyösti Mälkki
Change-Id: I4356a8bda71e84afe8c348d366479c5006bf2459 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49796 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28mb/intel/adlrvp: Remove ClkReq assignment for RP8Subrata Banik
CLKSRC6 for RP8 is free-running CLK hence ClkReq is not required. TEST=Able to detect PCIe SD card over x1 slot. Change-Id: I550d5be9cc7566708b0b86fcd1da833bc4bc828f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-27ACPI: Add top-level ASLKyösti Mälkki
Objects that are created with acpigen need to be declared with External () for the generation of dsdt.asl to pass iasl without errors. There are some objects that are common to all platforms, and some that should be declared only conditionally. Having a top-level ASL helps to achieve this. Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-25soc/intel/adl and mb/intel/adlrvp: Use the newly added meminit block driverFurquan Shaikh
This change uses the newly added meminit block driver and updates ADL SoC and mainboard code accordingly. BUG=b:172978729 Change-Id: Ibcc4ee685cdd70eac99f12a5b5d79fdbaf2b3cf6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-01-24arch/x86: Use wildcard for mb/smihandler.cKyösti Mälkki
Change-Id: I306f8cd74af62c0cd30f445d20c47f774f122481 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49247 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21mb/intel/adlrvp: Add PRESERVE to UNIFIED_MRC_CACHESubrata Banik
This patch preserves MRC training data across FW update. Change-Id: I6b7273471e4fc9dc25eac80904e012f86a981836 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49681 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21mb/intel/adlrvp: Remove redundant HAS_RECOVERY_MRC_CACHE KconfigSubrata Banik
HAS_RECOVERY_MRC_CACHE is already part of CHROMEOS hence remove redundant Kconfig. Change-Id: Ia55b587d77ca5be2a8ae701a3ab95cfebe8627db Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-10mb/intel/adlrvp: Update GPIOs as per latest schematicsSubrata Banik
1. GPP_D8, GPP_H23 => Remove unused GPIOs 2. GPP_E18 .. GPP_E22 => Program the correct Native Functions for GPIO Change-Id: Iedb1f8fbf5f96a9617b72ba1a6419e3fd4e331b4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49260 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10mb/intel/adlrvp: Fix FW download failed for PEG 060, 010Subrata Banik
Enable PCIE RP1 to fix DEKEL FW download failed for x4 controller (PEG 0:6:0). Enable PCIE RP3 to fix HSPHY FW download failed for x8 controller (PEG 0:1:0) BUG=b:176940923 TEST=No FSP error seen while loading DEKEL, HSPHY FW. Change-Id: I3cd8cba02a96185803a0c0d442f3d6aa495d2642 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-10soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPsSubrata Banik
List of changes: 1. Create new Kconfig MAX_CPU_ROOT_PORTS and MAX_PCH_ROOT_PORTS as per EDS. 2. Add new chip variable to enable/disable CPU PCIE RPs from mainboards. 3. Rename PcieRpEnable to PchPcieRpEnable. 4. Enable CPU RPs as below in mainboard devicetree.cb RP1: PEG60 : 0:6:0 : CPU SSD1 RP2: PEG10 : 0:1:0 : x8 CPU Slot RP3: PEG62 : 0:6:2 : CPU SSD2 Change-Id: I92123450bd7cfb2e70aae8de03053672a7772451 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49136 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07mb/intel/adlrvp: Fix building with CONFIG_CHROMEOS unsetMatt DeVillier
Make GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC depend on VBOOT, rather than force-select it. Change-Id: I0ec418d4182865636b6350f1ee151420d8e02c33 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-12-23mb/intel/adlrvp: Make SI_ALL region within 16MiBSubrata Banik
TEST=Able to build and boot ADLRVP. Change-Id: I93da53f8835e0eec4cf4e78daab26332fd55d334 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-17mb/intel/adlrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 portsV Sowmya
This change enables PCIEXP_HOTPLUG to support resource allocation for TCSS TBT/USB4 ports. Referred from TGLRVP -> https://review.coreboot.org/c/coreboot/+/41543 Change-Id: I5f883dac0d7e5fa84ad2e1683f84c933a90cea51 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-12-12mb/intel/adlrvp: Make CLKSRC and CLKREQ proper for PCIE RP8Subrata Banik
1. Make CLKSRC -> 7 and CLKREQ -> 6 2. CLK 6 is using free running CLK 3. Make LAN CLK 7 as unused as GbE is disable TEST=Able to detect PCIE SD card on 0x1 slot. Change-Id: I7fbde9492a0c59fc76931bfb7c9522d4f208ebb0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48449 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09mb/intel/adlrvp: Add PMC.MUX.CONx device config for Conn2V Sowmya
This patch adds the PMC MUX and CONx devices for adlrvp for conn2. BUG=b:170607415 TEST=Built and booted adlrvp. Verified the PMC.MUX CONx objects in SSDT tables. Change-Id: I52afbd429750cfa416f4ed93aeb1be590f8c3a5c Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48230 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-07mb/intel/adlrvp: Remove GPP_E0Meera Ravindranath
Remove the unused UART_BT_WAKE GPIO as BT is over USB. Change-Id: I638b4528fa5c4c378a1e8ff7bb88546da1513df2 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-12-02mb/intel/adlrvp: Replace tab by white space in devicetreeMeera Ravindranath
Change-Id: I928b4528fa5b4c378a2e8ff7bb88547da1413df2 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48213 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-01mb/intel/adlrvp: Remove unused EC_SYNC_IRQ GPIO on ADLRVPSubrata Banik
As per latest schematics GPP_A15 is not used for EC_SYNC_IRQ hence remove the unused GPIO. Wrong GPIO configuration is causing platform reboot issue on ADLRVP with Chrome SKU. Change-Id: I704cd722683258c80197d8872d3bdaafb7c923dc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-12-01mb/intel/adlrvp: Add ASL support for WFC annd UFCVarshit Pandya
1. Add 2 ports and 2 endpoints 2. Add support for OVTI5675 WFC Cam is on I2C5 and UFC is on I2C1 BUG=None BRANCH=None TEST=Build and Boot adlrvp board and able to capture image using camera. Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com> Change-Id: I6d2a4fdca99354d1b6977233c70ccd950c99d8a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47497 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-01mb/intel/adlrvp: Configure Camera related GPIO as per schematicsVarshit Pandya
Configure RST and PWR_EN signals for both WFC and UFC Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com> Change-Id: Ie416da373756b1c73472b8572f87930965a3d6ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/47496 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-01mb/intel/adlrvp: Update GPIO configuration as per schematicsVarshit Pandya
Configure I2C related GPIO as per ADL-P schematics. This is based on Revision 0.974 of schematics. Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com> Change-Id: I76e1207cb31bed10b6e9fbeb2456b6feec42f97e Reviewed-on: https://review.coreboot.org/c/coreboot/+/47495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-12-01mainboard/intel/adlrvp: Enable PCH PCIe device over x1 slotSubrata Banik
List of changes: 1. Enable Root Port 8 aka 0:0x1c:7 2. Assign free running clock for RP8 3. Apply W/A to get card detected on x1 slot - Drive OEB 7:GPP_A7 and OEB 6:GPP_E5 low TEST=Able to detect PCIe SD card over x1 slot localhost ~ # dmesg | grep mmc [ 3.643755] mmc0: SDHCI controller on PCI [0000:02:00.0] using ADMA [ 3.825201] mmc0: new ultra high speed DDR50 SDHC card at address 17f8 [ 3.835452] mmcblk0: mmc0:17f8 SE16G 14.4 GiB [ 3.849158] mmcblk0: p1 Change-Id: Ibea37b8de4dd020ff0108ec90ea6f8bcfaa4fb17 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48080 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 02:16:53 +0000