diff options
| author | V Sowmya <v.sowmya@intel.com> | 2021-06-21 08:59:43 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-07-05 10:47:31 +0000 |
| commit | 34764100393544b0b9dddf4019b30c178a704195 (patch) | |
| tree | 34e1e957cbc7bcccf35e3260b3f9793bf7e17400 /src/mainboard/intel/adlrvp | |
| parent | 418d37e68956b13ea4e8abff8bf6ed30c0059bcd (diff) | |
mb/intel/adlrvp: Update the FIVR configurations
This patch sets the optimized FIVR configuration for adlrvp cutomized
based on the pnp measurements to achieve the better power savings in
sleep states.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
S4, S5 states.
* Update the supported voltage states.
* Set the ICC max to 500mA for v1p05 and vnn.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I83e6910502d5cf9d4c26fa581272f59ac483ae19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/mainboard/intel/adlrvp')
| -rw-r--r-- | src/mainboard/intel/adlrvp/devicetree.cb | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index be2659293f..affa6f8384 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -199,6 +199,21 @@ chip soc/intel/alderlake }, }" + # FIVR configurations + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, + .v1p05_voltage_mv = 1050, + .vnn_voltage_mv = 1050, + .vnn_sx_voltage_mv = 1050, + .v1p05_icc_max_ma = 500, + .vnn_icc_max_ma = 500, + }" + device domain 0 on device ref pcie5 on end device ref igpu on end |