diff options
| author | Bernardo Perez Priego <bernardo.perez.priego@intel.com> | 2021-05-24 14:32:19 -0700 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-05-28 04:53:50 +0000 |
| commit | e3a079cff89b8101d0b0a3a77938bd1c6ddaf752 (patch) | |
| tree | a577be1070ba703b42a2adddfdb3f74e8039c801 /src/mainboard/intel/adlrvp | |
| parent | c2c4a002ac3c90b9a0e99340835b5a42205bad9f (diff) | |
mb/intel/adlrvp_m: Disable unused TBT ports from device tree
These PCIe and DMA ports are not available for adlrvp_m.
BUG=none
TEST=Boot device
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Ic568c692fbb82fb3fc70c0cafc2328f8fa2cd74d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/intel/adlrvp')
| -rw-r--r-- | src/mainboard/intel/adlrvp/devicetree_m.cb | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index 51d97bcbe5..9c66bd73fd 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -158,15 +158,15 @@ chip soc/intel/alderlake device pci 06.2 on end # PEG62 device pci 07.0 on end # TBT_PCIe0 device pci 07.1 on end # TBT_PCIe1 - device pci 07.2 on end # TBT_PCIe2 - device pci 07.3 on end # TBT_PCIe3 + device pci 07.2 off end # TBT_PCIe2 + device pci 07.3 off end # TBT_PCIe3 device pci 08.0 off end # GNA device pci 09.0 off end # NPK device pci 0a.0 off end # Crash-log SRAM device pci 0d.0 on end # USB xHCI device pci 0d.1 off end # USB xDCI (OTG) device pci 0d.2 on end # TBT DMA0 - device pci 0d.3 on end # TBT DMA1 + device pci 0d.3 off end # TBT DMA1 device pci 0e.0 off end # VMD device pci 10.0 off end device pci 10.1 off end |