coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-09-30	mb/intel/adlrvp: Update Rcomp target value for DDR4 RVP SKU	Subrata Banik
2021-06-14	mb/intel/adlrvp: Add board id for MR DDR5 SKU	Deepti Deshatty
2021-05-12	mb/intel/adlrvp: Fill CmdMirror and DqDqsRetraining for ADLRVP	Maulik V Vaghela
2021-03-28	mb/intel/adlrvp_m: Enable ADL-M RVP LP5 memory configuration	Maulik V Vaghela
2021-03-28	mb/intel/adlrvp_m: Enable ADL_M RVP LP4 memory configuration	Maulik V Vaghela
2021-03-26	soc/intel/alderlake: Add provision to override Rcomp settings	Subrata Banik
2021-03-26	soc/intel/alderlake: Align RcompResistor definition as per MRC	Subrata Banik
2021-02-22	mb/intel/adlrvp: Add support for LP5 SKU with boardid 0x17	Subrata Banik
2021-02-11	src: Remove unused <arch/cpu.h>	Elyes HAOUAS
2021-01-25	soc/intel/adl and mb/intel/adlrvp: Use the newly added meminit block driver	Furquan Shaikh
2020-12-01	mb/intel/adlrvp: Add support for LPDDR5	Sridhar Siricilla
2020-12-01	mb/intel/adlrvp: Refactor lpddr4_mem_config structure	Subrata Banik
2020-11-29	mb/intel/adlrvp: Disable dq_pins_interleaved for DDR4/5 RVP	Subrata Banik
2020-11-09	mb/intel/adlrvp: Replace if-else-if ladder with switch construct	Sridhar Siricilla
2020-11-08	mb/intel/adlrvp: Refactor ADLRVP code to get rid of 'variants/baseboard'	Subrata Banik