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Refer to brask board to add audio settings for gaelin.
BUG=b:253177160
BRANCH=firmware-brya-14505.B
TEST=Able to verify audio playback on gaelin with kernel v5.10.
Change-Id: Ibc8cacce6cb4b3e55fc7332bb9eb9ac20848fc5b
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Modify USB2.0 port[4] settings to support camera.
BUG=b:238252678
BRANCH=firmware-brya-14505.B
TEST=with brask overlay changes, camera in camera app works
Change-Id: I42325b75e129429ee451ded6a2086fd3808e581a
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Add new audio sku configure for Pujjo board.
BUG=b:260538412
TEST=Boot to OS on pujjo and check that audio are configured
based on fw_config.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Ia9ddc683945002a0b19efd67006e1983b2eb9f2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Instead of using a fake lapic device hook up the cpu cluster to chip
cpu/intel/model_206ax.
The lapic device is also not needed as the mp init will allocate it for
the BSP at runtime.
Change-Id: Id3b1c4ca027e2905535e137691c3e3e60417dbf3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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When retrieving the SKU id value through the sku_id() function in
mainboard_needs_pcie_init(), we only want the values in the lower 5
bits as we can only represent SKU id up to 27. Everything in the
higher bits should be masked out because they are not needed.
BUG=b:254281839
BRANCH=None
TEST=Make sure that NVMe is not initialized
Tested on a herobrine board with SKU id 0
Change-Id: I0e786ec392b5e1484cb2ff6d83a8d4fdd698950c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70164
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently, we are getting the sku id from the EC every time we call
the sku_id() function. However, this will never change so we only
need to retrieve it once. Inserting exit condition if sku id is
already set, then don't get it from the EC again.
Also, removing the ram_code function, which does nothing right now.
There is already a weak stub_function for this in
src/lib/coreboot_table.c that already does the same thing.
BUG=b:260740438,b:182963902
BRANCH=None
TEST=make sure image still boots to login on herobrine device
Change-Id: Ia787968100baf58a41ccce0cf95ed3ec9ce1758a
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
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Expand DPTC_INPUT macro to supoort 13 DPTC thermal table parameters for
dynamic table switching support.
BRANCH=none
BUG=b:232946420
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I6d6a00f0eca0b0941860b9bc75da41d7a10d60e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP
threshold.
FSP silicon discards the request if the Voltage Regulator or SoC does
not support the feature.
BUG:b:259057787
TEST:Verify that the feature is enabled by reading from pcode
No PnP regression observed
BRANCH=firmware-brya-14505.B
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I7e318534f1429af8ec06048430966344ddd346a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69579
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Jeremy Compostella <jeremy.compostella@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This only moves CPU configuration to a common place. Other PCI devices
can be done in follow-ups.
Change-Id: I9c5b6f25b779e28b6719cf70455ff0f1a916ad87
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56912
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch supports multiple camera modules based on FW_CONFIG.
BUG=b:251235140
TEST=Test the changes with ov2740/hi556 camera.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ib0a4f46d889e9f6c2898efee6825cf2d02252d87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jim Lai <jim.lai@intel.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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This patch enables crashlog for all brya projects.
BUG=b:190756531, b:259978562
BRANCH=None
TEST=emerge-brya coreboot chromeos-bootimage & ensure the crashlog
PCIe device 0xa.0 is enabled and intel-pmt kernel driver is
loaded.
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: Ib632c8ac9ea7a4f0e0b08b96eb149f8ef1386be0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68526
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This change disables unused PCIE RP8 and CLKSRC4. Without this change
sasukette cannot enter into s0ix properly.
BUG=b:259891452
TEST=Build and verified in sasukette
Change-Id: I61bcefa128d4f39613a760b647048f9e19e262c2
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add ACPI DmaProperty for ethernet devices.
BUG=b:259716145
TEST=Verified SSDT on google/osiris.
Before:
Scope (\_SB.PCI0.RP01)
{
Device (RLTK)
{
Name (_HID, "R8168") // _HID: Hardware ID
Name (_UID, 0xD0E889DD) // _UID: Unique ID
Name (_DDN, "Realtek r8168") // _DDN: DOS Device Name
Name (_ADR, 0x00000000) // _ADR: Address
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x07,
0x03
})
}
}
After:
Scope (\_SB.PCI0.RP01)
{
Device (RLTK)
{
Name (_HID, "R8168") // _HID: Hardware ID
Name (_UID, 0xD0E889DD) // _UID: Unique ID
Name (_DDN, "Realtek r8168") // _DDN: DOS Device Name
Name (_ADR, 0x00000000) // _ADR: Address
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x07,
0x03
})
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
Package (0x01)
{
Package (0x02)
{
"DmaProperty",
One
}
}
})
}
}
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I647593fd02644d30cd21b60d8305c0ec55dc64cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70017
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:259716145
TEST=TBD
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ifaa0912b38129ed2db01fb78ed39c0db89e746fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70018
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new ram_id:0100 for memory Samsung K3LKBKB0BM-MGCP.
Add new ram_id:0101 for memory Samsung K3LKCKC0BM-MGCP.
The RAM ID table has been assigned as:
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
H9JCNNNBK3MLYR-N6E 0 (0000)
MT62F1G32D4DR-031 WT:B 1 (0001)
H9JCNNNCP3MLYR-N6E 1 (0001)
MT62F2G32D8DR-031 WT:B 2 (0010)
H9JCNNNFA5MLYR-N6E 3 (0011)
K3LKBKB0BM-MGCP 4 (0100)
K3LKCKC0BM-MGCP 5 (0101)
BUG=b:254758998
BRANCH=None
TEST=FW_NAME=frostflow emerge-skyrim coreboot
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I8ff879ff7185f5a0ca1b9632820aba3b0f5d02c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
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Set Package Power Parameters from AMD DevHub document #57316.
"stapm_time_constant_s" = "200"
BRANCH=none
BUG=b:257187831
TEST=emerge-skyrim coreboot
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I15a69df1436aba05bc19eaffd79394e5ca9bdb3a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69565
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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The Skyrim devices share a common set of DPTC values to enable booting
with low/no battery. Rather than duplicating them in each variant's
overridetree.cb, move them into the baseboard/devicetree.cb.
BUG=b:217911928
TEST=tast run <IP> power.ShutdownWithCommandBatteryCutoff
Change-Id: I20f0a8259c2fc986da23026da88feadd69942046
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69904
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Name a variable based on its utility. `is_external` variable adds
`ExternalFacingPort` _DSD property to an ACPI device hence
rename it to `add_acpi_external_facing_port`.
BUG=b:259716145
TEST=Build google/rex with this flag and verify it in SSDT at
runtime.
SSDT snippet:
Name (_DSD, Package (0x04) // _DSD: Device-Specific Data
{
ToUUID ("6211e2c0-58a3-4af3-90e1-927a4e0c55a4"),
Package (0x01)
{
Package (0x02)
{
"HotPlugSupportInD3",
One
}
},
ToUUID ("efcc06cc-73ac-4bc3-bff0-76143807c389"),
Package (0x01)
{
Package (0x02)
{
"ExternalFacingPort",
One
}
}
})
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I65100283ed9b65037c9890f28ecab41fcfa25d83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69970
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Based on latest schematic to update the gpio table.
BUG=b:254365935
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=marasov emerge-brya coreboot
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I03b443826d39182eaf23ad3e4e0ba8d6b8a93022
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69180
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
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SATA is not supported on google/rex hence disable it.
BUG=none
TEST=Build and boot to google/rex.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I35a742ab9782feed86c3af514505d870d181b34b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Enable NVMe GPIOs based on fw_config and add NVMe to devicetree.
Note, eMMC and NVMe are not probed in devicetree. On first boot in
factory, the device needs to boot with unprovisioned fw_config, so all
storage devices should be enabled when unprovisioned. Currently,
devicetree disables all probed devices when unprovisioned. If we want
eMMC and NVMe to be probed, support needs to be added for enabling
probed devices when unprovisioned.
BUG=b:259211172
TEST=Verified by ODM. On craask, LTE and WCAM still work. On craaskneto,
eMMC and NVMe SKUs can both boot.
Change-Id: I76a056cddff2246cfb5bb26ddbdfc333b49d9aaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69958
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Follow thermal table from thermal team.
1. Modify TS1 passive policy to 68.
BUG=b:249446156
TEST=emerge-nissa coreboot chromeos-bootimage
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I8539a29cab4863034a2b64d38aef4b772473246d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69960
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The cpu cluster is always present and it's the proper device to contain
the settings that need to be applied to all cpus. This makes it possible
to remove the fake lapic from devicetrees.
Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59314
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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`is_untrusted` is eventually ended up by adding DMA property _DSD which is similar to what `add_acpi_dma_property` does for WWAN drivers, hence it
makes sense to have a unified name across different device drivers.
BUG=b:259716145
TEST=Verified that the _DSD object is still present in the SSDT.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I4e0829a76a193b0a1e1e0f2b7ce2119bb00dd696
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69937
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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A function declaration without a prototype is deprecated in all versions
of C.
Change-Id: Ie22231908233f2fba25d78f6c5f53940011e8158
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69748
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add conn0/conn1 for pch_espi.
BUG=b:254365935
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot.
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I5969d2941c02400788d66521680fcd13d3a6b13f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69785
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Declare touchscreen and touchpad under I2C3 and I2C5
BUG=b:254365935
BRANCH=firmware-brya-14505.B
TEST=Built successfully
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ifc865fc0c0c42af0d74272289c562e347fac3a9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69467
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adjust SPD ID order
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
H9JCNNNBK3MLYR-N6E 1 (0001)
MT62F1G32D4DR-031 WT:B 2 (0010)
H9JCNNNCP3MLYR-N6E 3 (0011)
BUG=b:254365935
BRANCH=None
TEST=run part_id_gen to generate SPD id
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I3a62cf355508debce387c48d9d089e73763b2bf0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69784
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adding cros_gpios for crossystem to access WP GPIO
BUG=b:258048687
TEST= run FAFT firmware_WriteProtect passed.
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Change-Id: Ieac1df805c6399aefdc13aae136630d496aacd58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69924
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The brask doesn't include a real chassis so we don't need to configure
the fan setting in the overridetree.cb. Instead, we can leave the fan
running at full speed after the device boot up.
BUG=b:259643676
BRANCH=firmware-brya-14505.B
TEST=flashed the bios to the device and make sure the fan spinned
at full speed.
Change-Id: I6075b6171ca4d7b907679efd0ce7e355759385bc
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Based on the latest schematic to update the gpio table.
BUG=b:239513596
TEST=emerge-brask coreboot
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: Ifaf0629dcd77d21cf09fe84e760f1f22c075467f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Override devicetree configuration based on the latest gaelin schematic.
BUG=b:249000573, b:254375472
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=emerge-brask coreboot
Change-Id: I3a741feec52cf73da8d6ec0b03cc93d6a4cba256
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Update devicetree setting per the schematic.
BUG=b:239513596
TEST=emerge-brask coreboot
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I8746d44daa43c06723bdfcac6803eb90a3c124b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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This reverts commit 7203aa5c2dcb90e50356305cabbe062bd4f4dc76.
BUG=b:260138434
TEST=None
Cq-Depend: chrome-internal:5126951, chromium:4049177
Change-Id: Ieaa44a33a7c65d384581b5145821b449783ca3fa
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
All parameters of DPTC_INPUT() need to be configured on devicetree
when SOC_AMD_COMMON_BLOCK_ACPI_DPTC is enabled. The parameters without
configurations on devicetree would be 0 when
SOC_AMD_COMMON_BLOCK_ACPI_DPTC is enable. Follow AMD DevHub document
#57316. Configure vrm_current_limit_mA, vrm_maximum_current_limit_mA
and vrm_soc_current_limit_mA on devicetree with thermal table config E
as default table for SMT. Since the dynamic thermal table switching
mechanism is still under cooking, after discussing with thermal team,
suggest adopting config E(limit Soc not reach to max power) as default
thermal config to avoidany thermal-related issue during phase build.
Once the dynamic thermal table switching mechanism is finished, will
change the default value to config A.
BUG=b:258572474, b:248976976, b:259167917, b:257394883
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: Ic1e7a46cac4119c7237d96a7bd0d23c8db028680
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
|
|
It shouldn't be assumed that all variants of skyrim will use the same
gpio for TPM interrupts.
Use the PSP's new mailbox command to tell it what gpio the tpm interrupt
comes in on.
BUG=b:248193764
TEST=tast run <ip> hwsec.TPMContest
Verify log entry:[DEBUG] PSP: Setting TPM GPIO to 18...OK
Use incorrect GPIO in mailbox cmd and verify TPMContest test
failed.
Signed-off-by: Mark Hasemeyer <markhas@google.com>
Change-Id: I9f4005e10987caf9f32e5ac99ff5f2b9467e586c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69874
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
For nissa, the ISH main firmware will be included in the CSE region in
flash instead of loading it from rootfs. So remove the ISH
firmware-name.
BUG=b:234776154
TEST=Boot to OS on nirwen and yaviks UFS SKUs. Check ISH firmware is not
loaded by kernel, and device still goes to S0i3.
Cq-Depend: chrome-internal:5102230
Change-Id: I68f963e17bc0dbf9db9adaaa3f96f06b8737523b
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69868
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
BUG=b:253387689
Test:Boot to OS on craask and check SAR Proximity Sensor GPIO pin
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I2b2a2516890b68036e96d1a542e6a10a098cb6a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69790
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
field STORAGE 30 31
option STORAGE_UNKNOWN 0
option STORAGE_NVME 1
option STORAGE_UFS 2
end
BUG=b:254365935
TEST=emerge-brya coreboot.
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I17f8a852808d279a1f2b08b364cd4e525a807560
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69786
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
This change enables the DisplayPort detection at preboot for Rex board.
BUG=b:247670186
TEST=Built image and validated DisplayPort feature at preboot on Rex.
Change-Id: I1a8a13e937c7132696aa39d85c3c6b6fb2dd13a5
Signed-off-by: zhaojohn <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67742
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
EC_HOST_EVENT_USB_CHARGER is no longer defined by the EC, so remove all
references.
BUG=b:216485035,b:258126464
BRANCH=none
TEST=none
Change-Id: I9e3e0e9b45385766343489ae2d8fc43fb0954923
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
BUG=b:235919755
Test=Check error message "Exposing GPIOs in Power Resource and _CRS"
not show in firmware log.
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I21a47adde48555098d041b94d483cad308bdb717
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
|
This patch deselects `USE_PM_ACPI_TIMER` kconfig to ensure that
ACPI PM timer remains disabled.
The PM timer (by PMC IP) consumes more power and blocks S0ix so the
timer is emulated by ucode to save power and unblock S0ix.
TEST=Able to boot Google, Rex and ensure PMC MMIO register 0x18fc
BIT 1 is set.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I2a23b417ff7fb6328323380a7df46b4b397fc8eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69685
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
BUG=b:231291430
TEST=See STB Spill-to-DRAM enabled
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ib60b7fc2ba85c7a8025c9f8c6495e94049499f56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69707
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Implement mainboard_needs_pcie_init() for herobrine in order to
determine if we need to initialize the pcie links. When the SKU id is
unknown or unprovisioned (for example at the beginning of the factory
flow), we should still initialize PCIe. Otherwise the devices with
NVMe will fail to boot.
BUG=b:254281839
BRANCH=None
TEST=emerge-herobrine coreboot
Change-Id: I8972424f0c5d082165c185ab52a638e8b134064c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Modify the chromeos FMD file for nissa variants to redistribute the
buffer in SI_ME region obtained due to CSE size optimizations to SI_BIOS
region.
1. Modify SI_ALL region size to 3712K. SI_DESC remains at 4K and SI_ME
is 3708K.
2. Modify SI_BIOS region to 12672K. This results in an addition of 32K
buffer each to FW_MAIN_A/B regions.
BUG=b:228936671
BRANCH=firmware-nissa-15217.B
TEST=Verify CSE FW update with new FMD and ME RW blobs on craask.
Cq-Depend: chrome-internal:5094491
Change-Id: I5ead2f81850a2aa79e677c7f271db672e235750a
Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
+-----------+-------+-------+---------+-------------+----------+
| Setting | AC LL | DC LL | ICC MAX | TDC Current | TDC Time |
| |(mOhms)|(mOhms)| (A) | (A) | (msec) |
+-----------+-------+-------+---------+-------------+----------+
| IA | 2.8 | 2.8 | 80 | 43 | 28000 |
+-----------+-------+-------+---------+-------------+----------+
| GT | 3.2 | 3.2 | 40 | 23 | 28000 |
+-----------+-------+-------+---------+-------------+----------+
- IA TDC current from 20A to 43A.
- GT TDC current from 20A to 23A.
BUG=b:256754175
TEST=Build test image and use PTAT to check IA and GT value
Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: Ife36655f077bae567bff3c3e33f779c990cf5ed9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69135
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
Update touchscreen setting.
Change hid as panel team request to fix touchscreen with no function.
The panel team verification result is on b/251378772 comment#17.
BUG=b:251378772
TEST=Build/boot ChromeOS on winterhold, ensure touchscreen is
functional.
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I07d446111b1c18bfe15d00b6eacff23382cd461a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
None of the touchscreens (over I2C) used in the rex program requires
exporting GPIOs in the ACPI _CRS method.
This can cause i2c devices to malfunction or cause timing
sequence violations if ACPI exports a PowerResource for the
device that uses GPIOs that are also exported in _CRS.
BUG=none
TEST=Able to build and boot Google, Rex platform.
Without this patch:
[ERROR] I2C: 00:10: Exposing GPIOs in Power Resource and _CRS
With this patch:
None
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I578a60eff27f94d6dc94b900604bc7560337d60b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69612
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Tune timing between power on and reset on SD device RTD3.
BUG=b:250746988
TEST=Use the value to boot on Pujjo successfully.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I1ea77ec8381000249229653f1c0b9044bdf7866d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
|
This reverts commit d164feb72602da958b644643b44e754f04a1f281.
Reason for revert: Herobrine program decided that we wanted
to be able to boot from NVMe if one exists.
Change-Id: I2d3217c514734608e2ff049b620f4c7acf86de89
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69720
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
ALC5682-VS/ALC5682-VD use different kernel driver by different hid name.
Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config.
ALC5682I-VS: _HID = "RTL5682"
ALC5682-VD: _HID = "10EC5682"
BUG=b:246491349
TEST=ALC5682-VD/ALC5682-VS audio codec can work.
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I60d5e0af7e2dabd134c8059eaeac388d40ac2073
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Enable ISH driver and set firmware name as "adl_ish_lite.bin"
BUG=b:242291814
TEST=boot into kernel, and check dmesg
"ISH firmware intel/adl_ish_lite.bin loaded"
Change-Id: I4badabba1a0cfceb77fc91f21953496152f19615
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69606
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add power limits for the RPL SKUs of Agah.
BUG=b:258432915
TEST=build and boot ADL based Agah. RPL based testing
when hardware becomes available.
Change-Id: Ie97a9d14f1ee6f65225b7d26e25ff3d902fddc7f
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69419
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
ELAN updated the datasheet, the HID/I2C protocol's T3 delay
time is 150ms now. Modify the volmar's delay time to follow
the requiremnet.
BUG=b:257073343
TEST=Build firmware and measure the T3 timing of resume
and boot up on volmar DUT.
Run Suspend/Resume with UI test and got pass.
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I40a30ed567cd676d0a9373527d93fe51f89d39e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69559
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Follow Dynamic Thermal Table Switching proposal to initialize
thermal table config E as default table for SMT.
Since the dynamic thermal table switching mechanism is still
under cooking, after discussing with thermal team, suggest
adopting config E(limit Soc not reach to max power) as default
thermal config to avoid any thermal-related issue during phase
build. Once the dynamic thermal table switching mechanism
is finished, will change the default value to config A.
BUG=b:232946420, b:258572474
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I4aa90304e1e7bda7d580de2582129191e9eb0e76
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
|
|
Create the crystaldrift variant of the skyrim reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:240970782
BRANCH=None
TEST=util/abuild/abuild -p none -t google/skyrim -x -a
make sure the build includes GOOGLE_CRYSTALDRIFT
Signed-off-by: Chao Gui <chaogui@google.com>
Change-Id: Ibb3ebaa7e4af1a03173b93b8c4fbd342f7cd7100
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Now that coreboot performs the necessary power sequencing, switch
from using the 'probed' flag to 'detect' for all I2C touchscreens.
This alleviates ChromeOS from having to probe to see which
touchscreen model is actually present, prevents breaking ACPI spec
by generating device entries with status 'enabled and present'
which aren't actually present, and improves compatibility with
upstream Linux and Windows.
BUG=b:121309055
TEST=build/boot ChromeOS and Linux on zork, ensure touchscreen is
functional, and ACPI device entry generated for correct touchscreen
model.
This mirrors the changes made for skyrim in commit 22683fab
(mb/google/skyrim: Use detect vs probed flag for touchscreens)
Change-Id: Idfe899bd535507c56f0825c6538246441b3b0827
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69457
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
As all variants have a touchscreen option, in baseboard tables set the
enable GPIO high and hold in reset during romstage, then release reset
in ramstage. This will allow the touchscreen to make use of the runtime
I2C detect feature (enabled in a subsequent commit) so that an ACPI
device entry is created only for the touchscreen actually present.
This mirrors the change to skyrim in commit f90ff456
(mb/google/skyrim: Implement touchscreen power sequencing)
Change-Id: Ifdd75cd96e7b6880085a3f47214b92948a56aa2e
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69456
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Correct G2 touchscreen HID to GT75CH02.
BUG=b:235919755
Test=Dump the SSDT on craask and check the HID had been modified.
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Iad32e8cbd534dc43fca24d881092f3477ca1a4e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69600
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add (empty) baseboard GPIO tables, getter functions, and call to
gpio_configure_pads() in romstage, in preparation for adding
touchscreen GPIO configuration/power sequencing.
Change-Id: If0f626dbc7e601c2f49759e49a0baf027bf25f96
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69482
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
As all variants have a touchscreen option, in baseboard table set the
enable GPIO high and hold in reset during romstage, then release reset
in ramstage. This will allow the touchscreen to make use of the runtime
I2C detect feature (enabled in a subsequent commit) so that an ACPI
device entry is created only for the touchscreen actually present.
This mirrors similar changes made for skyrim, guybrush, and zork.
TEST=tested with rest of patch train
Change-Id: Id235815904dfc093549a1ed529e19974010977c7
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69547
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Now that coreboot performs the necessary power sequencing, switch
from using the 'probed' flag to 'detect' for all I2C touchscreens.
This alleviates ChromeOS from having to probe to see which
touchscreen model is actually present, prevents breaking ACPI spec
by generating device entries with status 'enabled and present'
which aren't actually present, and improves compatibility with
upstream Linux and Windows.
BUG=b:121309055
TEST=build/boot ChromeOS and Linux on barla/liara, ensure touchscreen
is functional, and ACPI device entry generated for correct touchscreen
model.
Change-Id: I142a6cdb6e8cef51fd925d34362a19a8736982a5
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69548
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Rename variant_romstage_gpio_table() to baseboard_romstage_gpio_table()
since the GPIO table comes from the baseboard (and is not overridden by
any variant).
Drop the __weak qualifier as this function is not overridden.
This mirrors similar changes made for skyrim, guybrush, and zork.
Change-Id: I772bd2d74fd6778ffaa1e0809cc53f8d43b153f3
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69546
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Disable GPIO export in ACPI _CRS for touchscreens which set the
register "have_power_resource." This eliminates the error:
[ERROR] I2C: <bus:addr>: Exposing GPIOs in Power Resource and _CRS
TEST=build/boot barla/liara, verify touchscreen functional, no error in
cbmem log.
Change-Id: Ifa8248755f346df37faf7a3182651bf190b0c33d
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69549
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
GPP_H13 should be reset when going to S5. Update it to do so on
PLTRST
BUG=b:240617195
TEST=Measured on Agah that PP3300_SD_X goes off in S5.
Change-Id: I959f92f2c486e0ca5cb4269b271c163b4c4925d4
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69340
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add TPM I2C bus for gaelin in Kconfig.
BUG=b:249000573
BRANCH=firmware-brya-14505.B
TEST=Build "emerge-brask coreboot" and can boot to OS.
Change-Id: Idaac11111a9ba7df0929267567e4730b2811f5f0
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68886
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Some nissa devices want to disable boot from SD card. Since nissa has a
single shared depthcharge target, add a program-wide fw_config to allow
disabling it.
BUG=b:253003881
TEST=With depthcharge change, set SD_BOOT_DISABLE on nivviks and check
SD card is not initialised in depthcharge.
Change-Id: I1a3a533e4e74e48d9ce4a9678b812cb62ce2066b
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69541
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The SI_ME subregions were added to support using the CSE stitching tools
(cse_serger). Use of the stitching tools has been reverted and probably
won't be re-enabled soon, so the subregions are not currently used by
anything. They also don't match the actual region sizes chosen by the
FIT tool, so remove them to avoid confusion. The other option would be
to manually keep them in sync with the sizes chosen by the FIT tool, but
this would be extra manual effort without much benefit.
BUG=None
TEST=Build and boot on nivviks
Change-Id: I993e07a060445ab8de1b0e40a023e8248867c53c
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69540
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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Now that we have a common init_tables in all mainboards using AMD SoCs,
both the population of the fch_pic_routing and fch_apic_routing arrays
and the definition of those arrays can be moved to the common AMD SoC
code to not have the code duplicated in all mainboards.
BUG=b:182782749
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: I8c65eca258272f0ef7dec3ece6236f5d00954c66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68853
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Without RTC, the timestamps in the eventlog are currently all
'2000-00-00 00:00:00'. Enable RTC to get the correct timestamps.
localhost ~ # head /var/log/eventlog.txt
0 | 2022-10-15 22:59:38 | Log area cleared | 4088
1 | 2022-10-15 22:59:38 | Memory Cache Update | Normal | Success
2 | 2022-10-15 22:59:45 | System boot | 0
3 | 2022-10-15 22:59:46 | Firmware vboot info | boot_mode=Developer |
fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown
localhost ~ #
localhost ~ # date
Sun Oct 16 01:42:59 PDT 2022
localhost ~ #
BUG=b:233720142
TEST=check the timestamp field in /var/log/eventlog.txt
Change-Id: Iddad102dc8d60de01a691d330deb8247e99c616a
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69432
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure the rcomp, dqs and dq tables based on the schematic.
BUG=b:254365935
BRANCH=None
TEST=Built successfully
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I8c9541006828deae83e2ae4a860f40d7433662d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69149
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Rewrite the Kahlee IRQ mapping handling to be in line with the newer AMD
SoCs to allow making the largest part of the corresponding code common
for all AMD SoCs in the coreboot tree.
The PIC-mode IRQ numbers for both PIRQ_ASF and PIRQ_SDIO were 0 in the
data tables which is the PIT IRQ which looks very wrong to me, so it was
changed to PIRQ_NC. Since the ASF and likely also the SDIO controller
are unused, this shouldn't change runtime behavior. The data tables also
had non 0 and non 0x1f entries in the following locations the internal
BKDG #55072 revision 3.04 describes as unused: 0x31, 0x33, 0x35-0x37,
0x40, 0x50-0x53. The entry at 0x32 is also non 0 and non 0x1f and the
description in the BKDG says that it controls the IRQ mapping of another
internal PCI device, but that PCI device doesn't exist in the SoC.
TEST=No obvious IRQ-related breakage on google/liara
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Change-Id: I9b3bfca33d88ef3989b63f4fe6c301e0e485b7e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68851
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the
marasov variant.
BUG=b:254365935
TEST=FW_NAME=marasov emerge-brya coreboot
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I4d155fb35424d1ec12e825ca0aab233bd3cd607e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69376
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Change 'printk(BIOS_DEBUG, "ERROR:' to printk(BIOS_ERR, "'.
Change-Id: Id31c25f5b8686f951ab4f331682b82ff327d5e78
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Request by RF team, remove RFIM related settings to disable it.
BUG=b:239657092
Test=RF team test on DUT and check it's disable
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I1eb4d93c2821cb067628dc1228c6c522d292c739
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Modify touch screen hid for Pujjo board.
BUG=b:258586760
TEST=Use the value to boot on Pujjo successfully.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Ia3b374de8cba2125c478814a1890a4b6831715b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Rename variant_pcie_gpio_table() to baseboard_pcie_gpio_table(), since
the GPIO table comes from the baseboard (and is not overridden by any
variant).
Drop the __weak qualifier as this function is not overridden.
This is similar to the change made for skyrim in CB:67809
Change-Id: Idd8ea3446ab7940b21265a3ed8080ba4029c4ff7
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69453
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Enable RPL support for Agah.
BUG=b:258432915
TEST=build and boot ADL based Agah. RPL based testing
when hardware becomes available.
Change-Id: I5437dbf9e7812367a280d1ed659f286fb9b62a68
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69398
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This will enable crossystem to access WP GPIO
BUG=b:258048687
TEST= wpsw_cur in crossystem reads the correct gpio
Change-Id: I67f4a57025064dbf8c691255b0abae9d3fa0dbd3
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69468
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Disable the unused fingerprinter(FP) gpio for zavala by fw_config
FPMCU_MASK field.
BUG=b:250807253
TEST=build firmware and veriify the FP function on volmar DUT
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I0af1b7c3e4829ecab98525ead4f078c3eb6485d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69465
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:234776154
TEST=Build and boot Marasov UFS, copy ISH firmware to host
file system /lib/firmware/intel/adl_ish_lite.bin
check "dmesg |grep ish", it should show:
ish-loader: ISH firmware intel/adl_ish_lite.bin loaded
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic53a3cbdf83825adc27f37877a14f4f405d4a5ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69377
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
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This patch ensures that Marasov selects the ISH driver for
devices with UFS enabled.
BUG=b:256566011
TEST=Able to build Marasov.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I97a0aa3bc6976be32ddbf1fc6b37c16bb62a62e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69379
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This removes the dev_index argument from the google_chromeec_reboot
API. It's always set to 0, so don't bother passing it.
BUG=b:258126464
BRANCH=none
TEST=none
Change-Id: Iadc3d7c6c1e048e4b1ab8f8cec3cb8eb8db38e6a
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69373
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I77a333827552741453d8b575f2a8009b3e1bf8f1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
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BUG=b:239513596
TEST=emerge-brask coreboot
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I7411e10348c36786000c6918b9b154b7329f3cd0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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Support GL9763E as a eMMC boot disk.
BUG=b:239513596
TEST=emerge-brask coreboot
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I2b29309615df381f1e24f29fc048c6f9bf216b7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69425
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the
gladios variant.
BUG=b:239513596
TEST=emerge-brask coreboot
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: Id6f2bf2a79df883bcb70171051cec4c577ca3bc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69424
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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Skyrim platforms have I2C3 controller which is shared between PSP and
X86. In order to enable cooperation, PSP acts as an arbitrator. Enable
SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP, so that proper driver is
binded on the OS side.
BUG=b:241878652
BRANCH=none
TEST=Build kernel and firmware. Run on skyrim and verify TPM
functionality.
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I2a3de8cb2b9241e2d81e02df49f317ac0408d5bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
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Updated comment as per guidelines.
BUG=b:232302324
TEST=none
Signed-off-by: Venkat Thogaru <quic_thogaru@quicinc.com>
Change-Id: I6a925477a926e7e9d54e42d662768536318ec8e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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To support an RPL SKU on marasov, marasov must use the FSP for RPL.
Select SOC_INTEL_RAPTORLAKE for marasov so that it will use the RPL
FSP headers for marasov.
BUG=b:254365935
BRANCH=None
TEST=FW_NAME=marasov emerge-brya intel-rplfsp
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I7874420c0fb51b9cc616cd979ffc9349c381602e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69367
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add supported memory parts in mem_parts_used list, and generate SPD ID
for these parts.
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
H9JCNNNBK3MLYR-N6E 1 (0001)
MT62F1G32D4DR-031 WT:B 4 (0100)
H9JCNNNCP3MLYR-N6E 5 (0101)
BUG=b:254365935
BRANCH=None
TEST=run part_id_gen to generate SPD id
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ifa0637b47d0017cdb9e26ed32328f4405c0df3f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69311
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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update devicetree setting per the schematic
BUG=b:254365935
BRANCH=None
TEST=Built successfully
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ifa4cb18b8e1a7b162f505ff12612ef808fb7061a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69364
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:257879909
Test:Boot to OS on craask and check stylus GPIO pins
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I7e3a2583187c8a8e2616a5272b5a7a61debe982b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69138
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Request by thermal team, make below changes:
1) tdp_pl2_override: 12 --> 25
2) pl1.min_power: 3000 --> 5500
3) pl1.time_window_max: 32 * MSECS_PER_SEC --> 28 * MSECS_PER_SEC
4) pl2.min_power: 12000 --> 25000
5) pl2.max_power: 12000 --> 25000
6) pl2.time_window_min: 28 * MSECS_PER_SEC --> 1
7) pl2.time_window_max: 32 * MSECS_PER_SEC --> 1
BUG=b:239495499
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I88c8c4e6798ec5bc2930dd713e8c8b2c543cfaf9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68523
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
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Update SX9324 related settings based on tunned values from the ODM.
This patch supports both legacy and upstream Linux's SX9324 driver.
BUG=b:242662878
TEST=i2cdump -y -f 13 0x28
(Verified register values on Pujjo)
Signed-off-by: Victor Ding <victording@google.com>
Change-Id: I34d8073ffe93e6939f8da0cd7efb8667c0e9ac37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69366
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Instead of including pci_int_defs.asl in each board's DSDT, include it
in the common soc.asl. This moves the PRQM OperationRegion and the PRQI
IndexField defined in pci_int_defs.asl into the \_SB scope, but those
are defined inside the \_SB scope both in the Picasso reference code and
for the AMD SoCs from Cezanne on.
TEST=Both Linux and Windows still boot and don't show ACPI errors on
Mandolin after moving this inside the \_SB scope
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib4e7bfb15de184cc43cd17c8249be0f59405793f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
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This aligns Picasso more with the newer AMD SoCs and also makes it a bit
clearer what this file does. Also remove the unneeded tabs at the
beginning of each line.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie6e5ee815e4346004bc864a6111a255dc689eae8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
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Change-Id: I955274bc6bda587201f130762c0735c36f5501d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69289
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add wifi sar table for craask/craaskbowl.
Use fw_config to separate different project settings.
BUG=b:247652032,b:251287099,b:251287101
Test=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I5c92f0ab53ece12a97068f09241e5298909116aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
