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2021-12-03mb/google/brya/variants/primus: Swap TPM I2C with touchscreen I2CMalik_Hsu
In next build phase, primus will exchange i2c port for touchscreen and cr50. BUG=b:207834727 TEST=build pass Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: Ief1b156b866a9aaa2919f0e209b6439c7019e939 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03mb/google/brya/var/taeko: Set vGPIO reset typeKevin Chang
Due to the vGPIO is not reset when we power on through S5, we would met MCA when PCIE send L1 request without following Ack BUG=b:207070967 TEST=S0->S3->S5->power key->S3->S0, see if boot up normal Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: Ice522260f288b165ae66dddc3e1979e806b53f9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/59749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03mb/google/brya: Create taniks variantJoey Peng
Create the taniks variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:207402720 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_TANIKS Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I797051f93019ccf72f1007d9c0b98cfb071717b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-02mb/google/brya/var/brask: Set PL and PsysPLAlan Huang
1. Set the PL1, PL2 and PL4 according to issue b:193864533 comment#55 and Intel's doc #626774. 2. Set PsysPL2 and PsysPmax according to the conclusion in issue b:193864533 comment#23 and comment#29. BUG=b:193864533 BRANCH=none TEST=Compare the measured power from adapter with the value of 'psys' from the command 'dump_intel_rapl_consumption'. Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Change-Id: I9261902b8c892d0b866f326b24988039c1d30b56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-02mb/google/brya/var/baseboard/brask: Add power limits functionsAlan Huang
Copy function variant_update_power_limits from brya to set power limits. Add function variant_update_psys_power_limits and copy the algorithm from puff. Add structure system_power_limits and psys_config to define and configure the psys power limits. BUG=b:193864533 BRANCH=none TEST=Build pass Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Change-Id: I183017068e9c78acb9fa7073c53593d304ba9248 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-02mb/google/brya/var/gimble: Swap TPM I2C with touchscreen I2CMark Hsieh
DVT schematic will exchange TPM_I2C3 to TPM_I2C1, that may need swap TPM I2C with touchscreen I2C to avoid TPM I2C fall on muxed ISH I2C, need change I2C map, sch amd GPIO map. b/196293623 BUG=b:207613972 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I26d059a7ea5a3fdf00de260214c00d3bba9aa7f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59580 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-02mb/google/brya/var/felwinter: Swap TPM and touchscreen I2C busEric Lai
Follow the latest HW schematic change. BUG=b:208556921 TEST=build pass Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ic05843487ea540b8cd9a50d5f73803905fd80d49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-02mb/google/brya: Fix S0i3 regressionMeera Ravindranath
Keeping the PM timer enabled will disqualify an ADL system from entering S0i3, and will also cause an increase in power during suspend states. The PM timer is not required for brya boards, therefore disabling it. Fixes: 0e905801 (soc/intel: transition full control over PM Timer from FSP to coreboot) BUG=b:206922066 TEST=Boot gimble to OS and verify S0i3 counter incrementing after exiting S0ix suspend states. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I8005dacd732c033980ccc479375ff5b06df8dac1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59790 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-02soc/intel/alderlake: Add Kconfigs for all PCH typesAngel Pons
The Alder Lake code currently supports the PCH-M and PCH-P types, which have some differences (so far, only the amount of PCIe I/O). Mainboards can use the `SOC_INTEL_ALDERLAKE_PCH_M` Kconfig option to specify which PCH type they use: select the option to choose PCH-M, do not select the option to choose PCH-P. While this works, it can be confusing once more PCH types are added. Introduce the `SOC_INTEL_ALDERLAKE_PCH_P` Kconfig option so that boards have to explicitly choose a PCH type. Also, use this option to restrict the PCH-P defaults for PCH-dependent settings to avoid unintended reuse of the PCH-P defaults when adding a new PCH type. To make sure only one PCH type is selected, add some preprocessor in `bootblock.h` to provoke a build-time error if this requirement is not met. Kconfig doesn't seem to have a mechanism to describe sets of mutually-exclusive bool options that allows said options to be selected (a `choice` block doesn't allow its elements to be selected). Finally, adapt the ADL boards accordingly. Change-Id: I7deca820e08ce2b5a220f3c97a511a4f3464a976 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-12-01guybrush: add RO_GSCVD area to FMAPVadim Bendebury
This area is used for storing AP RO verification information. BRANCH=none BUG=b:141191727 TEST=built a guybrush firmware image and verified that the RO_GSCVD area was indeed added: $ dump_fmap /build/guybrush/firmware/image-guybrush.bin | \ grep -B3 RO_GSCVD area: 25 area_offset: 0x00808000 area_size: 0x00002000 (8192) area_name: RO_GSCVD $ - verified that guybrush device boots fine with the new image. Change-Id: Ifa24d5a6271a8bcbf737d4580ec85b9cfdd9af01 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57864 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-01mb/google/brya/redrix: Add _HID for privacy screen deviceTim Wawrzynczak
The ChromeOS kernel platform driver is adding support for a ChromeOS privacy screen device, and in order to locate that device, the driver uses the GOOG0010 reserved HID for this. Patch for 5.10 kernel can be found at: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3289984 BUG=b:206850071 TEST=dump SSDT, see _HID instead of _ADR Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: If988ca94b6c70d08a7b07cc9f6bbb077fac84e5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59731 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-01herobrine: Assert gpio for USB_HUB_LDO_ENSandeep Maheswaram
Some herobrine variants have USB hub powered by discrete LDO that is controlled by USB_HUB_LDO_EN gpio. Assert the GPIO on boot. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board. Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Change-Id: Ia94e046f9eb0d3ce593f3445e0203a7391c14de2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-30mb/google/herobrine: Initialize USB by calling SOC methodRavi Kumar Bokka
Initialize by calling `setup_usb_host0()` from SOC code BUG=b:182963902 TEST=Validated USB enumeration on qcom sc7280 development board Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Change-Id: Ic378352a97e4f3ed89089f1f7545f8ebb172b1f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-11-30mb/google/brya/var/kano: Enable USB2 port 9 for BlueToothDavid Wu
BlueTooth disappeared after disabled USB2 port 9, so we need to re-enable it. BUG=none TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I7971509d7428562c80e781339ead059a189cea13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-30mb/google/dedede/var/beetley: Enable GEO_SAR_ENABLE for beetleywizard
BUG=b:207307897 BRANCH=dedede TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Change-Id: Ib1682cdafe1b6ed7cc0cf23624f83d2e5bbfb92e Signed-off-by: Wizard Shen <shenhu5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com>
2021-11-30brya: add various ES variantsYH Lin
Fork multiple "4ES" variants off some brya devices to properly support ES SoC. BRANCH=none BUG=b:201767461 TEST=emerge-brya coreboot and check the artifacts Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: Ic9516fec591429238bde1478eca2522d8ed10127 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-29soc/qualcomm/common/usb: Add support for common USB driverSandeep Maheswaram
Add common USB driver for qualcomm soc sc7180 and sc7280. This includes dwc3 controller, qmp ss phy, qusb hs phy and snsp hs phy. BUG=b:182963902 TEST=Validated USB enumeration on qcom sc7180 and sc7280 development board Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Change-Id: I1013ded22855286220cfa747cb25418070fe85a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-26mb/google/corsola: Add an option for SD card initializationRex-BC Chen
There is no support for SD card on Corsola reference board, so we add a configuration to disable SD card initialization to prevent setting GPIOs in a mistaken way. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ia05fd046335c6ce6f9198ddbb7cbda2afc6ae3cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/59571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-26mb/google/corsola: Get RAM code from ADCRex-BC Chen
On Chromebooks the RAM code is implemented by the resistor straps that we can read and decode from ADC. For Corsola the RAM code can be read from ADC channel 2 and 3. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I485c32dec7b425b604b4063d742a0e37d3961513 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-26mb/google/corsola: Raise little CPU frequencyRex-BC Chen
Raise little CPU to 2GHz at romstage. TEST=check little core cpu frequency is 2GHz BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: If4c983d15beb2b588230f3db7416cb767b29978d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-26mb/google/corsola: Add VPROC12/VSRAM_PROC12 to regulator interfaceRex-BC Chen
Add VPROC12/VSRAM_PROC12 to adjust power for raising little CPU frequency. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I59b4627220022a51a116716036a8ba0048039508 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-26mb/google/corsola: configure GPIOsRex-BC Chen
Configure Chromebook specific GPIOs, including EC_AP_INT, EC_IN_RW, GSC_AP_INT, EN_SPK, GPIO_AP, and GPIO_RESET. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I76bde75788889111c0a051eed731dadc9898c0e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-26mb/google/brya/var/kano: swap TPM i2c with TS i2c for the next build phaseDavid Wu
Kano EVT will exchange i2c port for touchscreen and cr50. BUG=b:195853169 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I500f0721689ca66b65b8fb1deb79bef2bd988465 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-25mb/google/brya/variants/primus: update gpios for power consumptionMalik_Hsu
In different sku, some unused GPIO pins are processed by NC for power consumption. BUG=b:196790249 TEST=emerge-brya coreboot chromeos-bootimage and check power Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I753e41dec1825299e6cd437b5f67e2d957bc6148 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-25src/mb/brya: Enable crashlog on brya0Kane Chen
Enabling crashlog helps partners to debug hang issues efficiently. BUG=b:195327879 TEST=Found BERT table is created and the tcss function is ok in depthcharge. Warm/cold/suspend_stress test pass 50 cycles on gimble Change-Id: Ib4bbe5d7cece0c6c5fc170460d55ac820054abb9 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-25mb/google/brya/variants/primus: add fw config probe for speaker ampMalik_Hsu
Added fw config probe for MX98360A. BUG=b:205883511 TEST=emerge-brya coreboot chromeos-bootimage and check audio function Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I2452b752ce58a5d0f1008cf187fb79ace6c4285f Reviewed-on: https://review.coreboot.org/c/coreboot/+/59613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-25mb/google/brya/var/felwinter: Add DPTF parameters for FelwinterJohn Su
The DPTF parameters were verified by the thermal team. BUG=b:207463762 BRANCH=brya TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I634d6d98c28e75ad41488921df6b8e836e253ff1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-25mb/google/brya/var/primus: Update thermal table for primusAriel_Fang
- Add 4 TEMP_SENSORs - Configure granularity of power limits BUG=b:200836803 TEST=USE="project_primus emerge-brya coreboot" and verify it builds without error. Signed-off-by: Ariel_Fang <ariel_fang@wistron.corp-partner.google.com> Change-Id: Id4d8dbe678b7f0870aeffa0a0118e65de9d5c22d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-11-25mb/google/brya/var/kano: Update thermal tableDavid Wu
Update thermal setting from thermal team. BUG=b:205648035 TEST=build and verified by thermal team. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: If5082462b79c88ecf510f7a552381c792604366e Reviewed-on: https://review.coreboot.org/c/coreboot/+/59572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-11-25mb/google/brya/var/kano: set power limits for thermalDavid Wu
Set power limits for kano based on CPU SKUs. BUG=b:205648035 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I25cf9be68f8981d8307b4c15ab9f65b59058fb19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-24mb/google/brya/var/gimble: Enable DRIVERS_GENESYSLOGIC_GL9750Mark Hsieh
Enable DRIVERS_GENESYSLOGIC_GL9750 support for Gimble. BUG=b:206014046 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ifc490e6e081b6a8534656417603d2916c3edcb05 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59579 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-23mb/google/brya/var/redrix: Disable autonomous GPIO power managementWisley Chen
With cr50 fw 0.3.22 or older version, it needs to disable autonomous GPIO power management and then can update cr50 fw successfully. BUG=b:202246591 TEST=FW_NAME=redrix emerge-brya coreboot chromeos-bootimage. Change-Id: Idc01ebb4d3ef990f24f18bef5424b7d6ba683d49 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-23mb/google/trogdor: change pin define for quackingstickSheng-Liang Pan
change TP_EN pin to GPIO_67 for quackingstick BUG=b:206862167 BRANCH=trogdor TEST=make Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I7cc1083111f46cd3489cbbb9e579c34dc972b0b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Bob Moragues <moragues@google.com>
2021-11-22mainboard/google/brya: Enable dev screen in bios-stage for BraskAdam Liu
Add Kconfig item ENABLE_TCSS_DISPLAY_DETECTION. TEST=Build with the VBT provided in issue b:199490251. Check the dev screen in bios-stage. BUG=b:199490251, b:206014054 Signed-off-by: Adam Liu <adam.liu@quanta.corp-partner.google.com> Change-Id: I5f34be030a6d819a0e93a2d479c4ff41bb14cfe2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-22mb/google/brya: Move cr50 configuration to variantDavid Wu
Brya schematic will swap TPM I2C with touchscreen I2C, so move into variant level. BUG=b:195853169 TEST=build pass. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ie5276527da135ec15045a81985ae006722871b0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-22mb/google/brya/variants/primus: add fw_config_probe for ALC5682I-VSMalik_Hsu
Added fw_config_probe method to distinguish different audio codecs to facilitate the use of different topology files by the OS. BUG=b:205883511 TEST=emerge-brya coreboot chromeos-bootimage and check audio function Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I0d5b95e89154b2cb6b371f24cc1b151c23ff642f Reviewed-on: https://review.coreboot.org/c/coreboot/+/59367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-22mb/google/brya/var/felwinter: Add ALC5682I-VS codec supportEric Lai
ALC5682I-VS will use in next build. BUG=b:194367025 TEST=none. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I34d736fe1c39860443dac07435a21ccd0ee2f21c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-22mb/google/dedede/var/bugzzy: Configure Acoustic noise mitigation UPDsSeunghwan Kim
Enable Acoustic noise mitigation for bugzzy and set slew rate to 1/8 which is calibrated value for the board. BUG=b:207046230 BRANCH=dedede TEST=build firmware to UPD and Acoustic noise test Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: Id249a143efb9bce70f48fb466fed42e766a10937 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-19mb/google/brya: Move EC_HOST_EVENT_USB_MUX wake event to S0ix onlyJoey Peng
If a USB_MUX_EVENT happens while the AP is in S3 during powerdown transtion (S0->S3->S5), this will cause the device to boot again after it has finished sequencing down to S5. Since S3 is not POR for ChromeOS devices anymore, change this event to wake from S3 and S0ix to just S0ix. BUG=b:206867635 TEST=emerge-brya coreboot Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Icdab40b6a845a34246d7da336f43e970f7908301 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-19mb/google/volteer/var/chronicler: set DdrMemoryDown enableSheng-Liang Pan
as doc #632048, there is a fix in MRC for this sighting but DdrMemoryDown need to be set to 1. BUG=b:192478111 BRANCH=volteer TEST=FW_NAME=chronicler emerge-volteer coreboot chromeos-bootimage Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: If7ead2d0bb2955a4f1b81d012ee2e2518b2a82e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59373 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-19mb/google/brya/var/redrix: Configure _DSC for CAM devices to ↵Varshit B Pandya
ACPI_DEVICE_SLEEP_D3_COLD Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips initial probe during kernel boot and prevent privacy LED blink. BUG=b:199823938 TEST=Build and boot redrix to OS. Verify entries in SSDT and monitor LED during boot. Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I88ea1b87698c63e1bd69367ee857fba3f25c84ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/59260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-18mb/google/guybrush: Add variant_tpm_gpio_tableRob Barnes
Add separate gpio table for TPM i2c and interrupt. Remove TPM gpios from early_gpio_table. This allows for initializing TPM gpios separately from other gpios. BUG=b:200578885 BRANCH=None TEST=Build and boot guybrush Change-Id: I51d087087b166ec3bb3762bc1150b34db5b22f2f Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59083 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-18mb/google/brya/var/felwinter: Correct USB3 TCSS settingEric Lai
Based on Intel Kit#615686, USB3 only needs to disable TBT and DMA per port. And if uses USB3 directly you need to set TcssAuxOri accordingly. BUG=b:206716691,b:205235144 TEST=USB function work as expected at USB3 only sku. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I303d042d6c80194ff48130fe4e9c04b49ca13ee8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-18mb/google/brya/var/gimble: Include 2 new SPDsMark Hsieh
Add SPD support to gimble for LPDDR4 memory part MT53E1G32D2NP-046 WT:B and MT53E512M32D1NP-046 WT:B. BUG=b:191574298 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Id3fc35605675b953bf993a29f35140f7721eedab Reviewed-on: https://review.coreboot.org/c/coreboot/+/59299 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-18mb/google/brya/var/redrix: De-assert SSD PERST# in romstageWisley Chen
After CB:57539 applied, it can support romstage GPIO table override. We can move SSD PERST# de-assertion to romstage. The reason for this is to give enough time after PERST# deassertion so that the SSD has enough time to initialize before the FSP scans the RPs for downstream devices. BUG=b:199714453 TEST=build Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I242cb1517f564d9d135d523b1e7f95ac34d601f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-18mb/google/brya/var/redrix: Correct WWAN power sequenceWisley Chen
Correct the WWAN power sequence to meet spec BUG=b:206079177 TEST=build Change-Id: Ibba1ecc04b563ae4eedd7596594f33812cbac150 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-18mb/google/brya/var/redrix: Configure Acoustic noise mitigationWisley Chen
Enable Acoustic noise mitigation for redrix and set slew rate to 1/8 BUG=b:204009588 TEST=build and verified by power team Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I0fc0bb68c4de6fca60ee290eb46a77200d748ca8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-18amdfwtool: Call the set_efs_table for StoneyridgeZheng Bao
Related to https://review.coreboot.org/c/coreboot/+/58555 commit-id: 35b7e0a2d82ac In 58555, we added the SOC ID for Stoneyridge in amdfwtool command line. But it raised building error because it then called "set_efs_table" without setting SPI mode. So we skipped calling that. But in set_efs_table, it has case for Stoneyridge. The boards also need to have this setting. So we remove the skipping and give the proper SPI mode in mainboard Kconfig. Change-Id: I24499ff6daf7878b12b6044496f53379116c598f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-17mb/google/brya/var/felwinter: Add MT53E1G32D2NP-046 WT:B SPDEric Lai
Add MT53E1G32D2NP-046 WT:B SPD. BUG=b:205669003 TEST=Boot up without issues. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If084a8af941b36a8f3f608271078e32b093d9108 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17mb/google/cyan: use shared touchpad/touchscreen interruptsMatt DeVillier
Windows (10/11) freaks out and generates an interrupt storm if two ACPI devices are enabled and share an interrupt, even when only one device is actually present. To mitigate this, mark Cyan's touchpad/touchscreen interrupts as SharedAndWake rather than ExclusiveAndWake. Test: build/boot Windows 10 on Relm, observe normal CPU usage in Task Manager for System Interrupts task when touchpad/touchscreen in use. Change-Id: I09bc878318f9fa6252f65a42ad46109418805fa0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17mb/google/trogdor: Adjust mipi panel backlight gpioZanxi Chen
According hareware design, mipi panel backlight relies on AP_BKLTEN(GPIO_12) and TP_EN(GPIO_85). Meanwhile, TP_EN(GPIO_85) needs pull up to enable PP3300_DISP_ON before AP_BKLTEN(GPIO_12) up. BUG=b:197709288,b:199081803,b:205166230 BRANCH=trogdor TEST=emerge-strongbad coreboot Change-Id: Ie9920e5366f6b1ea9e0da228bd211317516b390a Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-17mb/google/brya/var/taeko: Correct touchpad GPE settingsJoey Peng
Correct GPE settings so touchpad can wake up DUT. BUG=b:206526991 TEST=emerge-brya coreboot and builds without error Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I1978e9220ad7a275d351ad5eeff7036131926b24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17mb/google/brya/var/taeko: disabled autonomous GPIO power managementJoey Peng
Used H1 firmware where the last version number is 0.0.22, 0.3.22 or less to production that will need to disable autonomous GPIO power management and then can get H1 version by gsctool -a -f -M BUG=b:205315500 TEST=emerge-brya coreboot and test that DUT can boot to OS. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ib26797fa2d4d0b1a6eb28c5d79b9ac0a6054abd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17mb/google/brya/variants/primus: Correct SSD power sequenceCasper Chang
SSD sometimes can't be detected in in warm/cold boot stress. M.2 spec describes SSD_PERST# should be sequenced after power enable. BUG=b:199967106 TEST=SSD was always discovered in warm/cold boot stress. Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I74c21cd96cf1c4518c4ed7c0b3b39e915b6b1ff7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17mb/google/brya: Enable early EC syncBoris Mittelberg
Enable VBOOT_EARLY_EC_SYNC in corebot BUG=b:201356952 BRANCH=None TEST=Tested on Brya id 2 Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: I6e480d64a5d90d5bb9cf59ed60b7b53af9edf46a Reviewed-on: https://review.coreboot.org/c/coreboot/+/59274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17mb/google/hatch: Add VBTs for variantsMatt DeVillier
Add VBTs for all hatch variants currently supported by ChromeOS recovery images. For variants which use multiple VBTs and select at runtime, ensure these are added directly to CBFS. Change-Id: I3c62ce204e3272e778ba0a34f7a47a65d8125f53 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17mb/google/hatch: Alphabetize variants in Kconfig.nameMatt DeVillier
Change-Id: Ie29242e635bae1e2754bc1109754a64cb496af29 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17mb/google/brya: Move typeC AUX configuration to variantEric Lai
TypeC AUX configuration is variant specific. So move into variant level. BUG=b:205235144 TEST=No typeC port 0 AUX in felwinter. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I02bfea462cf4c6359fd8d5cca4368786ee03bc8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17mb/google/guybrush: Update SPKR GPIO configuration for guybrush/nipperkinKevin Chiu
For Guybrush Board Version 2, Nipperking Board Version 1, update SPKR GPIO to match H/W schematic: SPKR: GPIO31 For Nipperkin Board Version 2, update SPKR GPIO to match H/W schematic: SPKR: GPIO70 BUG=b:202992077 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Change-Id: I3d82292b116f53d85d9518364ffd2169bd915a7e Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59051 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-17mb/google/octopus: Add missing VBTs for variantsMatt DeVillier
Add VBTs for all octopus variants currently supported by ChromeOS recovery images. For variants which use multiple VBTs and select at runtime, ensure these are added directly to CBFS. Change-Id: I4b5c4268f9255d658f9762d94488db66e0677830 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17mb/google/octopus: Alphabetize variants in Kconfig.nameMatt DeVillier
Change-Id: I2e57c4f1baa8a42bde2642e7f76ddead7bfd6a58 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17mb/google/slippy/peppy: use shared touchpad interruptsMatt DeVillier
Windows (10/11) freaks out and generates an interrupt storm if two ACPI devices are enabled and share an interrupt, even when only one device is actually present. To mitigate this, mark Peppy's interrupts as Shared rather than the default of Exclusive. Test: build/boot Windows 10 on Peppy, observe normal CPU usage in Task Manager for System Interrupts task when touchpad in use. Change-Id: Ida78ddec3105cef6581cdde78da2e2c97d983a0a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17soc/mediatek/mt8186: Add RTC and clkbuf driversYuchen Huang
Add support for RTC and clkbuf. TEST=boot to kernel and check log ok BUG=b:202871018 Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com> Change-Id: Ia02a74f685feb2466c113a77cbfa3a7d8fedb595 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-17mb/google/corsola: Initialize SPMRex-BC Chen
Initialize SPM (System Power Management) in RAM stage. This adds 55ms to the boot time. TEST=program counter of SPM is correct value(0x250) after booting up BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I822417f7a679107760b202dd43fb79d1934940bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/59342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-17soc/mediatek: move MSDC drivers to soc folderRex-BC Chen
Setting of MSDC is defined by soc, so we move them to soc folder. TEST=emerge-cherry coreboot; emerge-asurada coreboot Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I84ad8a4cde120c97024870ebf750d44b36c2284d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-17mb/google/brya/variants/primus: enable ALC5682I-VSMalik_Hsu
In next phase build, the audio codec will change to ALC5682I-VS BUG=b:205883511 TEST=emerge-brya coreboot chromeos-bootimage and check audio function Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I5906ef9bb88da7fe450a986bf7dd1ee701227f95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-16mb/google/brya/var/redrix: Update dsm parameters for speeker/tweeterWisley Chen
For tuning, redrix needs differnet dsm paramters file for L/R speeker/tweeter. BUG=b:204841998 TEST=build Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I6f93603a6809f9a5aea9f2e554935de5d0457286 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-16soc/mediatek/mt8186: add early initialization for eMMCRex-BC Chen
Some eMMCs need 80+ms for CMD1 to complete. And the payload may need to access eMMC in the very early stage (for example, depthcharge needs it 20ms after started) so we have to start initialization in coreboot. TEST=boot kernel from eMMC ok BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I3bc06b1fc506b1d6f54f7f456117d22477a87e29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-16mb/google/corsola: Configure eMMC and SD CardWenbin Mei
The Corsola reference design has both eMMC and SD Card interfaces so we have to configure both in RAM stage. TEST=boot kernel from eMMC and SDCard ok BUG=b:202871018 Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: I0fa8712eb61685a305dc5dd49cc2e55f1f0eecd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-16soc/mediatek/mt8186: Configure eMMC and SD CardWenbin Mei
The Corsola reference design has both eMMC and SD Card interfaces so we have to configure both in RAM stage. TEST=build pass BUG=b:202871018 Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: I2f26a8a11edd29a80a7195e3a324151d66ecb293 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-16mb/google/brya/var/vell: Generate LP5 RAM IDKevin Chiu
Add the support LP5 RAM parts for vell: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) BUG=b:204284866 TEST=emerge-brya coreboot Change-Id: I49745948ebdb25fd98e285defd75714f80271968 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2021-11-16mb/google/guybrush: Make GPIO_69 default for SD_AUX_RESET_LRob Barnes
In CL:3248796 GPIO_5 was made the default for SD_AUX_RESET_L. No variant is actually using GPIO_5 for SD_AUX_RESET_L. Making GPIO_69 the default and only overriding to GPIO_70 for guybrush bid==1. BUG=b:202992077 BRANCH=None TEST=Build and boot guybrush, SD card works Change-Id: I6546ad9961f6f7146aa3aefc35d39a2eb282a252 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-15mb/google/brya/var/redrix: Hook up two missing sensorsWisley Chen
Redrix has 4 thermal sensors, so add the missing sensors settings. BUG=b:200134784 TEST=build and verified by thermal team. Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Ia9c58129d439ade21e96896c5e593cd08a627603 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-11-15mb/google/herobrine: Use same I2C/SPI configs for piglin and hoglinShelley Chen
As Hoglin variant was recently added, need to make sure that it uses the same configs as piglin. BUG=b:197366666 BRANCH=None TEST=create hoglin image and make sure that it boots on CRD 2.0 Change-Id: I14497a205262ac1081c24631e4fd8d39bb804fce Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59273 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-15Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"Hsuan-ting Chen
This reverts commit adb393bdd6cd6734fa2672bd174aca4588a68016. This relands commit 6260bf712a836762b18d80082505e981e040f4bc. Reason for revert: The original CL did not handle some devices correctly. With the fixes: * commit 36721a4 (mb/google/brya: Add GPIO_IN_RW to all variants' early GPIO tables) * commit 3bfe46c (mb/google/guybrush: Add GPIO EC in RW to early GPIO tables) * commit 3a30cf9 (mb/google/guybrush: Build chromeos.c in verstage This CL also fix the following platforms: * Change to always trusted: cyan. * Add to early GPIO table: dedede, eve, fizz, glados, hatch, octopus, poppy, reef, volteer. * Add to both Makefile and early GPIO table: zork. For mb/intel: * adlrvp: Add support for get_ec_is_trusted(). * glkrvp: Add support for get_ec_is_trusted() with always trusted. * kblrvp: Add support for get_ec_is_trusted() with always trusted. * kunimitsu: Add support for get_ec_is_trusted() and initialize it as early GPIO. * shadowmountain: Add support for get_ec_is_trusted() and initialize it as early GPIO. * tglrvp: Add support for get_ec_is_trusted() with always trusted. For qemu-q35: Add support for get_ec_is_trusted() with always trusted. We could attempt another land. Change-Id: I66b8b99d6e6bf259b18573f9f6010f9254357bf9 Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15mb/google/brya/var/felwinter: Disable PCIE port 6Eric Lai
PCIE port 6 is empty as per schematics. BUG=b:206047996 TEST=PCIE port 6 is disabled. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I30fa897c9310c44545e3df670895639a5144e1de Reviewed-on: https://review.coreboot.org/c/coreboot/+/59243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-15mb/google/brya/var/felwinter: Remove USB2 port 0Eric Lai
USB2 port 0 is empty as per schematics. BUG=b:206047996 TEST=USB2 port 0 is disabled. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I45d467a80c23d82dc33dcbed176430a758eea403 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-15mb/google/brya/var/felwinter: Enable garage pen detectionEric Lai
Enable garage pen detection. BUG=b:197912223 TEST=Check evtest can trigger event when toggling the switch. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib5929c876d1a0da34dadd7997a61ab8e75acbbb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-15mb/google/brya/variants/primus: enable RTD3 for PCIe-eMMC bridgeMalik_Hsu
Enable RTD3 driver for PCIe-eMMC bridge, If the board version is less than 1, do not enable RTD3 driver. BUG=b:204469567 TEST=Boot into eMMC storage and perform suspend stress 100 cycle passed Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I5836d65cedfe3907af2c4c33de7a396c4bb8b727 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-15mb/google/brya/variants/gimble: Update PL1 min valueSumeet Pawnikar
Update PL1 minimum value from 3W to 12W as per the thermal design discussed in this bug 203371203 comment #10. BUG=b:203371203 BRANCH=None TEST=Build and boot the gimble system Change-Id: Id66cfb6f6dc0217bd4d83eae1d66ad867a1bdb46 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-15mb/google/brya/var/kano: Add thermal sensor settingsDavid Wu
Kano has 3 thermal sensors, so add the missing sensor settings. BUG=b:205648035 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I0da25f142149f94c83fdf7b2ba2cb8694cddb412 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-11-15mb/google/brya: Create vell variantShon Wang
Create the vell variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:205908918 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_VELL Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Change-Id: Ide8ba1c0dd9b5d9ad90556053abf2a597136a10c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-15mb/google/corsola: Add VMCH and VMC for regulator interfaceRex-BC Chen
Add VMCH and VMC for providing power of SDCard. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I50fc87415086eb22ff35d157dba38cfd7594cc40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15soc/mediatek/mt8186: add USB supportRex-BC Chen
1. Enable and setup USB drivers. 2. Pull up to a weak resistor for USB3_HUB_RST_L and we reset the hub via GPIO149. TEST=boot kernel from USB ok BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ifcc11d51b0c1e495477957111e6021ef8275f629 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15mb/google/corsola: Implement regulator interfaceRex-BC Chen
Use regulator interface to use regulator more easily. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ied43cba51036c62a120df2afffeb63b5d73f012b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15mb/google/corsola: add configuration for kingler and krabbyRex-BC Chen
The 'corsola' reference design will include two implementations with different BOM selections - 'krabby' and 'kingler'. TEST=none BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Iaf9c6af1a395030937a9a5c00e95d7246ddcb6eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/59249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15soc/mediatek/mt8186: Add support for PMIC MT6366James Lo
Add basic support for VCORE/VDRAM1/VDDQ of MT6366. TEST=build pass BUG=b:202871018 Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com> Change-Id: I22e30421560a32f4a9e15899e8150376b1414494 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-13mb/google/guybrush: Add variant_espi_gpio_tableRob Barnes
Add separate gpio table for early eSPI bus init. Remove espi GPIO from early_gpio_table. This allows for initializing eSPI separately from other GPIOs. Simplify verstage_mainboard_early_init. BUG=b:200578885 BRANCH=None TEST=Build and boot guybrush Change-Id: I0cd439f207df7c27575ae363b207293d40485bf8 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-11-13Revert "mb/google/brask: Correct GPIO GPP_R6 and GPP_R7 setting"David Wu
This reverts commit ba6fdc892d62741e456ac5628fcd6f869c4cb9af. Reason for revert: Refer to intel doc #627075 (Intel_600_Series Chipset_Family_PCH_GPIO_Impl_Sumry_ Rev1p5p1), GPP_R6 ~ GPP_R7 should be NF3 for dmic. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I460fd99b4ad4b9c470f692032ff7ea2b51cad388 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-12google/stout: Remove duplicate recovery mode switch entryKyösti Mälkki
Change-Id: I6e742b9d5256da2b7edcca0efda4faf999207465 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-12google/butterfly: Refactor get_recovery_mode_switch()Kyösti Mälkki
Do not place console output in low-level GPIO functions. The caller of get_recovery_mode_switch() is in vboot_logic.c that is linked in romstage. So presumably recovery mode is broken and is not fixed with this commit either. Change-Id: I2a0fdbb370d54898c72adb29a0e9b990a5fc0ce1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-12mb/google/trogdor: Modify BOE panel_id for mrblandZanxi Chen
Modify BOE panel_id for mrbland due to hardware changes. BUG=b:205166230,b:198548221 BRANCH=trogdor TEST=emerge-strongbad coreboot Change-Id: I65fecd854c4e3443edc07a44a1d43572d5030e4c Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58995 Reviewed-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-12mb/google/brya/var/primus: Disable autonomous GPIO power managementCasper Chang
Used H1 firmware where the last version number is 0.0.22, 0.3.22 or less to production that will need to disable autonomous GPIO power management and then can get H1 version by gsctool -a -f -M BUG=b:201054849 TEST=USE="project_primus emerge-brya coreboot" and verify it builds without error. Change-Id: If5a99a96e5d4b84be3f2c1165283ce249ca75d58 Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-12google/deltaur,drallion,sarien: Refactor ChromeOS GPIOsKyösti Mälkki
Low-level GPIOs should not depend on late cros_gpios that should be guarded with CHROMEOS and implemented for the purpose of ACPI \OIPG package generation. Change-Id: Ibe708330504bc819e312eddaf5dfe4016cda21a1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-12mb/google,intel: Add ChromeOS GPIOs to onboard.hKyösti Mälkki
Change-Id: Ia473596e3c9a75587cd1288c8816bfef66bef82e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-11mb/google/brya/var/felwinter: Enable SaGvEric Lai
Enable SaGv. BUG=b:198235324 TEST=Boot into without issues. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I3cbff8d28bb5b5bfdad323f348b9f880245d049d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-11mb/google/brya/var/kano: Configure USB2 and USB3 portDavid Wu
Disable unused USB2 and USB3 port BUG=b:192370253 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ia2fa10fb21e0a42e51728bc3d78163ca213f8d91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-11mb/google/brya/var/kano: Add gpio-keys ACPI node for PENHDavid Wu
Use gpio_keys driver to add ACPI node for pen eject event. Also setting gpio wake pin for wake events. BUG=b:192415743 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ia36119678cfd5c65a62685d3312537d9aa21e83b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-11-11mb/google/guybrush: Define ACPI Power Resources for FPMCUKarthikeyan Ramasubramanian
Currently all the power sequencing for FPMCU is done explicitly in different stages of coreboot. This can all be done by adding ACPI power resources for FPMCU and clean up the unused code. Here is the expected power sequence: PowerUp : Assert EN_PWR_FP -> 3 ms delay -> De-assert FPMCU_RST_ODL Shutdown : De-assert EN_PWR_FP -> Assert FPMCU_RST_ODL Reboot : Shutdown -> 200 ms delay -> PowerUp BUG=None TEST=Build and boot to OS in Guybrush. Ensure that the FP is able to unlock the system after the first login attempt. Ensure that the FP is able to wakeup the system. Observed that the power resource is added correctly in the FPMCU ACPI object Name (_PR0, Package (0x01) // _PR0: Power Resources for D0 { PR01 }) Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot { PR01 }) PowerResource (PR01, 0x00, 0x0000) { Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x01) } Method (_ON, 0, Serialized) // _ON_: Power On { \_SB.CTXS (0x0B) \_SB.STXS (0x20) \_SB.STXS (0x0B) } Method (_OFF, 0, Serialized) // _OFF: Power Off { \_SB.CTXS (0x0B) \_SB.CTXS (0x20) } } Change-Id: I52322eaecf6961ff9a196ca9ab2d58b7d4599d4f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-11mb/google/brya/var/taeko: Enable CPU PCIE RP 1Joey Peng
Modify settings to enable CPU PCIE RP 1 according to schematics. BUG=b:205504257 TEST=emerge-brya coreboot and can successfully boot with ssd and emmc. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I0f817c860f2b295c6aa84fa1999d374d99f817f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-02 08:29:56 +0000