diff options
| author | Wisley Chen <wisley.chen@quanta.corp-partner.google.com> | 2021-11-12 22:02:34 +0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-18 23:31:40 +0000 |
| commit | cd04c6e07db851be7b9d7de2224dc6f853e4379a (patch) | |
| tree | d8b30973896a9ea57e32e95c3608460616de9f35 /src/mainboard/google | |
| parent | e589ee38794ff02ec258c7bee347ccdcb35f170a (diff) | |
mb/google/brya/var/redrix: Correct WWAN power sequence
Correct the WWAN power sequence to meet spec
BUG=b:206079177
TEST=build
Change-Id: Ibba1ecc04b563ae4eedd7596594f33812cbac150
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google')
4 files changed, 34 insertions, 5 deletions
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 4afee7423b..11f9b69c64 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -42,6 +42,7 @@ config BOARD_GOOGLE_REDRIX select DRIVERS_GENESYSLOGIC_GL9755 select DRIVERS_GFX_GENERIC select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select HAVE_WWAN_POWER_SEQUENCE config BOARD_GOOGLE_KANO bool "-> Kano" diff --git a/src/mainboard/google/brya/variants/redrix/Makefile.inc b/src/mainboard/google/brya/variants/redrix/Makefile.inc index acf9bada81..446d113a80 100644 --- a/src/mainboard/google/brya/variants/redrix/Makefile.inc +++ b/src/mainboard/google/brya/variants/redrix/Makefile.inc @@ -1,6 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c +romstage-y += gpio.c + ramstage-y += gpio.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/brya/variants/redrix/gpio.c b/src/mainboard/google/brya/variants/redrix/gpio.c index f35e0fd40e..20d6b48c48 100644 --- a/src/mainboard/google/brya/variants/redrix/gpio.c +++ b/src/mainboard/google/brya/variants/redrix/gpio.c @@ -37,13 +37,14 @@ static const struct pad_config override_gpio_table[] = { PAD_NC(GPP_E3, NONE), /* E7 : PROC_GP1 ==> NC */ PAD_NC(GPP_E7, NONE), + /* E16 : RSVD_TP ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_E16, 1, DEEP), /* E20 : DDP2_CTRLCLK ==> NC */ PAD_NC(GPP_E20, NONE), /* E22 : DDPA_CTRLCLK ==> NC */ PAD_NC(GPP_E22, NONE), /* E23 : DDPA_CTRLDATA ==> NC */ PAD_NC(GPP_E23, NONE), - /* F20 : EXT_PWR_GATE# ==> NC */ PAD_NC(GPP_F20, NONE), @@ -67,11 +68,17 @@ static const struct pad_config override_gpio_table[] = { PAD_NC(GPP_S6, NONE), /* S7 : SNDW3_DATA ==> NC */ PAD_NC(GPP_S7, NONE), - + /* + * E0 : SATAXPCIE0 ==> WWAN_PERST_L + * Drive high here, so that PERST_L is sequenced after RST_L + */ + PAD_CFG_GPO(GPP_E0, 1, DEEP), }; /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */ + PAD_CFG_GPO(GPP_A12, 1, DEEP), /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ @@ -91,16 +98,18 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_D2, 1, DEEP), /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ PAD_CFG_GPO(GPP_D11, 1, DEEP), - /* E0 : SATAXPCIE0 ==> NC */ - PAD_NC(GPP_E0, NONE), + /* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */ + PAD_CFG_GPO(GPP_E0, 0, DEEP), /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ PAD_CFG_GPI(GPP_E13, NONE, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), - /* E16 : RSVD_TP ==> WWAN_RST_L */ + /* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */ PAD_CFG_GPO(GPP_E16, 0, DEEP), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */ + PAD_CFG_GPO(GPP_F21, 0, DEEP), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ @@ -115,6 +124,11 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_B4, 0, DEEP), }; +static const struct pad_config romstage_gpio_table[] = { + /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */ + PAD_CFG_GPO(GPP_F21, 1, DEEP), +}; + const struct pad_config *variant_gpio_override_table(size_t *num) { *num = ARRAY_SIZE(override_gpio_table); @@ -126,3 +140,9 @@ const struct pad_config *variant_early_gpio_table(size_t *num) *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/redrix/include/variant/gpio.h b/src/mainboard/google/brya/variants/redrix/include/variant/gpio.h index c4fe342621..99d09b2432 100644 --- a/src/mainboard/google/brya/variants/redrix/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/redrix/include/variant/gpio.h @@ -5,4 +5,10 @@ #include <baseboard/gpio.h> +#define WWAN_FCPO GPP_F21 +#define WWAN_RST GPP_E16 +#define WWAN_PERST GPP_E0 +#define T1_OFF_MS 16 +#define T2_OFF_MS 2 + #endif |