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2020-09-06mb/*: devicetree: drop now unneeded USBx_PORT_EMPTYMichael Niewöhner
Setting USBx_PORT_EMPTY is not a requirement anymore, since unset devicetree settings default to 0 and the OC pin now only gets set when the USB port is enabled (see CB:45112). Thus, drop the setting from all devicetrees. Change-Id: I899349c49fa7de1c1acdca24994ebe65c01d80c6 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-09-04mb/*/Kconfig: Drop redundant 'select CPU_INTEL_HASWELL'Elyes HAOUAS
CPU_INTEL_HASWELL is already selected at nb/intel/haswell/Kconfig. Change-Id: I608286aae72bc740be642a72109472fb235f37bf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-04mb/google/volteer/variant/lindar: Update memory settingsRasheed Hsueh
Based on the Lindar's schematic, generate memory settings. util: rename lp4x spds to include "lp4x-" in name BUG=b:161089195 TEST=FW_NAME=lindar emerge-volteer coreboot chromeos-bootimage Signed-off-by: Rasheed Hsueh <rasheed.hsueh@lcfc.corp-partner.google.com> Change-Id: I1ec35d62f8ed21356329b78a614114edad78c2bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/45064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Michael Niewöhner
2020-09-03soc/intel/cnl: Add new Kconfig option which matches its FSPs nameFelix Singer
Since there are 4 different versions of FSPs for the Comet Lake platform, add a new Kconfig option for the currently used SoC being able to differ between the various SoCs and FSPs. The new Kconfig option selects the Comet Lake SoC as base for taking over its specific configuration and is only used for configuring the path to its specific FSP header files and FSP binary. Also, adjust all related mainboards so that their Kconfig selects the new option. For details, please see https://github.com/intel/FSP/tree/master/CometLakeFspBinPkg Built System76/lemp9 with BUILD_TIMELESS=1 before and after this patch and both images are equal. Change-Id: I44b717bb942fbcd359c7a06ef1a0ef4306697f64 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-09-03mb/google/volteer/variants/volteer: route GPP_F14 via APICAlex Levin
GPP_F14 should be configured to be routed via APIC and not SCI. BUG=b:162528549 TEST=verified on a volteer Change-Id: Ie262ceeaea1c07bcc99e1545f5eb99e0d0dee905 Signed-off-by: Alex Levin <levinale@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44948 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-03mb/google/zork: update DRAM table for berknipKevin Chiu
Add Dual DDR4 Samsung K4AAG165WA-BCTD 16Gb x 8 BUG=b:165956925 BRANCH=zork TEST=1. gen part id by gen_part_id 2. emerge-zork coreboot Change-Id: Ia21a561e9b89feeccb6509d9280eaf52cfc2f5a3 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-03trogdor: Assert EN_PP3300_HUBJulius Werner
Some Trogdor variants power their USB hub from a PMIC LDO that is already enabled by QcLib, and some have a discrete LDO that is controlled by GPIO_84. For the latter, let's make sure we assert that GPIO on boot. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I9d206cd7154ded3bf179e68c2b1421d0a8ee89f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: mturney mturney <mturney@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Philip Chen <philipchen@google.com>
2020-09-03trogdor: Shuffle RAM and SKU ID pins (again)Julius Werner
We're moving a lot of pins around on Trogdor again. For firmware this only affects the RAM and SKU strapping ID pins. Since there are quite a few of the old devices in circulation this time and some people seem to care about mosys RAM information working, let's actually check the board revision and support both cases this time. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If7728d8ea4b7f6e7ff6721ade90f975f6efd5ddd Reviewed-on: https://review.coreboot.org/c/coreboot/+/44949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Philip Chen <philipchen@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-09-02mb/google/puff/var/noibat: Update DPTF parameters for noibatWisley Chen
1. Update paramerters form thermal team. 2. Update PL2 Max/Min to 51W/15W. BUG=b:167494420 BRANCH=puff TEST=build noibat and verified by thermal team. Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: Id96e681e9a990a1a1eaeb22781b1c60a7369118b Reviewed-on: https://review.coreboot.org/c/coreboot/+/45020 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-02mb/google/puff: Update DPTF parameters and TCC offset for faffyDavid Wu
1. Set tcc offset to 5 degree celsius 2. Apply the DPTF parameters receive from the thermal team. 3. Change PL2 min value from 25W to 15W. BUG=b:167477885 BRANCH=puff TEST=build and verify by thermal team Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I68fdefe99cf36a39797c29ad84d08321bb8175f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-09-02mb/*/Kconfig: Drop redundant 'select DRIVERS_INTEL_WIFI'Elyes HAOUAS
DRIVERS_INTEL_WIFI is already set to yes. Change-Id: I09f628a9c1feb8992b6fe7c7ca93c75243ffc0f1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-09-02Revert "mb/google/volteer/variant/lindar: Update memory settings."Patrick Georgi
This reverts commit 2ad859988b5243411393fdf3116eea281b92b1bb. Reason for revert: broke the build Change-Id: I7e7d917c2e8b698d5c7c3ce0b6d34e80696185f3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44993 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-02mb/google/volteer/variant/lindar: Update memory settings.rasheed.hsueh
Based on the Lindar's schematic, generate memory settings. BUG=b:161089195 TEST=FW_NAME=lindar emerge-volteer coreboot chromeos-bootimage Signed-off-by: rasheed.hsueh <rasheed.hsueh@lcfc.corp-partner.google.com> Change-Id: I75fb9254ec7aa40acc2e125f0c4fd31003d28be6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-09-02mb/google/poppy/var/rammus: Update SPD table for RammusKane Chen
1. Add new SPD file, "samsung_dimm_K4E8E324ED-EGCG.spd.hex". 2. Add SPD support in Rammus memory table, as follows: SPD_SOURCES += samsung_dimm_K4E8E324ED-EGCG # 0b0110 SPD_SOURCES += samsung_dimm_K4E6E304ED-EGCG # 0b0111 BUG=b:166576463 BRANCH=firmware-rammus-11275.B TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I82386507c4e996e0a59c26ce50de3bced45b1196 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44854 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-02mb/google/sarien/Kconfig: Drop redundant 'select TPM2'Elyes HAOUAS
TPM2 set to yes by MAINBOARD_HAS_TPM2 at security/tpm/Kconfig file. Change-Id: I815d545618e2e734f8e9b65731bbb4bed0b2d93d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-02src: Drop redundant 'select BOOTBLOCK_CONSOLE'Elyes HAOUAS
BOOTBLOCK_CONSOLE is already set to yes in console/Kconfig file. Change-Id: I2a4ee517795bc7b378afc5eae92e2799ad36111b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-09-02mb/google/kukui: Add LPDDR4X support for fennel/cerise/sternxuxinxiong
Modify the BOARD_SDRAM_TABLE_OFFSET as 0x10 BUG=b:162891673 BRANCH=kukui TEST=make Change-Id: I5a4794d6e899e35686c40a553b991643f9e35ea3 Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jianbo Zhang <zhangjianbo@huaqin.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
2020-09-01mb/google/puff: Update DPTF parameters for kaisa and duffyDavid Wu
1. Apply the DPTF parameters receive from the thermal team. 2. Change PL2 min value from 25W to 15W. 3. Change PL2 max value from 64W to 51W. BUG=b:166696500 BRANCH=puff TEST=build and verify by thermal team Change-Id: I53a4e8809369883c3ba77744fdc05fb510408209 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44903 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-01{include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistentSubrata Banik
Convert 0X -> 0x Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Iea3ca67908135d0e85083a05bad2ea176ca34095 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-01mb/google/puff: Convert ASL file to new DPTF dt implEdward O'Callaghan
This patch converts the current DPTF policies from static ASL files into the new SSDT-based DPTF implementation. All settings are intended to be copied exactly. BUG=b:158986928 BRANCH=puff TEST=duffy boots and dumped SSDT table for quick check. Change-Id: I45987f44ec381917173f8d2a878edb50da454b4b Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-08-31mb/google/zork: Fix SPD typo in trembyle makefileRob Barnes
Relative path to spd directory was wrong. BUG=b:167175547 TEST=Boot Trembyle SKU 2 Change-Id: I63ae4f39ba69d2d80c25ac7383b6eb953901f56d Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44946 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31mb/google/zork: Fix active polarity of REPORT_EN pin in overridetreeFurquan Shaikh
GPIO_144 is REPORT_EN pin for the touchscreen controller where 1 means enable operation and 0 means stop operation. Override tree exposes this pin as stop GPIO. Thus, it needs to be configured as active low i.e. 0 = active (stop), 1 = inactive (enable report). Change-Id: I349123655260349b78d2f75f846da0ce1dc966fc Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-31mb/google/zork: Fix active polarity of touchscreen reset GPIO in overridetreeFurquan Shaikh
v3.6+ of reference schematics have moved to using active low polarity for touchscreen GPIO. This change sets the default polarity in override tree accordingly to active low. To support boards from older builds, variant_touchscreen_update() already updates the polarity to active high. BUG=b:161937506 Change-Id: I370bdb27ea5d0601612d13b515113a6048018964 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-31mb/google/dedede/var/drawcia: Add elan USI touchscreenWisley Chen
BUG=b:155002684 TEST=emerge-dedede coreboot chromeos-bootimage Change-Id: I87d8575131e745dec818bc5864ca6b21ce0825af Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-08-31mb/google/zork/dalboz: move PCIe GPP clock setting to devicetreeFelix Held
BUG=b:149970243 BRANCH=zork Change-Id: I0b31466c5a991b02cef3432942f8de45805fe546 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44891 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31mb/google/zork/trembyle: add PCIe GPP clock setting to devicetreeFelix Held
BUG=b:149970243 BRANCH=zork Change-Id: Ie3fc83484c6ce769956dc8e6e57194ffebb4f5b0 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44890 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31mb/google/zork: update GPIO config for dirinbozKevin Chiu
dirinboz does not support stylus, config AGPIO4/5 to NC to prevent unexpected wake event for s3. BUG=none BRANCH=zork TEST=emerge-zork coreboot chromeos-bootimage Change-Id: I3cfdeb326c3d3775148b2a00732c7d848dab35cb Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44894 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31mb/google/zork: update GPIO config for berknipKevin Chiu
berknip does not support stylus, config AGPIO4/5 to NC to prevent unexpected wake event for s3. BUG=b:162376046 BRANCH=zork TEST=emerge-zork coreboot Change-Id: I8d9b711ce1d7300181fe496d490dd33b38bc5983 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44893 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31mb/google/volteer: Add probed fw_configs to SMBIOS OEM stringsTim Wawrzynczak
Some Linux kernel drivers bind to "DMI quirks." In this case, the audio fw_config is added as an OEM string, e.g., "AUDIO-MAX98357_ALC5682I_I2S" so the audio topology can be correctly discovered. But add all successfully probed fw_config items as well, because this makes it easier to view what is selected from userspace. BUG=b:161963281 TEST=With CBI FW_CONFIG field set to 0x201: localhost ~ # dmidecode -t 11 # dmidecode 3.2 Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x0009, DMI type 11, 5 bytes OEM Strings String 1: DB_USB-USB4_GEN2 String 2: AUDIO-MAX98373_ALC5682I_I2S Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7b7586b0ebfe7b2fd888f448a50ae086364fa718 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-31mb/google/volteer: add GPP_F11 to baseboard gpio_tableNick Vaccaro
GPP_F11 was in the early gpio table, but the definition was missing from the main gpio_table. This change adds GPP_F11 to the gpio_table array. BUG=none TEST="emerge-volteer coreboot" and verify it builds correctly. Change-Id: I40f887300a9dfd4f8e790031b77bbee8a014f499 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-08-31mb/google/volteer: add generic DDR4 SPDs for EldridNick Vaccaro
Add Makefile.inc to include six generic DDR4 SPDs for the following parts for Eldrid: DRAM Part Name DRAM ID to assign H5AN8G6NDJR-XNC 0 (0000) MT40A512M16TB-062E:J 1 (0001) H5ANAG6NCMR-XNC 2 (0010) K4A8G165WC-BCWE 0 (0000) K4AAG165WA-BCWE 3 (0011) MT40A1G16KD-062E:E 3 (0011) Add mem_list_variant.txt as a manifest of eldrid's DRAM parts for use by gen_spd, the generic DD4 SPD generation tool. Add dram_id_generated.txt to specify DRAM ID strap settings. NOTE that Eldrid specified DRAM IDs for the first three parts to be 0 though 2 (i.e. no combined DRAM IDs for parts that use the same SPD). BUG=b:161772961 TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds without error. Change-Id: Ica62e299ed40e60c2d5928b29ead5d2205b1af66 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44272 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31mb/google/volteer/var/halvor: Update TBT2 setting for HalvorFrank Wu
Enable TBT2 setting in overridetree.cb based on schematic. BUG=b:165175296, b:166060548 BRANCH=none TEST=Check all USB ports USB2 and USB3 both functional Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I23ecf76a3c2f631211b0ae2898707c68862b374b Reviewed-on: https://review.coreboot.org/c/coreboot/+/44747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-08-31mb/google/puff: Set TCC offset to 5 for kaisa and duffyDavid Wu
Set tcc offset to 5 degree celsius for kaisa and duffy BUG=b:166696500 BRANCH=puff TEST=Build, and verify test result by thermal team. Change-Id: I2bb977b98c0764f0b9cac3543074da56057717cf Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44901 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30mb/google/volteer: Update flashmap descriptor for CSE Lite FW updateJamie Ryu
To support CSE Lite firmware update, CSE RW partition is extracted from CSE blob binary and added to FW_MAIN_A and FW_MAIN_B. CSE RW size for TGL is close to 2.3MB; hence, the size of FW_MAIN_A and FW_MAIN_B is increased to avoid an overflow. BUG=b:140448618 TEST=build with me_rw binary blob for volteer and boot to kernel. Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: Ie3c2b657f0426d206dfe3729829ec34ff57812c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43790 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30mb/google/kukui: Add LPDDR4X Samsung K4UBE3D4AA-MGCR 4GB support for ↵Kevin Chiu
burnet/esche Add LPDDR4x DRAM index#0 Samsung K4UBE3D4AA-MGCR 4GB BUG=b:165956924 BRANCH=kukui TEST=emerge-jacuzzi coreboot Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I644b65d77b79891ed65215d810b970fe43b29e3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/44821 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28mb/google/zork: Modify USI_RESET_L GPIO 140 to be active to lowKane Chen
Modify USI_RESET_L GPIO_140 in touchscreen power on/off sequence to be active low. BUG=b:160126287 BRANCH=Zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I53dd872fdacb95cda43f297d2c3f9c6723b27bad Reviewed-on: https://review.coreboot.org/c/coreboot/+/44858 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28mb/google/zork: Disable SATA device for all Zork platforms to save powerMatt Papageorge
SATA is currently turned on in the Dalboz and Trembyle base board variant devicetrees, even though no Google/Zork device uses SATA; for mass storage they either use eMMC or NVME PCIe SSDs. This patch disables both the SATA PCIe device and the bus where it was the only enabled device on. The next patch in this patch train sets a new FSP-M UPD setting BUG=b:162302027 Change-Id: Ie7773d9dcb0518c3e01bdd0af23b62268ab64694 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44068 Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28mb/google/zork/woomax: Remove unused memory partsRob Barnes
These parts have not been used in any woomax devices. Removing so IDs can be assigned more efficiently. Command to generate files: go build gen_part_id.go local variant=woomax ./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/${variant}/spd/ ../../../src/mainboard/google/zork/variants/${variant}/spd/mem_parts_used.txt BUG=b:165611555 TEST=none Change-Id: I651539c2df8e6d817582573d45b9e77156ece7d4 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-28mb/google/zork/berknip: Remove unused memory part IDsRob Barnes
These parts have not been used in any berknip devices. Removing so IDs can be assigned more efficiently. Command to generate files: go build gen_part_id.go local variant=berknip ./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/${variant}/spd/ ../../../src/mainboard/google/zork/variants/${variant}/spd/mem_parts_used.txt BUG=b:165611704 TEST=none Change-Id: I9020fc9cbbb4a97664b0c969dd841c5696a4d60f Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44871 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28mb/google/zork/dirinboz: Remove unused memory part IDsRob Barnes
These parts have not been used in any dirinboz devices. Removing so IDs can be assigned more efficiently. Command to generate files: go build gen_part_id.go local variant=dirinboz ./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/${variant}/spd/ ../../../src/mainboard/google/zork/variants/${variant}/spd/mem_parts_used.txt BUG=b:165611271 TEST=none Change-Id: I605550d44ba57d979df1bd5bef114f8ecc94fa3a Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44846 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28mb/google/zork: Switch zork to use spd_toolsRob Barnes
Switch all zork boards to use generated generic SPDs from spd_tools. HMAA1GS6CMR6N-VK is unused by Ezkinil, and all other boards, so it was removed. picasso/Makefile.inc was updated to populate the 2nd APCB channel based on APCB_POPULATE_2ND_CHANNEL. This removes the need to suffix spd entires with _x1/_x2. Command to generate files: $ find src/mainboard/google/zork/variants/ -maxdepth 1 -type d | grep -v '/$' | while read b; do n=$(basename ${b}); if [ "${n}" = "baseboard" ]; then continue fi go run util/spd_tools/ddr4/gen_part_id.go src/mainboard/google/zork/spd \ src/mainboard/google/zork/variants/${n}/spd \ src/mainboard/google/zork/variants/${n}/spd/mem_parts_used.txt done BUG=b:162939176 TEST=Boot ezkinil and dalboz check dmidecod -t17 Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I0553858f83d3d1e90cf35bece108768f004a29a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44480 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28mb/google/volteer: add initial SPDs for Elemi variantNick Vaccaro
Add mem_list_variant.txt, a list of memory parts used by elemi SKUs. Add dram_id.generated.txt, a list of dram id's to use for each memory part. Add Makefile.inc, to specify DDR4 and build the SPD file list. BUG=b:165461530 TEST=none Change-Id: I6dbcccf577161cc0c787775e2ac03e0c7039baef Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44650 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28util: Add memory parts needed by zork boardsRob Barnes
Add memory parts needed by zork boards. Attributes are derived from data sheets. BUG=b:162939176 TEST=Compared generated SPDs with data sheets and checked in SPDs Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I67f205f9af24bbc5c12656be1f363a15fe975955 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44447 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28mb/google/volteer: update Delbin SPD for H9HCNNNCPMMLXR-NEENick Vaccaro
I noticed that re-running the lpddr4x SPD parts id tool that generates the variants/VARIANT_NAME/memory/Makefile.inc changed the SPD that is used for the H9HCNNNCPMMLXR-NEE part. $ go run ./util/spd_tools/lp4x/gen_part_id.go \ src/soc/intel/tigerlake/spd src/mainboard/google/volteer/variants/delbin/memory src/mainboard/google/volteer/variants/delbin/memory/mem_list_variant.txt Based on the currently checked in generic SPDs for LPDDR4x, this operation changes the Makefile.inc to use lp4x-spd-3.hex for the H9HCNNNCPMMLXR-NEE part instead of lp4x-spd-2.hex. This change updates that discrepancy in Delbin's memory Makefile.inc. BUG=none TEST=none Change-Id: I9a19ab7b1bcdc3814fdd9c462ca2f590c8ed2935 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44785 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28util: rename lp4x spds to include "lp4x-" in nameNick Vaccaro
Change lp4x spd names to include lp4x memory type (eg. lp4x-spd-1.hex). BUG=b:160157545 TEST=run gen_part_id for volteer variants and verify that it changed spd names to prepend the "lp4x-" to the filename.. Change-Id: I0c59da7eb78f34640aad2e852ca725d3e8571a8e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44784 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28util: volteer/dedede: move generic SPDs to common locationNick Vaccaro
Now that generic SPD files have the memory type prepended to the filename, they can be stored in the same location. This CL moves the generic SPDs to the new location. Change the ddr4 gen_part_id.go and gen_spd.go tools to use "ddr4_spd_manifest.generated" instead of "spd_manifest.generated". Change the lpddr4x gen_part_id.go and gen_spd.go tools to use "lp4x_spd_manifest.generated" instead of "spd_manifest.generated". Move TGL DDR4 and LPDDR4x generic SPDs into a common location. Move JSL DDR4 and LPDDR4x generic SPDs into a common location. Change the volteer/spd/Makefile.inc to use the new path for the spds. Change the dedede/spd/Makefile.inc to use the new path for the spds. BUG=b:165854055 TEST="emerge-volteer coreboot" and verify all variants build correctly. Change-Id: I83b088cb718d15ffd3012c84a12b5231ae84a3e4 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44648 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-27mb/google/volteer*: Enable IPURavi Sarawadi
Enable IPU for Volteer and Volteer2 variants for MIPI camera. BUG=165340186 BRANCH=None TEST=IPU is enabled and shows in lspci. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I66d60474e16c7a9aa8006d42b22510c1495dbd84 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44628 Reviewed-by: Daniel H Kang <daniel.h.kang@intel.corp-partner.google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-27mb/google/puff: Update psyspl2 to 97% of adapter ratingDavid Wu
Set psyspl2 to 97% of adapter rating, based on our experiment results. BUG=b:160676773 TEST=Built and check firmware log. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I4b621a8cc1749ee52a9f16a7ad2ae7a7aa0f7a5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/44805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2020-08-26mb/google/zork: meet SAR depedenciesAaron Durbin
DRIVERS_WIFI_GENERIC is a dependency for these SAR settings. However, coreboot.org builders are not failing, but chromium builders are only for serial configurations. It's not clear as to why. Either way correct this. BUG=b:159304570 Change-Id: I978b622a3a5a2490b0e3aaa14c24807d5afdff9a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44825 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-26mb/google/volteer/variant/lindar: Update gpio and devicetree settingsJulia Tsai
Based on schematic and gpio table of lindar, generate gpio and overridetree.cb settings for lindar. BUG=b:161089195 TEST=FW_NAME=lindar emerge-volteer coreboot chromeos-bootimage Signed-off-by: Julia Tsai <julia.tsai@lcfc.corp-partner.google.com> Change-Id: Ib869eef08433dab367edd46b3dc577190b6673d8 Signed-off-by: rasheed.hsueh <rasheed.hsueh@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
2020-08-26mb/google/asurada: Load dram params from sdram configHuayang Duan
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I2cc38115c27cbbe157fc850bbd88b10ae8001f52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-08-26mb/google/deltaur: Make return values non-constJacob Garber
Returning a const uint32_t doesn't do anything, and it conflicts with the declaration of sku_id() in include/boardid.h. Change-Id: I2719e5782c9977f8ca4ce8f1dd781f092aa73d64 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1428708 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44746 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-26mb/google/zork: add TS/TP support for dirinbozKevin Chiu
TS: ELAN 5015M G2 GTCH7503 HID TS TP: ELAN i2c-hid touchpad BUG=b:161579679 BRANCH=master TEST=1. emerge-zork coreboot chromeos-bootimage 2. power on proto board successfully 3. TP/TS are functional Change-Id: I54aa16d433b6d71a39cca2ddd026a33e4741320f Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-26mb/google/volteer/var/halvor: Update USB relevant GPIO settingsEric Lai
Follow HW schematic to correct DDSP_HPD1/2/3 and USB_OC3 pin. BUG=b:165175296 BRANCH=none TEST=Check all USB ports USB2 and USB3 both functional Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I2f941141d761b1b69bc8f9ef0b0c4516062fec4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/44651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-08-26Reland "mb/google/zork: Revert Don't expose reset GPIO for touchscreen to OS"Furquan Shaikh
This reverts commit 81066b7ce7192432389578fc0f15b3a46da84bad. Reason for revert: The hang observed when not exposing the reset GPIOs was root caused to zork sharing the same I2C bus between touchscreen and touchpad and interleaving of messages during probe which resulted in incorrect information returned back by touchscreen firmware. Exposing the reset GPIO changed the timing of probe and hence helped workaround the hang issue. The touchscreen driver is now fixed to perform I2C transactions in a single transfer and so the hang is no longer observed when reset GPIO isn't exposed. BUG=b:162596241 BRANCH=zork Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ica11c33d542dd2324bb0b8905c5de06047cee301 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-25mb/google/volteer: Enable CSE Board Reset OverrideTim Wawrzynczak
This will ensure that the cold reset is performed when CSE Lite jumps from RO to RW. BUG=b:162977697 TEST=Verify CSE reset is cold (sits in S5 for PCH Min Slp Duration time) Change-Id: Ib1173e219ba46ee3275824220c8cf790b1d497fa Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-08-24mb/google/dedede/var/drawcia: Add Goodix touchscreenWisley Chen
BUG=b:155002684 TEST=emerge-dedede coreboot chromeos-bootimage Change-Id: I89a4a5bbcd26b156a9660f80090bb5c953196b84 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-08-24mb/google/volteer/var/terrador: Add PMC.MUX.CONx devices to devicetreeDavid Wu
Add PMC.MUX.CONx devices to devicetree for terrador. BUG=b:164941862 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I3f5ea4c0fbcc0117934a1ec1c350e867d881eb9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/44543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-24mb/google/volteer/var/todor: Add PMC.MUX.CONx devices to devicetreeDavid Wu
Add PMC.MUX.CONx devices to devicetree for todor. BUG=b:164941862 TEST=FW_NAME=todor emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Iaef603553597685b03e805603352f38d70d65a5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/44542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-24mb/google/zork: update telemetry settings for woomaxChris Wang
update telemetry value with the SDLE test result. BUG=b:158964769 BRANCH=none TEST=emerge-zork coreboot Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ic419ca5ca00e4e8602dbc12212a8a63ed3657e02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-24mb/google/zork: Fix GPIO table for v3.6 schematics for woomaxKane Chen
Add board version switch GPIO table on gpio.c. BUG=b:165887084 BRANCH=Zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I661e16f7b4769e83450f41ff267c0d253441c4cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/44655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-24mb/google/zork: Enable WiFi SAR configsKevin Chiu
BUG=b:159304570 BRANCH=master TEST=1. cros-workon-zork start coreboot-private-files-zork 2. emerge-zork chromeos-config coreboot-private-files-zork \ coreboot chromeos-bootimage Change-Id: Ibf1cca8a039e37acbbd9f97ee6a35414ceb3ca6e Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-24mb/google/dedede: add mainboard_smi_espi_handler for dedede.Kane Chen
By adding mainboard_smi_espi_handler, the espi smi can be handled properly. BUG=b:163382105 TEST=Tested lid close smi can be handled properly in depthcharge stage Signed-off-by: Kane Chen <kane.chen@intel.com> Change-Id: I8a2ecb52d5f6586f8acd57c4965b4238b95e3b64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44564 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24mb/google/kukui: Add LPDDR4X MT53E2G32D4NQ-046 8GB support for burnet/escheKevin Chiu
Add LPDDR4x DRAM index#6 MT53E2G32D4NQ-046 8GB BUG=b:159301679 BRANCH=master TEST=1. emerge-jacuzzi coreboot 2. MT53E2G32D4NQ-046 8GB M/B boot successfully 3. check DRAM size: 8GB Change-Id: I16449591ec576b1c613a5dad511bafac2bb46f04 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-08-24mb/google/volteer: Update settings for FPMCU on HalvorJohn Su
Configure gpio settings for FPMCU on Halvor. BUG=b:153680359 TEST=After flash FP MCU FW, during bootup we see spi id spi-PRP0001:01 in dmesg. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I5503cfe0fb9933e98ed01afeef8cad1345593ac6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44575 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24mb/google/volteer/var/halvor: Correct USB device tree settingEric Lai
Halvor uses TBT 0/1/2 for USB type C. We doesn't use PCIE/USB3 port therefore disable PCIE/USB3 ports and enable TBT 2. Follow volteer to set USB2 OC_SKIP. BUG=b:165175296 BRANCH=none TEST=Check all USB ports USB2 and USB3 both functional Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ifb844ce475f3d58f0c95be0f172fc49edb4cd5fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/44649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-08-24mb/google/dedede/var/magolor: Add device settingsRen Kuo
Add the configuration in device tree: 1. Add HDA,speaker codec and speaker amp setting 2. Add Elan and Goodix touchscreen setting 3. Add user facing camera usb setting 4 Add Synaptics and Elan Touchpad setting 5. Add WiFi configuration BUG=None BRANCH=None TEST=build magolor firmware Change-Id: Ifc562b4a05c8955d2aec105f2f429f926ad1e702 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44633 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24mb/google/volteer/*/gpio.c: add GPP_D16 to early_gpio_tableCaveh Jalali
GPP_D16 is routed to the main power enable pin on several PCIe SD card controllers on SD daughterboards. We should enable the power to these chips as early as possible so they can participate in PCIe enumeration. BUG=b:162722965 TEST=Verified RTS5261 and GL9755 daughterboards enumerate on PCI and can read SD cards. Change-Id: Icf5e770f540e5d1e27b40f270bb004f4196bc7be Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-08-24mb/google/dedede/variants/drawcia: add charger input current throttlingSumeet R Pawnikar
Add charger input current throttling for drawcia system BUG=None BRANCH=None TEST=Built and tested on drawcia system Change-Id: I34fdc23fcd84b5c27c2bada769f7a9049c2a56a5 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-08-24mb/google/zork: Add GPIO_144 in touchscreen power on/off sequenceKane Chen
Add GPIO_144 setting to fix touchscreen function not work. 1. Modify reset pin to stop gpio delay to 200ms. 2. Reset GPIO off delay set to 1ms. 3. Add GPIO_144 as stop GPIO. 4. Stop GPIO off delay set to 1ms. 5. Set disable_gpio_export_in_crs = 1. BUG=b:160126287 BRANCH=Zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I25299861b91cb7b76e512fad743b80221e6ffb4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/44513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-24mb/google/zork: Fix VARIANT_MIN_BOARD_ID_V3_6_SCHEMATICS for WoomaxKane Chen
PROTO stage board version =0. EVT stage board version =1. Modify "VARIANT_MIN_BOARD_ID_V3_6_SCHEMATICS" from 2 to 1 for Woomax EVT configuration. BUG=b:165887084 BRANCH=Zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I894049298bc0313df4fe0a527c55f53ffe56dc8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/44657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-23mb/google/zork: disable non-GPU HD Audio deviceFelix Held
The zork devices use the ACP (audio co-processor) and the I2S interface for audio and not the HDA (HD audio) device and interface. BUG=b:158535201,b:162302028 BRANCH=zork TEST=Equivalent change on Mandolin disabled the non-GPU HDA device with the corresponding FSP change applied. Change-Id: I6c7de881cff8398fe416151fab219142d4fc904a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-23soc/intel/cnl: Configure FSP option PcieRpSlotImplementedNico Huber
Allow configuring FSP option PcieRpSlotImplemented. Also, update all related devicetrees and configure PcieRpSlotImplemented to keep the current behaviour. Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-08-22mb/google/puff: Select cse_board_reset() strong symbolEdward O'Callaghan
Since Puff uses CSE Lite SKU that supports in-field CSME updates an additional reset is triggered when jmp from RO to RW during boot. However this reset is not detected by the cr50 running older firmware because the strapping configuration for EFS2 uses PLT_RST_L to assert to cr50 that a AP reset occured. The older cr50 firmware version of 0.0.22 only monitors AP resets via SYS_RESET_L and hence never detects the reset. To mitigate the issue above a modified reset sequence is required to be performed to signal the reset occured and hence a board-specific cse_board_reset() strong symbol is provided to modify the flow accordingly. V.2: Select CHROMEOS_CSE_BOARD_RESET_OVERRIDE common implementation instead of a local variant in mainboard.c BUG=b:162290856 BRANCH=puff TEST=none Change-Id: I27ab9711aedf92b5af7a58f3b5472ce79f78c8fa Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44454 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-22mb/google/dedede: Enable CSE Board Reset OverrideKarthikeyan Ramasubramanian
This will ensure that the cold reset is performed when CSE Lite jumps from RO to RW. BUG=b:162386991 TEST=Ensure that Drawcia board boots to OS. Ensure that global reset is triggered when cr50 is running firmware versions newer than 0.0.22. On cr50 versions 0.0.22 or older, EC triggers cold reset of AP. Change-Id: I46a390c71e380328cd7fe70214df09553b2db75c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-21mb/google/zork/var/ezkinil: Fix stylus GPIO to enable suspendJosie Nordrum
Make GPIO_4 and GPIO_5 PAD_NC in ezkinil/gpio.c. None of the Ezkinil SKUs use internal stylus and hence pen pads are configured as NC. BUG=b:164892883, b:165342107 TEST=Verified taht pen detect GPIO does not cause spurious wakes. BRANCH=None Signed-off-by: Josie Nordrum <josienordrum@google.com> Change-Id: I7557575cf8b8e0f849e05bda1d69acf61e91a157 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44629 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-21mb/google/zork: provide full range backlight settings to kernelAaron Durbin
Utilize the SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF option to provide full range backlight settings to the kernel. BUG=b:163583825 Change-Id: I3c337fad38e668488800f4d6bc583a82a93659d3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-21mb/google/dedede: Enable IPU for Wdoo and Wdee variantsMaulik V Vaghela
IPU is required to be enabled for platform supporting MIPI camera. IPU is by default disabled in devicetree for all variants. Enable IPU for Waddledoo and Waddledee supporting MIPI camera. BUG=None BRANCH=None TEST=IPU is enabled for platforms and enumerates in lspci. Change-Id: Ia3cf06d78be4301c68bfa8b1118ddff231d24a66 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44271 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-21mb/google/asurada: Fixup BOOT_DEVICE_SPI_FLASH_BUS default valueCK Hu
On MT8192 the SPI flash is actually using a SPI-NOR controller with its own bus. The number here should be a virtual value as (SPI_BUS_NUMBER + 1). Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: Ibc269201a34968c8400d2235e8da2ecd88114975 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-08-20src/mainboard: Escape variable expansion in KconfigPatrick Georgi
Kconfig 5.8 interprets $(...) itself using environment variables, which generally means that they expand to the empty string. \$(...) works with both our current and new Kconfig with the desired behavior (to pass it through unmodified). Change-Id: I726567eeb61d2035560152677d2b4548c1472be9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44584 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-19mb/google/zork/baseboard: Remove unused referenceMatt Papageorge
Remove references to clk_pm_support which is currently ignored by Picasso AGESA FSP. BUG=b:161218965,b:162423378 TEST=Build test Trembyle and Dali, boot to ChromeOS 5 times each Change-Id: Ic5d6abc56821863b68e45c11763f00d2b6410983 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44556 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-19mb/google/volteer: Implement weak function `cse_board_reset`Tim Wawrzynczak
Since Volteer also uses the CSE Lite SKU and the cr50, it is subject to a problem where old cr50 FW will not be able to properly detect an SoC reset, so the reset on cold boots caused by the CSE Lite RO->RW jump should instead get an assist from the EC, which can perform a full cold reset. BUG=b:162977697 TEST=Verify EC performs the cold reset Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ie8ae21c203da218459d5fd30a23be23520ed0598 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-08-19mb/google/volteer: Update settings for trackpad on HalvorJohn Su
Configure gpio settings for trackpad. BUG=b:153680359 TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I525ba688f71b7a1893bcb64c77e02c8e2506d7b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44524 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-19mb/google/zork: remove unused asl files for dirinbozKevin Chiu
BUG=b:161579679 BRANCH=master TEST=1. emerge-zork coreboot chromeos-bootimage 2. power on proto board successfully Change-Id: I713ac3a47c2d47035affb32e6c604b9af23aa90e Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-19mb/google/zork: Adjust Dirinboz I2C valuesKevin Chiu
BUG=b:164757545 BRANCH=master TEST=1. emerge-zork coreboot chromeos-bootimage 2. power on proto board successfully 3. measure i2c freq by scope is close to 400kHz Change-Id: Icb27ff8a4960caaebc542ee4e507f1611da5a77e Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-18mb/google/zork: Clean up bt reset_gpio removalRob Barnes
Clean up of bt reset_gpio removal function. TEST=Boot and observe log showing bt reset_gpio was removed BUG=b:157580724 - Add reset_gpio for Bluetooth Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I1d40ad16dd3c624d4be89d9eea1835cc4e72c03d Reviewed-on: https://review.coreboot.org/c/coreboot/+/44273 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-18mb/google/volteer: Configure DP_HPD as PAD_NC and disable DdiPortHpdJohn Zhao
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function (NF1) without internal pull-down which wrongly presents HPD interrupts. DP_HPD had been removed for EVT design as those events are through eSPI. This change configures GPP_A19 and GPP_A20 to be no connection and disables DdiPort1Hpd and DdiPort2Hpd. BUG=b:162566436 TEST=Booted to kernel and verified no kernel HPD pins assertion message on Volteer EVT board. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ia3245741b776b75073d2b43d36c8ea40b476b3ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/44501 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-18mb/google/dedede: Fix S3 wake using trackpadMeera Ravindranath
Configure TRACKPAD_INT_ODL pad reset config to DEEP and map PMC_GPE_DW to PMC_GPP values. TEST=System should wake from S3 via trackpad Change-Id: I58ce3720e0fdeefb2c9440bb3006897ef80211ea Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-08-18src: Remove unused 'include <delay.h>'Elyes HAOUAS
Change-Id: I6afea5c102299e570378a1656d3dcd329a373399 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44093 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-18src: Remove unused 'include <stddef.h>Elyes HAOUAS
Change-Id: Iae1e875b466f8a195653d897efa1b297c61ad0a5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41912 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17mb/google/volteer: Make devicetree default as Aux Orientation retimer controlledBrandon Breitenstein
With new board designs being introduced it does not make sense for the default devicetree setting to be retimer disabled on port 0 for Aux Orientation. Change the default to be Aux Orintation retimer controlled on all ports and move the SOC controlled overrides to the corresponding overridetree files. BUG=NONE BRANCH=NONE TEST=Built image for delbin and verified that port 0 flip is working. Change-Id: I5ff59493472db096c027d223f2fd61545dc935e2 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2020-08-17mb/google/zork: Switch to normal read mode for EM100Furquan Shaikh
This change sets the EFS config for SPI read mode to normal read mode when using em100. With this, the boot is stable again without any random hangs in PSP. BUG=b:164429022 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I4cd3673dcc44a61905719a57f734df2fb9f4e6e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-17mb/google/dedede/var/magolor: Generate SPD ID for supported partsRen Kuo
Add supported memory parts in the mem_list_variant.txt and generate the SPD ID for the parts. The memory parts being added are: MT53E512M32D2NP-046 WT:E K4U6E3S4AA-MGCR H9HCNNNBKMMLXR-NEE MT53E1G32D2NP-046 WT:A K4UBE3D4AA-MGCR And also remove the deprecated by cl#43989 https://review.coreboot.org/c/coreboot/+/43989 BUG=None TEST=Build the magolor board Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: I3348b7fbeff038b85e7d3c9137517e05a35bf3dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/44408 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17mb/google/zork: adjust i2c2 data hold time for TPKevin Chiu
current setting got 0.278us which is less than the min 0.3us. increase i2c2 data hold time for TP. BUG=b:163613330 BRANCH=master TEST=1. emerge-zork coreboot chromeos-bootimage 2. data hold time measured by scope: 0.3805us Change-Id: I2d564983383c17ed43cc5cc5aaff0fcd67ce6928 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-17mb/google/volteer: Define stop_gpio for goodix touch screenCaveh Jalali
This applies to the goodix touch screen on both the volteer and volteer2 variants: Define GPP_E3 as the stop_gpio for the touch screen "Report_Switch" signal. Goodix defines a 1ms (minimum) delay after stop off. In addition, no longer drive this GPIO high by default as it is now controlled by the kernel through ACPI. BUG=b:153705232 TEST=touch screen still functional on volteer; confirmed timings with scope (VDD, RESET, REPORT_SWITCH) Change-Id: I3ead9cf79812d08c4917be4585ed273050465a9b Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-17mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDurV Sowmya
This patch updates the SLP_Sx assertion width and power cycle duration for the dedede platforms. Power cycle duration: With default value, S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0 With value set to 1, S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0 BUG=b:159104150 TEST=Verified that the power cycle duration is ~1.2s with global reset on waddledoo. Change-Id: I7079cbd564288b5d5b69e07661434439365063d3 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-08-15mb: remove unnecessary FADT flag devicetree entries for PicassoFelix Held
Those flags already get unconditionally set in soc/amd/picasso/acpi.c. Change-Id: I978c7d67480499d92c193d5bb87bc876211187db Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-08-14mb/google/volteer: Only enable TBT root ports if USB4 is supportedBrandon Breitenstein
TBT ports should be disabled if the DB is a USB3 DB. It is assumed if the DB doesn't support USB4 the platform as a whole should only be USB3 capable and TBT functionality on both ports should not be enabled. BUG=NONE BRANCH=NONE TEST=Built coreboot and verified that TBT was disabled on platform with USB3 DB and enabled on platform with USB4/TBT DB Change-Id: I594f2e9483aaf896de2b6aea9a3460bd3826c58c Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-14mb/google/dedede: Add a board specific resetKarthikeyan Ramasubramanian
When CSE Lite jumps from RO to RW, global reset is initiated. When AP is reset as part of global reset, TPM initialization fails. This is because AP reset is not detected by TPM hosting an older firmware version. Request Embedded Controller (EC) to perform AP reset so that TPM can detect that event. BUG=b:162290856, b:162386991 TEST=Ensure that the device boots to OS with the board-specific reset sequence when CSE Lite jumps from RO to RW with an older and newer Cr50 firmware. Cq-Depend: chromium:2337430 Change-Id: Ib1f7271130e0b4b68c7f0917ecc4eadba1486206 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-08-14mb/google/octopus/variants/casta: Disable xHCI compliance modeSeunghwan Kim
Disable xHCI compliance mode to prevent SS hub detection issue. BRANCH=firmware-octopus-11297.B BUG=none TEST=built Change-Id: I7a9bbc92565e752a8f8f4689519c100594596701 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44438 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>