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2021-12-09mb/google/guybrush/var/nipperkin: Configure Smart Card in normal modeKarthikeyan Ramasubramanian
As per the schematics, smart card is expected to operate in normal mode by default. So configure the SOC_SC_PWRSV gpio accordingly. BUG=b:202992077 TEST=Build and boot to OS in Nipperkin board version 2. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I8e12600ad45734b144a30c868f0e4f323aa056f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-09mb/google/guybrush/var/nipperkin: Override SPI fast speedKarthikeyan Ramasubramanian
After assessing the signal integrity, 100 MHz SPI fast speed can be enabled for SPI ROM. BUG=None TEST=Build and boot to OS in Nipperkin board version 2. Perform 250 iterations of warm and cold reset each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Id973acb939b69e0beda26252e57a278892f2f57d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-09mb/google/brya4es: sync change from brya0 (CB:58374)YH Lin
CB:58374 (for mb/google/brya0) was merged before brya4es is available (CB:59728). And since brya4es is forked from brya0, brya0's change need to be brought into brya4es as well. BUG=b:203014972 TEST=build Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: I97489343b8f7a5b9457cd6f4a61cc37cd10ab450 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09soc/intel/tigerlake: Hook up DPTF device to devicetreeFelix Singer
Hook up `Device4Enable` FSP setting to devicetree state and drop its redundant devicetree setting `Device4Enable`. The following mainboards enable the DPTF device in the devicetree despite `Device4Enable` is not being set. * google/deltaur Thus, set it to off to keep the current state unchanged. Change-Id: Ic7636fc4f63d4beab92e742a6882ac55af2565bc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09soc/intel/tigerlake: Drop unused SataEnable settingFelix Singer
`SataEnable` is set by some boards, but it doesn't have any effect since its related FSP option is hooked up to the devicetree state. Thus, drop it. Change-Id: Id645bfcade7ca1d495fb8df538113b3d10392a82 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-09soc/intel/tigerlake: Hook up SMBus device to devicetreeFelix Singer
Hook up `SmbusEnable` FSP setting to devicetree state and drop its redundant devicetree setting `SmbusEnable`. The following mainboards enable the SMBus device in the devicetree despite `SmbusEnable` is not being set. * google/deltaur * starlabs/laptop Thus, set it to off to keep the current state unchanged. Change-Id: I0789af20beb147fc1a6a7d046cdcea15cb44ce4c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09mb/google/brya/var/brask: Configure the ISOLATE pin of LANAlan Huang
1. Copy the default configuration from Puff. 2. Update the 'stop_gpio' to GPP_H22. BUG=b:193750191 BRANCH=None TEST=Update kernel for 8125 outbox driver and test with command suspend_stress_test. Change-Id: I2e82dbc1e6c68cbd84b603adc7fdc3ee1d4d3392 Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09mb/google/brya/var/redrix4es: sync change from redrixYH Lin
The original change was for mb/google/redrix (commit 0167f5adbb), "The ChromeOS kernel platform driver is adding support for a ChromeOS privacy screen device, and in order to locate that device, the driver uses the GOOG0010 reserved HID for this" But it was merged before redrix4es is available. As redrix4es is forked from redrix, relevant change in redrix need to be brought into redrix4es as well. BUG=b:206850071 TEST=build Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: I5ac90c249273bf4e75cccb5889844a7f196f56fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/59987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09mb/google/brya: keep the same TPM I2C for 4ES variantsYH Lin
Since 4ES variants were forked from their own original variants, use the same TPM I2C as well. BRANCH=none BUG=b:201767461 TEST=emerge-brya coreboot and check the artifacts Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: Iddd6d8c22a181aba596b836f20392f76539b8549 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09soc/amd/stoneyridge: use common fch_spi_early_initFelix Held
All SPI interface setup related functionality that Stoneyridge implemented in its southbridge code is already present in the common AMD SoC code, so use that code instead. The common fch_spi_early_init function requires the SPI controller's base address to be set, so call lpc_set_spibase(SPI_BASE_ADDRESS) right before it. fch_spi_early_init then calls lpc_enable_spi_rom and lpc_enable_spi_prefetch which can be removed from the board code now. Next it calls fch_spi_configure_4dw_burst which does the same as the now removed sb_disable_4dw_burst function when SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST is set to n which is the default. This option can also only be set to y for SoCs that aren't Stoneyridge. Finally fch_spi_early_init calls fch_spi_config_modes which configures the SPI mode and speed settings according to the Kconfig settings and the settings in the amdfw part. On Kahlee this was done by calls to sb_read_mode and sb_set_spi100 before. The previous patch added the remaining Kconfig settings, so the resulting register values don't change in the non-EM100 case. In the EM100 case the TPM speed is changed from 64 to 16 MHz. TEST=Both the non-EM100 mode with a real SPI flash and the EM100 mode with a first-generation EM100 results in Google/Barla reaching the payload and the show_spi_speeds_and_modes call in bootblock prints the expected settings: relevant bootblock console output in non-EM100 case: SPI normal read speed: 33.33 MHz SPI fast read speed: 66.66 Mhz SPI alt read speed: 66.66 Mhz SPI TPM read speed: 66.66 Mhz SPI100: Enabled SPI Read Mode: Dual IO (1-2-2) relevant bootblock console output in EM100 case: SPI normal read speed: 16.66 MHz SPI fast read speed: 16.66 MHz SPI alt read speed: 16.66 MHz SPI TPM read speed: 16.66 MHz SPI100: Enabled SPI Read Mode: Normal Read (up to 33M) Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8f37a3b040808d6a5a8e07d39b6d4a1e1981355c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-09mb/google/kahlee/Kconfig: add remaining SPI speed settingsFelix Held
Before this patch only the SPI settings that will also end up in the amdfw part of the firmware were specified in the board's Kconfig. This patch adds the settings from Kahlee's bootblock.c to the Kconfig file which will be needed in subsequent patches. Also add a comment about the EM100 case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie42feb9b41f435c329bf1c78471e65ef5a3fb783 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-09mb/google/corsola: Pass reset gpio parameter to BL31Rex-BC Chen
To support gpio reset SoC, we need to pass the reset gpio parameter to BL31. TEST=build pass BUG=b:202871018 Cq-Depend: chromium:3188686 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I48d8d004ea92e950d0040a11133c57c121b86af3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-09mb/google/corsola: correct NOR flash configuration in GPIO setRex-BC Chen
The reference design has changed to use GPIO SET1 for NOR flash. There are no devices already built using SET0 so we can safely change the implementation without conditional configs. Reference document: kingler_mt8186_mt6366_lpddr4x_e.pdf, page 11. crab_proto 0_2021112.pdf, page 11. BUG=b:202871018 TEST=flash verify pass on kingler on bootblock stage Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I031686ccddcf789f3fa966d113ee48949e454b8f Reviewed-on: https://review.coreboot.org/c/coreboot/+/59945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-09mb/google/corsola: get SKU IDRex-BC Chen
Retrieve the SKU ID for Corsola via CBI interface. If that failed (or no data found), fallback to ADC channels for SKU ID. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I2888190d498df28b5ae13cf92cc41d088e8f8ee7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-08mb/google/dedede/var/magolor: Add fw_config probe for multi codec andTyler Wang
amplifier Compatible headphone codec "ALC5682I-VS" and speaker amplifier "ALC1015Q-VB" BUG=b:208912135 TEST=ALC5682I-VD and ALC1015Q-VB can work normally Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Id661280061ede3fbb63c962dee8fb18a2053ad66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-08mb/google/guybrush: Combine mem_parts_used.txtRob Barnes
Combine guybrush mem_parts_used.txt across guybrush variants. Guybrush reference memory parts is used as the base, then Nipperkin memory parts were appended, followed by DeWatt memory parts. Duplicates were removed. The memory id mapping was not affected on guybrush reference and Nipperkin. DeWatt memory id mapping was affected, DeWatt boards will need to be adjusted. This works around a limitation in APCB, which currently only supports one set of memory SPDs. BUG=b:209486790, b:204151079 BRANCH=None TEST=Boot guybrush and nipperkin Change-Id: Ie17025e092f2b9397afea33fce285e80ef5dc995 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-08mb/google/brya/var/primus: Fix PLD group orderScott Chao
In ec/google/chromeec: Add PLD to EC conn in ACPI table(667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. It causes the DUT to not boot into the OS. So fix the USB3/USB2 Type-C Port C2 PLD group order from 3 to 2 to solve this issue. BUG=b:209568644 BRANCH=none TEST=build coreboot and system boot into OS. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: If5ce6ca061d9d56ba0bbb1f157b2ba278d3fa9c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59953 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-08mb/google/corsola: Configure TPMRex-BC Chen
Initialize SPI bus 2 for TPM control. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I8ede68d6eb594890195e8464151c1c0f88aeee43 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-08mb/google/corsola: implement get_ec_is_trustedRex-BC Chen
Set VB2_CONTEXT_EC_TRUSTED in verstage_main. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: If2837f5db52f91f5418d222d4dcd1af2aebcc105 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-08mb/google/corsola: Enable Chrome ECRex-BC Chen
Initialize SPI bus 1 for Chrome EC control. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I7d032d595f7ca1dbed3de4dfe308ff4be64333cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/59941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-08mb/google/zork,soc/amd/psp_verstage: Add verstage_mb_{tpm/espi}_initRaul E Rangel
These functions can't be weak, because they actually need to configure the GPIOs for eSPI and the TPM. With this change zork boots again. I also noticed that zork doesn't use the early table in bootblock. This means that zork will only boot if psp_verstage is enabled. BUG=b:209465425 TEST=boot zork to ramstage Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I384fd578efe7da0a3d74829cccf38c3ed524f130 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-07mb/google/brya: add list of gpios to lockNick Vaccaro
Add a list of gpios to lock for brya. This currently includes GPIOs connected to the FPMCU. BUG=b:201430600 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that brya0 boots successfully to kernel. Change-Id: Idea42a58575c280be0770d38f934acdf5508c45d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-06mb/google/brya/var/gimble: Configure Acoustic noise mitigationMark Hsieh
- Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to 16 BUG=b:206704930 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I2be3d30403284b98276c837adefd91aa62c971e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59535 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-06mb/google/brya/var/redrix: Swap TPM I2C with touchscreen I2CWisley Chen
According to the latest schematic, exchange I2C port for TPM/touchscreen. TPM: I2C3 -> I2C1 Touchscreen: I2C1 -> I2C3 BUG=b:205648040 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I3a8339c23522019da884944246427512170510b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-06mb/var/gimble: Set PsysPmax to 143 WChia-Ling Hou
This patch adds the setting of PsysPmax to 143 W according to gimble board design. BUG=b:206990759 TEST=emerge-brya coreboot chromeos-bootimage & ensure the value is passed to FSP by enabling FSP log & Boot into the OS Change-Id: Id6a203f05ecfcc1020a422850d35fa3fa64e01d0 Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ryan Lin <ryan.lin@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-06mb/google/brya/var/felwinter: Correct garage wake eventEric Lai
Eject event is high. Set wake event to active high. The polarity of the SCI and the wakeup_event_action for the pen ejection feature were both backwards, and was causing the system to fail to enter sleep states because the event was always asserted. BUG=b:208937710 TEST=only release switch can wake system. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I568e9175c7a66599f7a525c32e4def7a79b55a0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/59861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-05mb/google/hatch: Remove stryke mainboardTim Wawrzynczak
The stryke project/mainboard never ended up being built and was cancelled early on, therefore remove it from the tree. Change-Id: I4d91fbd4ba0abe0cf599e8e75f04398ef9ff5222 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-12-03mb/google/brya/var/felwinter: Add WiFi SAR table for felwinterIan Feng
Add WiFi SAR table for felwinter. BUG=b:206901900 TEST=emerge-brya chromeos-config chromeos-config-bsp-private coreboot-private-files-baseboard-brya coreboot chromeos-bootimage and checked SAR table can load by WiFi driver. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I0de710f4447302ee545a67cbd79373bdd2077637 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-12-03mb/google/brya: Update camera NVM parametersBernardo Perez Priego
Change HID name from INT3499 to PRP0001 along with size and address width. Size decreased from 10K to 2K, address width decreased from 14 to 8. BUG=b:203014972 Test= Boot board and issue commands: `cat /sys/bus/i2c/devices/i2c-PRP0001:02/eeprom > ./brya_imx208_eeprom.bin` `hexdump -C brya_imx208_eeprom.bin > brya_imx208_eeprom_dump.log` You should see the result in brya_imx208_eeprom_dump.log to be same as module nvm file by vendor provided or meet the Intel nvm calibration format. (e.g. first 4 bytes be 0x01, 0x03, 0x01, 0x00) Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Ib2366ba4c8bb70d8cc82e64ca585b118a96260c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03mb/google/dedede/var/drawcia: Generate new SPD ID for new memory partsRobert Chen
Add new memory parts in memory_parts_used.txt and generate SPD id for these parts: Samsung K4U6E3S4AA-MGCL BUG=b:204014463 TEST=run part_id_gen to generate SPD id Change-Id: Icb0f211508450b16b2e5d214ae6adc9852718a59 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-03mb/google/guybrush: Configure EN_SPKR GPIO in PSP verstageKarthikeyan Ramasubramanian
EN_SPKR GPIO is used as a multiplexer select signal between RAM_ID straps and Developer Mode Beep signals. During boot up it is LOW and selects RAM_ID straps. When the system enters OS, it is driven HIGH and selects DEV BEEP signals. Since in some boards, the GPIO chosen is in S5 domain it does not reset until the system enters mechanical off (G3) state. On scenarios where the power button is pressed when the system is in S5, incorrect RAM_ID strap is being read because the EN_SPKR is still selecting DEV BEEP signal. This causes boot up failures. Fix this by configuring the EN_SPKR GPIO (in S5 domain) explicitly in PSP verstage. BUG=b:204450368 TEST=Build and boot to OS in Guybrush. Perform suspend-resume cycle followed by a S5 -> S0 boot cycle for 2 iterations successfully. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I9a52a167da9c7040731da5d355ec345fd9b13762 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59813 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-03mb/google/brya/var/brask: Enable LAN driver to program MACAlan Huang
Turn on the LAN device in devicetree and add Kconfig item RT8168_GET_MAC_FROM_VPD to support programming MAC address. BUG=b:193750191 BRANCH=None TEST=Use 'vpd -s ethernet_mac0=...' to write MAC to VPD. Use 'ifconfig' to check if the MAC written successfully. Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Change-Id: Ibb95b02fd6d61621ef46db4d63b48456a0a72732 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03mb/google/brya/var/brask: Set vGPIO reset typeKane Chen
Due to the vGPIO is not reset when we power on through S5, we would met MCA when PCIE send L1 request without following Ack BUG=b:207625007 TEST=S0->S3->S5->power key->S3->S0, see if boot up normal Change-Id: I20cdd1650d1ca774065a6c051006dfd0b7a3fd79 Signed-off-by: Curtis Chen <curtis.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03mb/google/dedede: Create beadrix variantTeddy Shih
Create the beadrix variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:204882915 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_BEADRIX Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: Ie08cbc19967eca8ba31ea3203e71c4e1fef044d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-03mb/google/brya/variants/primus: Swap TPM I2C with touchscreen I2CMalik_Hsu
In next build phase, primus will exchange i2c port for touchscreen and cr50. BUG=b:207834727 TEST=build pass Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: Ief1b156b866a9aaa2919f0e209b6439c7019e939 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03mb/google/brya/var/taeko: Set vGPIO reset typeKevin Chang
Due to the vGPIO is not reset when we power on through S5, we would met MCA when PCIE send L1 request without following Ack BUG=b:207070967 TEST=S0->S3->S5->power key->S3->S0, see if boot up normal Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: Ice522260f288b165ae66dddc3e1979e806b53f9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/59749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03mb/google/brya: Create taniks variantJoey Peng
Create the taniks variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:207402720 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_TANIKS Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I797051f93019ccf72f1007d9c0b98cfb071717b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-02mb/google/brya/var/brask: Set PL and PsysPLAlan Huang
1. Set the PL1, PL2 and PL4 according to issue b:193864533 comment#55 and Intel's doc #626774. 2. Set PsysPL2 and PsysPmax according to the conclusion in issue b:193864533 comment#23 and comment#29. BUG=b:193864533 BRANCH=none TEST=Compare the measured power from adapter with the value of 'psys' from the command 'dump_intel_rapl_consumption'. Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Change-Id: I9261902b8c892d0b866f326b24988039c1d30b56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-02mb/google/brya/var/baseboard/brask: Add power limits functionsAlan Huang
Copy function variant_update_power_limits from brya to set power limits. Add function variant_update_psys_power_limits and copy the algorithm from puff. Add structure system_power_limits and psys_config to define and configure the psys power limits. BUG=b:193864533 BRANCH=none TEST=Build pass Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Change-Id: I183017068e9c78acb9fa7073c53593d304ba9248 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-02mb/google/brya/var/gimble: Swap TPM I2C with touchscreen I2CMark Hsieh
DVT schematic will exchange TPM_I2C3 to TPM_I2C1, that may need swap TPM I2C with touchscreen I2C to avoid TPM I2C fall on muxed ISH I2C, need change I2C map, sch amd GPIO map. b/196293623 BUG=b:207613972 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I26d059a7ea5a3fdf00de260214c00d3bba9aa7f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59580 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-02mb/google/brya/var/felwinter: Swap TPM and touchscreen I2C busEric Lai
Follow the latest HW schematic change. BUG=b:208556921 TEST=build pass Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ic05843487ea540b8cd9a50d5f73803905fd80d49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-02mb/google/brya: Fix S0i3 regressionMeera Ravindranath
Keeping the PM timer enabled will disqualify an ADL system from entering S0i3, and will also cause an increase in power during suspend states. The PM timer is not required for brya boards, therefore disabling it. Fixes: 0e905801 (soc/intel: transition full control over PM Timer from FSP to coreboot) BUG=b:206922066 TEST=Boot gimble to OS and verify S0i3 counter incrementing after exiting S0ix suspend states. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I8005dacd732c033980ccc479375ff5b06df8dac1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59790 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-02soc/intel/alderlake: Add Kconfigs for all PCH typesAngel Pons
The Alder Lake code currently supports the PCH-M and PCH-P types, which have some differences (so far, only the amount of PCIe I/O). Mainboards can use the `SOC_INTEL_ALDERLAKE_PCH_M` Kconfig option to specify which PCH type they use: select the option to choose PCH-M, do not select the option to choose PCH-P. While this works, it can be confusing once more PCH types are added. Introduce the `SOC_INTEL_ALDERLAKE_PCH_P` Kconfig option so that boards have to explicitly choose a PCH type. Also, use this option to restrict the PCH-P defaults for PCH-dependent settings to avoid unintended reuse of the PCH-P defaults when adding a new PCH type. To make sure only one PCH type is selected, add some preprocessor in `bootblock.h` to provoke a build-time error if this requirement is not met. Kconfig doesn't seem to have a mechanism to describe sets of mutually-exclusive bool options that allows said options to be selected (a `choice` block doesn't allow its elements to be selected). Finally, adapt the ADL boards accordingly. Change-Id: I7deca820e08ce2b5a220f3c97a511a4f3464a976 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-12-01guybrush: add RO_GSCVD area to FMAPVadim Bendebury
This area is used for storing AP RO verification information. BRANCH=none BUG=b:141191727 TEST=built a guybrush firmware image and verified that the RO_GSCVD area was indeed added: $ dump_fmap /build/guybrush/firmware/image-guybrush.bin | \ grep -B3 RO_GSCVD area: 25 area_offset: 0x00808000 area_size: 0x00002000 (8192) area_name: RO_GSCVD $ - verified that guybrush device boots fine with the new image. Change-Id: Ifa24d5a6271a8bcbf737d4580ec85b9cfdd9af01 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57864 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-01mb/google/brya/redrix: Add _HID for privacy screen deviceTim Wawrzynczak
The ChromeOS kernel platform driver is adding support for a ChromeOS privacy screen device, and in order to locate that device, the driver uses the GOOG0010 reserved HID for this. Patch for 5.10 kernel can be found at: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3289984 BUG=b:206850071 TEST=dump SSDT, see _HID instead of _ADR Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: If988ca94b6c70d08a7b07cc9f6bbb077fac84e5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59731 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-01herobrine: Assert gpio for USB_HUB_LDO_ENSandeep Maheswaram
Some herobrine variants have USB hub powered by discrete LDO that is controlled by USB_HUB_LDO_EN gpio. Assert the GPIO on boot. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board. Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Change-Id: Ia94e046f9eb0d3ce593f3445e0203a7391c14de2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-30mb/google/herobrine: Initialize USB by calling SOC methodRavi Kumar Bokka
Initialize by calling `setup_usb_host0()` from SOC code BUG=b:182963902 TEST=Validated USB enumeration on qcom sc7280 development board Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Change-Id: Ic378352a97e4f3ed89089f1f7545f8ebb172b1f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-11-30mb/google/brya/var/kano: Enable USB2 port 9 for BlueToothDavid Wu
BlueTooth disappeared after disabled USB2 port 9, so we need to re-enable it. BUG=none TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I7971509d7428562c80e781339ead059a189cea13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-30mb/google/dedede/var/beetley: Enable GEO_SAR_ENABLE for beetleywizard
BUG=b:207307897 BRANCH=dedede TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Change-Id: Ib1682cdafe1b6ed7cc0cf23624f83d2e5bbfb92e Signed-off-by: Wizard Shen <shenhu5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com>
2021-11-30brya: add various ES variantsYH Lin
Fork multiple "4ES" variants off some brya devices to properly support ES SoC. BRANCH=none BUG=b:201767461 TEST=emerge-brya coreboot and check the artifacts Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: Ic9516fec591429238bde1478eca2522d8ed10127 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-29soc/qualcomm/common/usb: Add support for common USB driverSandeep Maheswaram
Add common USB driver for qualcomm soc sc7180 and sc7280. This includes dwc3 controller, qmp ss phy, qusb hs phy and snsp hs phy. BUG=b:182963902 TEST=Validated USB enumeration on qcom sc7180 and sc7280 development board Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Change-Id: I1013ded22855286220cfa747cb25418070fe85a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-26mb/google/corsola: Add an option for SD card initializationRex-BC Chen
There is no support for SD card on Corsola reference board, so we add a configuration to disable SD card initialization to prevent setting GPIOs in a mistaken way. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ia05fd046335c6ce6f9198ddbb7cbda2afc6ae3cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/59571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-26mb/google/corsola: Get RAM code from ADCRex-BC Chen
On Chromebooks the RAM code is implemented by the resistor straps that we can read and decode from ADC. For Corsola the RAM code can be read from ADC channel 2 and 3. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I485c32dec7b425b604b4063d742a0e37d3961513 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-26mb/google/corsola: Raise little CPU frequencyRex-BC Chen
Raise little CPU to 2GHz at romstage. TEST=check little core cpu frequency is 2GHz BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: If4c983d15beb2b588230f3db7416cb767b29978d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-26mb/google/corsola: Add VPROC12/VSRAM_PROC12 to regulator interfaceRex-BC Chen
Add VPROC12/VSRAM_PROC12 to adjust power for raising little CPU frequency. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I59b4627220022a51a116716036a8ba0048039508 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-26mb/google/corsola: configure GPIOsRex-BC Chen
Configure Chromebook specific GPIOs, including EC_AP_INT, EC_IN_RW, GSC_AP_INT, EN_SPK, GPIO_AP, and GPIO_RESET. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I76bde75788889111c0a051eed731dadc9898c0e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-26mb/google/brya/var/kano: swap TPM i2c with TS i2c for the next build phaseDavid Wu
Kano EVT will exchange i2c port for touchscreen and cr50. BUG=b:195853169 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I500f0721689ca66b65b8fb1deb79bef2bd988465 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-25mb/google/brya/variants/primus: update gpios for power consumptionMalik_Hsu
In different sku, some unused GPIO pins are processed by NC for power consumption. BUG=b:196790249 TEST=emerge-brya coreboot chromeos-bootimage and check power Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I753e41dec1825299e6cd437b5f67e2d957bc6148 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-25src/mb/brya: Enable crashlog on brya0Kane Chen
Enabling crashlog helps partners to debug hang issues efficiently. BUG=b:195327879 TEST=Found BERT table is created and the tcss function is ok in depthcharge. Warm/cold/suspend_stress test pass 50 cycles on gimble Change-Id: Ib4bbe5d7cece0c6c5fc170460d55ac820054abb9 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-25mb/google/brya/variants/primus: add fw config probe for speaker ampMalik_Hsu
Added fw config probe for MX98360A. BUG=b:205883511 TEST=emerge-brya coreboot chromeos-bootimage and check audio function Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I2452b752ce58a5d0f1008cf187fb79ace6c4285f Reviewed-on: https://review.coreboot.org/c/coreboot/+/59613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-25mb/google/brya/var/felwinter: Add DPTF parameters for FelwinterJohn Su
The DPTF parameters were verified by the thermal team. BUG=b:207463762 BRANCH=brya TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I634d6d98c28e75ad41488921df6b8e836e253ff1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-25mb/google/brya/var/primus: Update thermal table for primusAriel_Fang
- Add 4 TEMP_SENSORs - Configure granularity of power limits BUG=b:200836803 TEST=USE="project_primus emerge-brya coreboot" and verify it builds without error. Signed-off-by: Ariel_Fang <ariel_fang@wistron.corp-partner.google.com> Change-Id: Id4d8dbe678b7f0870aeffa0a0118e65de9d5c22d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-11-25mb/google/brya/var/kano: Update thermal tableDavid Wu
Update thermal setting from thermal team. BUG=b:205648035 TEST=build and verified by thermal team. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: If5082462b79c88ecf510f7a552381c792604366e Reviewed-on: https://review.coreboot.org/c/coreboot/+/59572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-11-25mb/google/brya/var/kano: set power limits for thermalDavid Wu
Set power limits for kano based on CPU SKUs. BUG=b:205648035 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I25cf9be68f8981d8307b4c15ab9f65b59058fb19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-24mb/google/brya/var/gimble: Enable DRIVERS_GENESYSLOGIC_GL9750Mark Hsieh
Enable DRIVERS_GENESYSLOGIC_GL9750 support for Gimble. BUG=b:206014046 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ifc490e6e081b6a8534656417603d2916c3edcb05 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59579 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-23mb/google/brya/var/redrix: Disable autonomous GPIO power managementWisley Chen
With cr50 fw 0.3.22 or older version, it needs to disable autonomous GPIO power management and then can update cr50 fw successfully. BUG=b:202246591 TEST=FW_NAME=redrix emerge-brya coreboot chromeos-bootimage. Change-Id: Idc01ebb4d3ef990f24f18bef5424b7d6ba683d49 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-23mb/google/trogdor: change pin define for quackingstickSheng-Liang Pan
change TP_EN pin to GPIO_67 for quackingstick BUG=b:206862167 BRANCH=trogdor TEST=make Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I7cc1083111f46cd3489cbbb9e579c34dc972b0b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Bob Moragues <moragues@google.com>
2021-11-22mainboard/google/brya: Enable dev screen in bios-stage for BraskAdam Liu
Add Kconfig item ENABLE_TCSS_DISPLAY_DETECTION. TEST=Build with the VBT provided in issue b:199490251. Check the dev screen in bios-stage. BUG=b:199490251, b:206014054 Signed-off-by: Adam Liu <adam.liu@quanta.corp-partner.google.com> Change-Id: I5f34be030a6d819a0e93a2d479c4ff41bb14cfe2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-22mb/google/brya: Move cr50 configuration to variantDavid Wu
Brya schematic will swap TPM I2C with touchscreen I2C, so move into variant level. BUG=b:195853169 TEST=build pass. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ie5276527da135ec15045a81985ae006722871b0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-22mb/google/brya/variants/primus: add fw_config_probe for ALC5682I-VSMalik_Hsu
Added fw_config_probe method to distinguish different audio codecs to facilitate the use of different topology files by the OS. BUG=b:205883511 TEST=emerge-brya coreboot chromeos-bootimage and check audio function Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I0d5b95e89154b2cb6b371f24cc1b151c23ff642f Reviewed-on: https://review.coreboot.org/c/coreboot/+/59367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-22mb/google/brya/var/felwinter: Add ALC5682I-VS codec supportEric Lai
ALC5682I-VS will use in next build. BUG=b:194367025 TEST=none. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I34d736fe1c39860443dac07435a21ccd0ee2f21c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-22mb/google/dedede/var/bugzzy: Configure Acoustic noise mitigation UPDsSeunghwan Kim
Enable Acoustic noise mitigation for bugzzy and set slew rate to 1/8 which is calibrated value for the board. BUG=b:207046230 BRANCH=dedede TEST=build firmware to UPD and Acoustic noise test Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: Id249a143efb9bce70f48fb466fed42e766a10937 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-19mb/google/brya: Move EC_HOST_EVENT_USB_MUX wake event to S0ix onlyJoey Peng
If a USB_MUX_EVENT happens while the AP is in S3 during powerdown transtion (S0->S3->S5), this will cause the device to boot again after it has finished sequencing down to S5. Since S3 is not POR for ChromeOS devices anymore, change this event to wake from S3 and S0ix to just S0ix. BUG=b:206867635 TEST=emerge-brya coreboot Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Icdab40b6a845a34246d7da336f43e970f7908301 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-19mb/google/volteer/var/chronicler: set DdrMemoryDown enableSheng-Liang Pan
as doc #632048, there is a fix in MRC for this sighting but DdrMemoryDown need to be set to 1. BUG=b:192478111 BRANCH=volteer TEST=FW_NAME=chronicler emerge-volteer coreboot chromeos-bootimage Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: If7ead2d0bb2955a4f1b81d012ee2e2518b2a82e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59373 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-19mb/google/brya/var/redrix: Configure _DSC for CAM devices to ↵Varshit B Pandya
ACPI_DEVICE_SLEEP_D3_COLD Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips initial probe during kernel boot and prevent privacy LED blink. BUG=b:199823938 TEST=Build and boot redrix to OS. Verify entries in SSDT and monitor LED during boot. Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I88ea1b87698c63e1bd69367ee857fba3f25c84ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/59260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-18mb/google/guybrush: Add variant_tpm_gpio_tableRob Barnes
Add separate gpio table for TPM i2c and interrupt. Remove TPM gpios from early_gpio_table. This allows for initializing TPM gpios separately from other gpios. BUG=b:200578885 BRANCH=None TEST=Build and boot guybrush Change-Id: I51d087087b166ec3bb3762bc1150b34db5b22f2f Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59083 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-18mb/google/brya/var/felwinter: Correct USB3 TCSS settingEric Lai
Based on Intel Kit#615686, USB3 only needs to disable TBT and DMA per port. And if uses USB3 directly you need to set TcssAuxOri accordingly. BUG=b:206716691,b:205235144 TEST=USB function work as expected at USB3 only sku. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I303d042d6c80194ff48130fe4e9c04b49ca13ee8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-18mb/google/brya/var/gimble: Include 2 new SPDsMark Hsieh
Add SPD support to gimble for LPDDR4 memory part MT53E1G32D2NP-046 WT:B and MT53E512M32D1NP-046 WT:B. BUG=b:191574298 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Id3fc35605675b953bf993a29f35140f7721eedab Reviewed-on: https://review.coreboot.org/c/coreboot/+/59299 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-18mb/google/brya/var/redrix: De-assert SSD PERST# in romstageWisley Chen
After CB:57539 applied, it can support romstage GPIO table override. We can move SSD PERST# de-assertion to romstage. The reason for this is to give enough time after PERST# deassertion so that the SSD has enough time to initialize before the FSP scans the RPs for downstream devices. BUG=b:199714453 TEST=build Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I242cb1517f564d9d135d523b1e7f95ac34d601f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-18mb/google/brya/var/redrix: Correct WWAN power sequenceWisley Chen
Correct the WWAN power sequence to meet spec BUG=b:206079177 TEST=build Change-Id: Ibba1ecc04b563ae4eedd7596594f33812cbac150 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-18mb/google/brya/var/redrix: Configure Acoustic noise mitigationWisley Chen
Enable Acoustic noise mitigation for redrix and set slew rate to 1/8 BUG=b:204009588 TEST=build and verified by power team Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I0fc0bb68c4de6fca60ee290eb46a77200d748ca8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-18amdfwtool: Call the set_efs_table for StoneyridgeZheng Bao
Related to https://review.coreboot.org/c/coreboot/+/58555 commit-id: 35b7e0a2d82ac In 58555, we added the SOC ID for Stoneyridge in amdfwtool command line. But it raised building error because it then called "set_efs_table" without setting SPI mode. So we skipped calling that. But in set_efs_table, it has case for Stoneyridge. The boards also need to have this setting. So we remove the skipping and give the proper SPI mode in mainboard Kconfig. Change-Id: I24499ff6daf7878b12b6044496f53379116c598f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-17mb/google/brya/var/felwinter: Add MT53E1G32D2NP-046 WT:B SPDEric Lai
Add MT53E1G32D2NP-046 WT:B SPD. BUG=b:205669003 TEST=Boot up without issues. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If084a8af941b36a8f3f608271078e32b093d9108 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17mb/google/cyan: use shared touchpad/touchscreen interruptsMatt DeVillier
Windows (10/11) freaks out and generates an interrupt storm if two ACPI devices are enabled and share an interrupt, even when only one device is actually present. To mitigate this, mark Cyan's touchpad/touchscreen interrupts as SharedAndWake rather than ExclusiveAndWake. Test: build/boot Windows 10 on Relm, observe normal CPU usage in Task Manager for System Interrupts task when touchpad/touchscreen in use. Change-Id: I09bc878318f9fa6252f65a42ad46109418805fa0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17mb/google/trogdor: Adjust mipi panel backlight gpioZanxi Chen
According hareware design, mipi panel backlight relies on AP_BKLTEN(GPIO_12) and TP_EN(GPIO_85). Meanwhile, TP_EN(GPIO_85) needs pull up to enable PP3300_DISP_ON before AP_BKLTEN(GPIO_12) up. BUG=b:197709288,b:199081803,b:205166230 BRANCH=trogdor TEST=emerge-strongbad coreboot Change-Id: Ie9920e5366f6b1ea9e0da228bd211317516b390a Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-17mb/google/brya/var/taeko: Correct touchpad GPE settingsJoey Peng
Correct GPE settings so touchpad can wake up DUT. BUG=b:206526991 TEST=emerge-brya coreboot and builds without error Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I1978e9220ad7a275d351ad5eeff7036131926b24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17mb/google/brya/var/taeko: disabled autonomous GPIO power managementJoey Peng
Used H1 firmware where the last version number is 0.0.22, 0.3.22 or less to production that will need to disable autonomous GPIO power management and then can get H1 version by gsctool -a -f -M BUG=b:205315500 TEST=emerge-brya coreboot and test that DUT can boot to OS. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ib26797fa2d4d0b1a6eb28c5d79b9ac0a6054abd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17mb/google/brya/variants/primus: Correct SSD power sequenceCasper Chang
SSD sometimes can't be detected in in warm/cold boot stress. M.2 spec describes SSD_PERST# should be sequenced after power enable. BUG=b:199967106 TEST=SSD was always discovered in warm/cold boot stress. Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I74c21cd96cf1c4518c4ed7c0b3b39e915b6b1ff7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17mb/google/brya: Enable early EC syncBoris Mittelberg
Enable VBOOT_EARLY_EC_SYNC in corebot BUG=b:201356952 BRANCH=None TEST=Tested on Brya id 2 Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: I6e480d64a5d90d5bb9cf59ed60b7b53af9edf46a Reviewed-on: https://review.coreboot.org/c/coreboot/+/59274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17mb/google/hatch: Add VBTs for variantsMatt DeVillier
Add VBTs for all hatch variants currently supported by ChromeOS recovery images. For variants which use multiple VBTs and select at runtime, ensure these are added directly to CBFS. Change-Id: I3c62ce204e3272e778ba0a34f7a47a65d8125f53 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17mb/google/hatch: Alphabetize variants in Kconfig.nameMatt DeVillier
Change-Id: Ie29242e635bae1e2754bc1109754a64cb496af29 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17mb/google/brya: Move typeC AUX configuration to variantEric Lai
TypeC AUX configuration is variant specific. So move into variant level. BUG=b:205235144 TEST=No typeC port 0 AUX in felwinter. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I02bfea462cf4c6359fd8d5cca4368786ee03bc8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17mb/google/guybrush: Update SPKR GPIO configuration for guybrush/nipperkinKevin Chiu
For Guybrush Board Version 2, Nipperking Board Version 1, update SPKR GPIO to match H/W schematic: SPKR: GPIO31 For Nipperkin Board Version 2, update SPKR GPIO to match H/W schematic: SPKR: GPIO70 BUG=b:202992077 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Change-Id: I3d82292b116f53d85d9518364ffd2169bd915a7e Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59051 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-17mb/google/octopus: Add missing VBTs for variantsMatt DeVillier
Add VBTs for all octopus variants currently supported by ChromeOS recovery images. For variants which use multiple VBTs and select at runtime, ensure these are added directly to CBFS. Change-Id: I4b5c4268f9255d658f9762d94488db66e0677830 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17mb/google/octopus: Alphabetize variants in Kconfig.nameMatt DeVillier
Change-Id: I2e57c4f1baa8a42bde2642e7f76ddead7bfd6a58 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17mb/google/slippy/peppy: use shared touchpad interruptsMatt DeVillier
Windows (10/11) freaks out and generates an interrupt storm if two ACPI devices are enabled and share an interrupt, even when only one device is actually present. To mitigate this, mark Peppy's interrupts as Shared rather than the default of Exclusive. Test: build/boot Windows 10 on Peppy, observe normal CPU usage in Task Manager for System Interrupts task when touchpad in use. Change-Id: Ida78ddec3105cef6581cdde78da2e2c97d983a0a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17soc/mediatek/mt8186: Add RTC and clkbuf driversYuchen Huang
Add support for RTC and clkbuf. TEST=boot to kernel and check log ok BUG=b:202871018 Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com> Change-Id: Ia02a74f685feb2466c113a77cbfa3a7d8fedb595 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-17mb/google/corsola: Initialize SPMRex-BC Chen
Initialize SPM (System Power Management) in RAM stage. This adds 55ms to the boot time. TEST=program counter of SPM is correct value(0x250) after booting up BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I822417f7a679107760b202dd43fb79d1934940bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/59342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-17soc/mediatek: move MSDC drivers to soc folderRex-BC Chen
Setting of MSDC is defined by soc, so we move them to soc folder. TEST=emerge-cherry coreboot; emerge-asurada coreboot Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I84ad8a4cde120c97024870ebf750d44b36c2284d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-17mb/google/brya/variants/primus: enable ALC5682I-VSMalik_Hsu
In next phase build, the audio codec will change to ALC5682I-VS BUG=b:205883511 TEST=emerge-brya coreboot chromeos-bootimage and check audio function Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I5906ef9bb88da7fe450a986bf7dd1ee701227f95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-22 13:36:04 +0000