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From spec, [31:28] "HS DC Voltage Level Adjustment" is "TXVREFTUNE0".
correct rx_vref_tune -> tx_vref_tune
BUG=None
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I27003a952d8f8bdd8fe52af8a37010e23ee9cdfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Update Woomax to improve the performance.
BUG=b:168073070
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I2703d15f1fbe715ab1c684274d9e4e0bb55ef23b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add a function that initializes GPIOs based on the sleep type that
the system is coming back from. This allows initialization of the
fingerprint GPIOs which need to be handled differently between wake
from S3 and boot from S5.
On initial boot, the state of the FP sensor could be either
enabled or disabled. Because of this, on boot, we power off
the sensor for >200ms, to reset its state, then power it back on.
In suspend/resume, the fingerprint sensor should remain powered
the entire time.
If fingerprint is disabled on the trembyle-based board, set the pins
to no-connect. Dalboz doesn't have fingerprint and the GPIOS are
configured differently due to the FT5 chip having fewer GPIOS than
FP5, so nothing needs to be initialized there.
There were also a couple of trivial comment clean ups regarding the
FPMCU GPIOS.
BUG=b:171837716
TEST=Boot & Check GPIO states.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I16a2e621145782e0a908bb3e49478586c09a0e0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: I75a92616f11054993ff5a5bfefce5c3f4638c07c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Use command below to change the variable globally.
sed -i "s/\<variable\>/variable_u/g" `grep variable -rl ./ \
--exclude-dir=build --exclude-dir=crossgcc`
BUG=b:171334623
TEST=Build
Change-Id: I056a76663e84ebc940343d64178c18cb20df01a3
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Since google_chromeec_cbi_get_board_version and google_chromeec_cbi_get_fw_config both call cbi_get_unit32 and return 0 as success, non-zero as failure. Let's add more readability for the false condition.
BUG=None
TEST=check with empty CBI value
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia49ac1ee35302f8f6afe8c0eb8e13afdf36c5b2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46566
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The disconnect voltage needs to be adjusted up because the HS DC voltage
level is 0xF.
BUG=b:170879690
TEST=Servo_v4 USB hub functions
BRANCH=zork
Change-Id: If8662015a45c57e457b4593e55af888084842f58
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This will reduce boot time by 7ms. Some of the initial designs
don't have a pull-up resistor on the CMD line. These designs still boot
at 400 kHz despite not having the pull-up.
BUG=b:158766134
TEST=WIP
BRANCH=zork
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I2fcbe35103020c3444902c077b4985f87f970671
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45936
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Modify I2C3 setting to follow I2C specification(lower than 400kHz).
Original setting:
.rise_time_ns = 125
.fall_time_ns = 37
Change to:
.rise_time_ns = 110
.fall_time_ns = 34
BUG=b:169207742
BRANCH=None
TEST=emerge-zork coreboot chromeos-bootimage
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I0f0b791c3e701ebf6b336a8cb259eeb74c46af5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Modify USB 2.0 PHY parameters for improve usb eye diagram.
1. USB 2.0 TypeC port0:
.com_pds_tune = 0x03,
.sq_rx_tune = 0x3,
.tx_fsls_tune = 0x3,
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0xf,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
2. USB 2.0 TypeC port3:
.com_pds_tune = 0x03,
.sq_rx_tune = 0x3,
.tx_fsls_tune = 0x3,
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0xf,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
BUG=b:169207729
BRANCH=zork
TEST=emerge-zork coreboot chromeos-bootimage
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I764238485a1a81eb0d4740ac58c80a43f965f550
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45641
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Woomax needs memory ID 0 to map to MT40A512M16TB-062E:J.
BUG=b:165611555
TEST=None
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Ibbcef6be382bd6649c93cfe92427f124dd137112
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45264
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Allow comments prefixed with '#' in mem_parts_used csv file.
BUG=None
TEST=Run gen_part_id with mem_parts_used file containing comments
Change-Id: Ia9e274d45aa06dea7a3a5f8cd1c8ee2b23398876
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Modify USI_RESET_L GPIO_140 in touchscreen power on/off sequence
to be active low.
BUG=b:160126287
BRANCH=Zork
TEST=emerge-zork coreboot
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I53dd872fdacb95cda43f297d2c3f9c6723b27bad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44858
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These parts have not been used in any woomax devices. Removing
so IDs can be assigned more efficiently.
Command to generate files:
go build gen_part_id.go
local variant=woomax
./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/${variant}/spd/ ../../../src/mainboard/google/zork/variants/${variant}/spd/mem_parts_used.txt
BUG=b:165611555
TEST=none
Change-Id: I651539c2df8e6d817582573d45b9e77156ece7d4
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Switch all zork boards to use generated generic SPDs from spd_tools.
HMAA1GS6CMR6N-VK is unused by Ezkinil, and all other boards, so it was
removed.
picasso/Makefile.inc was updated to populate the 2nd APCB channel based
on APCB_POPULATE_2ND_CHANNEL. This removes the need to suffix spd
entires with _x1/_x2.
Command to generate files:
$ find src/mainboard/google/zork/variants/ -maxdepth 1 -type d | grep -v '/$' | while read b; do
n=$(basename ${b});
if [ "${n}" = "baseboard" ]; then
continue
fi
go run util/spd_tools/ddr4/gen_part_id.go src/mainboard/google/zork/spd \
src/mainboard/google/zork/variants/${n}/spd \
src/mainboard/google/zork/variants/${n}/spd/mem_parts_used.txt
done
BUG=b:162939176
TEST=Boot ezkinil and dalboz check dmidecod -t17
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I0553858f83d3d1e90cf35bece108768f004a29a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44480
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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update telemetry value with the SDLE test result.
BUG=b:158964769
BRANCH=none
TEST=emerge-zork coreboot
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ic419ca5ca00e4e8602dbc12212a8a63ed3657e02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add board version switch GPIO table on gpio.c.
BUG=b:165887084
BRANCH=Zork
TEST=emerge-zork coreboot
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I661e16f7b4769e83450f41ff267c0d253441c4cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add GPIO_144 setting to fix touchscreen function not work.
1. Modify reset pin to stop gpio delay to 200ms.
2. Reset GPIO off delay set to 1ms.
3. Add GPIO_144 as stop GPIO.
4. Stop GPIO off delay set to 1ms.
5. Set disable_gpio_export_in_crs = 1.
BUG=b:160126287
BRANCH=Zork
TEST=emerge-zork coreboot
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I25299861b91cb7b76e512fad743b80221e6ffb4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The USB OC pin mapping is similar enough to move it to the base board
and just have two overrides for trembyle, which is based on an older
version of the schematics, and one override for woomax, which doesn't
use one USB port.
BUG=b:163081097
Change-Id: I7e305d7e6f51d7ef7a4c699e3bacc6bcd699d2f2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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GPIO_89 was marked as EN_DEV_BEEP_L in pre-v3.6 schematics, but it was
never really used on any of the zork variants. Starting with v3.6,
GPIO_89 is left unused in schematics.
This change configures GPIO_89 as PAD_NC in baseboard GPIO
table. Since EN_DEV_BEEP_L still needs to be driven high to allow
speakers to work, GPIO_89 is configured as PAD_GPO driven high on
pre-v3.6 schematics.
BUG=b:62108046
Change-Id: I026cd6cb598667ce6e115c3ec9357a6a56051d39
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44190
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds support for touchscreen power control using:
* GPIO_90 for trembyle based boards
* GPIO_32 for dalboz based boards
By default, baseboard tables configure these GPIOs as PAD_GPO driven
low and override trees expose these pads as enable_gpio to be used by
ACPI power resource.
In order to support pre-v3.6 boards, override tables configure these
pads as PAD_NC and drop the enable_gpio setting from device tree based
on board version.
BUG=b:161935640, b:162747210
Change-Id: Iba5e36b65b44ea11613b4d5fc8f13ce6433f83ab
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44193
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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v3.6 of reference schematics have switched the polarity of reset
signal to touchscreen controller from active high to active low. This
change updates the default configuration in baseboard gpio tables to
set the reset GPIO to output low and override tables in variants to set the
reset GPIO to output high. Additionally, devicetree by default exposes
ACTIVE_LOW configuration for reset GPIO. In order to support pre-v3.6
boards, reset GPIO is updated to ACTIVE_HIGH based on board version.
BUG=b:161937506
Change-Id: I092f274d8eb1920a1cd6d3eccbe8f26b0b28928a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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BUG=b:162010077
Change-Id: Iba3e3ec62cdfd818077017abd28fa754c2ae7797
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Update Woomax configuration including GPIO, memory SPD table, I2C devices
and USB type C.
BUG=b:158343602
BRANCH=None
TEST=emerge-zork coreboot
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I55ba995d9438551d45cb9e17f92b5089ccf4a5fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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These methods are empty and the kernel treats these as optional.
BUG=b:153001807, b:154756391
TEST=Suspend and resume trembyle
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5f2b375c1186951f95b7ac44dc7158a0299013a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43465
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change drops mainboard.asl from zork because none of the objects
defined in it are used.
BUG=b:153879530
Change-Id: If5440bcbce39b4461b44acaec69561663b1ea329
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43519
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This information is redundant since it's already specified in
baseboard/devicetree_trembyle.cb or baseboard/devicetree_dalboz.cb
domain 0 is still required because sconfig uses it as an identity anchor
to match devicetree and overridetree.
BUG=b:157580724
TEST=Boot zork, usb functional
Change-Id: I3c3c1c2410166b99599d7343fae3ee756f4da321
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43437
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create the woomax variant of the zork reference board by copying
the template(coreboot-zork/util/mainboard/google/trembyle)
files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
BUG=b:158343602
BRANCH=None
TEST=emerge-zork coreboot
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I0bb8ce1851f4064d24e48fd8957e2f9fe1e80b53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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