diff options
| author | Martin Roth <martinroth@chromium.org> | 2020-10-30 16:41:32 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-16 11:03:25 +0000 |
| commit | 726504a61a83b12a72fca40c88c7fee1c40b54ad (patch) | |
| tree | 02bb42291254e307eb1f86183e988f3f486585d2 /src/mainboard/google/zork/variants/woomax | |
| parent | fc2047b1f74f42fc2e38fbafdf09929ca39bfa62 (diff) | |
mb/google/zork: Init fingerprint GPIOs for boot vs resume
Add a function that initializes GPIOs based on the sleep type that
the system is coming back from. This allows initialization of the
fingerprint GPIOs which need to be handled differently between wake
from S3 and boot from S5.
On initial boot, the state of the FP sensor could be either
enabled or disabled. Because of this, on boot, we power off
the sensor for >200ms, to reset its state, then power it back on.
In suspend/resume, the fingerprint sensor should remain powered
the entire time.
If fingerprint is disabled on the trembyle-based board, set the pins
to no-connect. Dalboz doesn't have fingerprint and the GPIOS are
configured differently due to the FT5 chip having fewer GPIOS than
FP5, so nothing needs to be initialized there.
There were also a couple of trivial comment clean ups regarding the
FPMCU GPIOS.
BUG=b:171837716
TEST=Boot & Check GPIO states.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I16a2e621145782e0a908bb3e49478586c09a0e0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/zork/variants/woomax')
| -rw-r--r-- | src/mainboard/google/zork/variants/woomax/gpio.c | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/mainboard/google/zork/variants/woomax/gpio.c b/src/mainboard/google/zork/variants/woomax/gpio.c index cb98df7d41..329e7dddb3 100644 --- a/src/mainboard/google/zork/variants/woomax/gpio.c +++ b/src/mainboard/google/zork/variants/woomax/gpio.c @@ -10,10 +10,6 @@ static const struct soc_amd_gpio woomax_bid0_gpio_set_stage_ram[] = { PAD_NC(GPIO_5), /* GPIO_6 NC */ PAD_NC(GPIO_6), - /* GPIO_11 NC */ - PAD_NC(GPIO_11), - /* GPIO_32 NC */ - PAD_NC(GPIO_32), /* GPIO_69 NC */ PAD_NC(GPIO_69), /* RAM_ID_4 */ @@ -37,10 +33,6 @@ static const struct soc_amd_gpio woomax_gpio_set_stage_ram[] = { PAD_NC(GPIO_5), /* GPIO_6 NC */ PAD_NC(GPIO_6), - /* GPIO_11 NC */ - PAD_NC(GPIO_11), - /* GPIO_32 NC */ - PAD_NC(GPIO_32), /* GPIO_69 NC */ PAD_NC(GPIO_69), /* RAM_ID_4 */ |