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Both Dali and Pollock chips have less PCIe, USB3 and DisplayPort
connectivity. While Dali can either be fused-down PCO or RV2 silicon,
Pollock is always RV2 silicon.
Since we have all boards using this code in tree right now,
soc_is_dali() can be renamed and generalized to soc_is_reduced_io_sku().
Change-Id: I9eb57595da6f806305552128b0c077ceeb7c4661
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42833
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change moves the configuration of PCIE_RST0_L as native
function to happen in early GPIO table. This ensures that the PERST#
signal is deasserted as soon as possible when the system comes out
of sleep state in case the sleep path asserted/deasserted the PERST#
as GPIO out.
A big difference in functionality with this change is that PCIE_RST0_L
signal is now configured as part of RO, which should be fine since
all PCIe devices have a second AUX_RESET_L signal or use PCIE_RST1_L
to control the actual reset to the device.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I21a9c25b5a8a6d502cdb79cbe0dbad6ef98d6d63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42739
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change replaces variant_wifi_romstage_gpio_table() with
variant_pcie_power_reset_configure() to handle the reset and power
sequencing for WiFi devices pre- and post- v3 version of schematics.
These are the requirements that need to be satisfied:
1. As per PCI Express M.2 Specification Revision 3.0,
Version 1.2, Section 3.1.4 "Power-up Timing", PERST# should stay
disabled until `TPVPGL` time duration after device power has
stabilized. Value of TPVPGL is implementation specific.
2. For Intel WiFi chip, it is known to get into a bad state if the
above requirement is violated and hence requires a power cycle.
3. On pre-v3 schematics:
- For both dalboz and trembyle references, GPIO42 drives
WIFI_AUX_RESET_L which is pulled up to PP3300_WIFI.
- For both dalboz and trembyle references, PP3300_WIFI is controlled
using GPIO29. This pad gets pulled high by default on PWRGOOD
because of internal pull-up. But, at RESET# it is known to have a
glitch. When GPIO29 gets pulled high, it causes WIFI_AUX_RESET_L to
be pulled high as well. This violates the PCIe power sequencing
requirements. Hence, for pre-v3 schematics on both dalboz and
trembyle, following sequence needs to be followed:
a. Assert WIFI_AUX_RESET_L.
b. Disable power to WiFi.
c. Wait 10ms to allow WiFi power to go low.
d. Enable power to WiFi.
e. Wait 50ms as per PCIe specification.
f. Deassert WIFI_AUX_RESET_L.
4. On v3 schematics:
- For trembyle: WIFI_AUX_RESET_L is driven by GPIO86 which has an
internal PU as well as an external PU to PP3300_WIFI.
- For dalboz: WIFI_AUX_RESET is driven by GPIO29. This is active
high and has an internal PU. It also has an external 1K PD to
overcome internal PU.
- For both dalboz and trembyle references, PP3300_WIFI is
controlled by GPIO42 which has an internal PU and external
PD. Trembyle schematics have a comment saying strong PD of 2.2K but
the stuffed resistor is a weak one (499K). ON dalboz, it uses a
weak PD (which doesn't look correct and instead should be a strong
PD just like trembyle). Having a strong PD ensures that the WiFi
power is kept disabled when coming out of G3 until coreboot
configures GPIO42 as high.
- Thus, for v3 schematics, following sequence needs to be followed:
a. Assert WIFI_AUX_RESET{_L} signal.
b. Enable power to WiFi.
c. Wait 50ms as per PCIe specification.
d. Deassert WIFI_AUX_RESET{_L} signal.
BUG=b:157686402, b:158257076
TEST=Verified that QCA and AX200 cards both continue working. Tested
QCA on Dalboz and Trembyle. Tested AX200 on morphius.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I532131ee911d5efb5130d8710f3e01578f6c9627
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42738
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change updates the baseboard GPIO table in ramstage to match
v3 version of dalboz reference schematics. All variants using this
reference are accordingly updated to configure the GPIOs that changed
as part of v3 schematics.
BUG=b:157165628, b:157744136, b:157743835
TEST=Compiles
Signed-off-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: If9d0e35801f9f9b15eddeb4ec7068fed6d401307
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2251394
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Auto-Submit: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42725
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change updates the baseboard GPIO table in ramstage to match v3
version of trembyle reference schematics. All variants using this
reference are accordingly updated to configure the GPIOs that changed
as part of v3 schematics.
BUG=b:157088093, b:154676993, b:157098434
TEST=Compiles
Signed-off-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib1d6ee2e995c1fca229c20ea63da9a45fb89f64a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2251393
Reviewed-by: Aaron Durbin <adurbin@google.com>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42724
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change updates _v3 version of romstage and wifi GPIO tables
to match v3 schematics.
BUG=b:157165628, b:157744136, b:157743835
TEST=Compiles
Signed-off-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Id8b46fcb4552af6eda5b50224b0557bae37f9ebd
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2251392
Reviewed-by: Aaron Durbin <adurbin@google.com>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42723
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change updates _v3 version of romstage and wifi GPIO tables to
match v3 schematics.
BUG=b:157088093, b:154676993, b:157098434
TEST=Compiles
Signed-off-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ic605559b3226e2ad9b5b3f3fa45c4aa9f9b5fe22
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2251391
Reviewed-by: Aaron Durbin <adurbin@google.com>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42722
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change updates variant_romstage_gpio_table() and
variant_wifi_romstage_gpio_table() to support v3 version of schematics
for dalboz and trembyle reference designs. gpio_set_stage_rom and
gpio_set_wifi are divided into two groups:
a) Pre-v3 (GPIO table for pre v3 schematics):
* gpio_set_stage_rom_pre_v3
* gpio_set_wifi_pre_v3
b) v3 (GPIO table for v3+ schematics):
* gpio_set_stage_v3
* gpio_set_wifi_v3
Currently, both _v3 is a copy of _pre_v3, but will be updated in
follow-up CLs to make it easier to identify what changed from _pre_v3
to _v3.
BUG=b:157088093, b:154676993, b:157098434, b:157165628, b:157744136, b:157743835
TEST=Compiles
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I444875d93100c2f2abdb6dec4312861fd89d9b78
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2251390
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42721
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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RAM_ID GPIOs are configured by ABL based on the information added to
APCB. coreboot does not need to configure these pads. This change
drops the RAM_ID configuration from trembyle baseboard. Dalboz never
really configured RAM_IDs in coreboot.
BUG=b:154351731
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ie1dfcc3c185304d917ab4386920445ba0119ac69
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2252710
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42720
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change moves the GPIOs that need to be configured for early
access in coreboot to early_gpio_table[] in
gpio_baseboard_common.c. These GPIOs include:
* Pads to talk to EC
* Pads to talk to TPM
* Pads to talk to serial console
These should be configured in the first stage that runs coreboot
i.e. in case of VBOOT_STARTS_BEFORE_BOOTBLOCK, it should be done as
part of verstage (which starts on PSP), else it should be done as part
of bootblock (which is the first stage that runs on x86).
This change drops GPIO_137 from early_gpio_table since that is not
really required in early stages.
BUG=b:154351731
TEST=Verified that trembyle still boots.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ifbdbb02cbfc65ddb68f0ae75cf4b1f2ea1656b91
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2252709
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add UPD xhci0_force_gen1 for Trembyle and Ezkinil.
The default setting is set to disable, and set enabled for Ezkinil.
Trambyle -> set default as disable.
Ezkinil -> set enable by request.
BUG=b:156314787
BRANCH=trembyle-bringup
TEST=Build. Verified the setting will be applied on Ezkinil/Trembyle.
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Change-Id: I65d06bfe379f9e42101bfae1a02a619ee2f24052
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2216090
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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We don't use these on zork, so lets save the power.
BUG=b:153001807
TEST=Boot OS and make sure UART 1, 2 and 3 are not probed and remain
powered off.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I2fadeba779b66ec2fb13951b9487118ef0737a94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The picasso_ prefix on the fsp_pcie_descriptor and fsp_ddi_descriptor
structs isn't needed, since this code is picasso-specific, so drop it.
Change-Id: Ia6a0ddb411aa64becc3c23a876f2ea43cb68e028
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42252
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The default HID was removed by a1c82c5ebee. We need to explicitly
specify it.
BUG=b:154756391
TEST=No longer see ERROR: _HID required message in console
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0083f98aea55ba262ac44b0018c9c1d2e12d9f8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This file is not used.
BUG=b:154756391
TEST=Build trembyle and check that peripherals still work
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I721e295546aa75c9745a4836425b6e3e0067afaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This is a copy of the mb/google/zork directory from the chromiumos
coreboot-zork branch. This was from commit 29308ac8606.
See https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/29308ac8606/src/mainboard/google/zork
Changes:
* Minor changes to make the board build.
* Add bootblock.c.
* Modify romstage.c
* Removed the FSP_X configs from zork/Kconfig since they should be
set in picasso/Kconfig. picasso/Kconfig doesn't currently define the
binaries since they haven't been published. To get a working build
a custom config that sets FSP_X_FILE is required.
BUG=b:157140753
TEST=Build trembyle and boot to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3933fa54e3f603985a0818852a1c77d8e248484f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41581
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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