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path: root/src/mainboard/google/volteer/variants
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2021-02-01mb/google/volteer: Drop boldar variantFurquan Shaikh
This variant never really got used and can be deprecated. Change-Id: I5d59460c90266ba5f9c3bdb951f53a37ffae9e03 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-26mb/google/volteer/var/voema: Add camera ACPI configurationDavid Wu
Add camera ACPI configuration for Voema BUG=b:169551066 TEST=Build and boot Voema. Start camera app and able to capture images. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I903e5e0b5f85718c7c9cbb6d5cafb8fc9ad5814e Reviewed-on: https://review.coreboot.org/c/coreboot/+/49302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Jim Lai <jim.lai@intel.com>
2021-01-25mb/google/volteer/eldrid: Use #define symbols for usb2_ports configTim Wawrzynczak
It's easier to understand what these symbolic names mean rather than using the constants; the static.c will will end up (indirectly) including `soc/usb.h` therefore the macros are in scope here. Change-Id: I5ef977a05a2522e177f32c99bfab74f9288ae869 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-25soc/intel/tgl and tgl mb/google,intel: Use the newly added meminit block driverFurquan Shaikh
This change uses the newly added meminit block driver and updates TGL SoC and mainboard code accordingly. TEST=Verified that UPDs are configured correctly with and without this change. Change-Id: I6d58cd6568b7bbe03c4e3011b2301209893e85a9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-22mb/google/volteer/var/elemi: Update dptf parametersWisley Chen
Update DPTF setting from thermal team. BUG=b:177635236 BRANCH=volteer TEST=emerge-volteer coreboot chromeos-bootimage, and verified by thermal team. Change-Id: I87256b5c210ef12c09ef6dd948d80f406ae0500b Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-01-22mb/google/volteer/variants/eldrid: Configure USB2 port for Type-CNick Chen
1. USB2 ports 3 and 8 assigned to Type-C connector 2. USB2 port 3 keep USB2_PORT_SHORT setting and add .type_c flag BUG=b:177481076 TEST=tested on eldrid Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com> Change-Id: I42a39318a151bdf1f5aeb84bb1992be128cb4a4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/49452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-21mb/google/volteer/variant/lindar: Enable SA GV settingKevin Chang
Allow MRC training in SA GV. BUG=b:177779469 BRANCH=firmware-volteer-13672.B TEST=Built and booted into OS. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: Idc9f634135b489450f53f8cd28d80649309d0f70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-21mb/google/volteer/variant/lindar: Configure USB2 port for type-cKevin Chang
Assigned USB2 port to type-c use. BUG=b:177483060 BRANCH=firmware-volteer-13672.B TEST=Built and booted into OS. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I9bd820406124927d56296508be05033217c0d472 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49638 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-18mb/google/volteer/var/elemi: Configure USB2 portsWisley Chen
Configure the USB2 port 3/4/9 1. USB2 port3 assign to WWAN, and elemi have no WWAN. 2. USB2 port4/port9 connect to Type-C C1/C0 BUG=b:177483059 TEST=emerge-volteer coreboot Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: I9affc69cc325b5eb0219b50bfe46f66eb0bb2016 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49473 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-16mb/google/volteer: do UART pad config at board-levelMichael Niewöhner
UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Thus, add the corresponding pads to the early UART gpio table for the board as a first step. Common UART pad config code then gets dropped in CB:48829. Also switch to `bootblock_mainboard_early_init` to configure the pads in early bootblock before console initialization, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: I5e07584d7857052c7a9388331a475f5a073af038 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-15mb/google/volteer/var/voema: Configure USB2 ports for Type CDavid Wu
Based on voema schematics, two USB2 ports 3 and 5 are assigned to type C connectors on Voema board. BUG=b:177483061 b:172535001 TEST=Build and boot Voema. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I12cef85595e511801ab9c563ae4aa26e25875679 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-14mainboard/volteer: Configure UsbTcPortEn valueBrandon Breitenstein
The default value is not sufficient to correctly configure the Type-C ports as it has all ports disabled by default. On Volteer ports 0 and 1 are enabled so setting this value to 0x3 and correctly keeping the IomPortPadCfg values at 0 for ports that have a retimer and ports that are not configured. These values were set to 0x90000000 to avoid s0ix issues which arose from the UsbTcPortEn value being incorrect. BUG=b:159151238 BRANCH=firmware-volteer-13672.B TEST=Built image for Voxel and verified that s0ix cycles complete without any issues Change-Id: Ib4f2bd0f68debd4e97ccaab9e1d8a873dc4e4d9f Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48814 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-13mb/google/volteer/variants/delbin: Update PL1 min and max for DelbinDeepika Punyamurtula
Update PL1 min and max values for Delbin systems BUG=b:168958222 BRANCH=None TEST=Build and verify on delbin system Signed-off-by: Deepika Punyamurtula <deepika.punyamurtula@intel.com> Change-Id: I2152f0dbeb0ae463b78464571b6c434830f0082a Reviewed-on: https://review.coreboot.org/c/coreboot/+/49364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
2021-01-12mb/google/volteer: Configure Voxel USB2 ports for Type CJohn Zhao
Two USB2 ports 4 and 9 are assigned to type C connectors on Voxel board. This update configures these USB2 ports for Type C which will allow USB2 port reset message upstream from PCH to CPU to recover a USB3 device that downgraded to USB2 to upgrade back to USB3. BUG=b:176575892 TEST=Booted to kernel on Voxel board and verified usb2 port reset message enable bits through pch xhci_mmio_base + R_XHCI_MEM_U2PRM_U2PRDE where the offset register R_XHCI_MEM_U2PRM_U2PRDE has value 0x92f4. Validated various USB3 devices enumeration. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ia370a449a41701e690c1c507d70bedfce2076a65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.corp-partner.google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2021-01-11mb/google/volteer: Set FORCE_PWR low at boot timeJohn Zhao
While FORCE_PWR is set high, it prevents retimer from entering low power state. S0ix failure occurs while USB4 Gatkex is connected on Port-0. This change sets FORCE_PWR(GPP_H10) low. This FORCE_PWR GPIO will be toggled by kernel through DSM method while updating retimer firmware. BUG=b:174166586 Cq-Depend: chromium:2594438 TEST=Verifed s0ix cycles with USB4 Gatkex connected on Port-0. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ie4b442e1078379c522a94bfdc00cd99e6f9b8170 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-08mb/google/volteer: Configure Delbin USB2 ports for Type CJohn Zhao
Two USB2 ports 4 and 9 are assigned to type C connectors on Delbin board. This update configures these USB2 ports for Type C which will allow USB2 port reset message upstream from PCH to CPU to recover a USB3 device that downgraded to USB2 to upgrade back to USB3. BUG=b:176575892 TEST=Booted to kernel on Delbin board and verified usb2 port reset message enable bits through pch xhci_mmio_base + R_XHCI_MEM_U2PRM_U2PRDE where the offset register R_XHCI_MEM_U2PRM_U2PRDE has value 0x92f4. Validated various USB3 devices enumeration. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Idb3ce949e1ecf3adc7615e0af79a38a0cc9be18f Reviewed-on: https://review.coreboot.org/c/coreboot/+/49202 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08mb/google/volteer: Update copano device treehao_chou
Update device tree override to match schematics. BUG=b:175896481 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com> Change-Id: I1fb006d750bb2d670885ec8ccc627436c5078072 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-08mb/google/volteer: Add GPIO to copano supporthao_chou
Add support for gpio driver for copano BUG=b:175896481 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com> Change-Id: I1e0f730c9865ed77c7071245b071315a9c6ea4c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48951 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08mb/google/volteer: Copano: Update SPD tablehao_chou
Add memory table to "mem_list_variant.txt", and command to generate files: go run ./util/spd_tools/lp4x/gen_part_id.go src/soc/intel/tigerlake/spd src/mainboard/google/volteer/variants/copano/memory/ src/mainboard/google/volteer/variants/copano/memory/mem_list_variant.txt DRAM Part Name ID to assign MT53D512M64D4NW-046 WT:F 0 (0000) H9HCNNNCRMBLPR-NEE 0 (0000) MT53D1G64D4NW-046 WT:A 1 (0001) H9HCNNNFBMBLPR-NEE 2 (0010) BUG=b:175896481 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com> Change-Id: I2ace17e8fff12d3f5de15a35f609265d8b6ed6b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48948 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07mb/google/volteer/var/elemi: Tune i2c frequencyWisley Chen
Tuning i2c frequency for elemi I2C0: 396.6 KHz I2C1: 395.9 KHz I2C5: 397.1 KHz BUG=b:176794161 BRANCH=volteer TEST=emerge-voleteer coreboot, and measure i2c clock. Change-Id: I23b04a9b5ff8873d9de12e762e8e2786ef474ac0 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-06mb/google/volteer/var/voema: Update Aux settings for Port 0David Wu
On Voema port 0 (MB PORT) does not have a retimer so the port needs to be configured for the SOC to handle Aux orientation flipping. BUG=b:176462544 TEST=tested on voema Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I3d31a5b848f56126f8ffe2babb29085471e8224f Reviewed-on: https://review.coreboot.org/c/coreboot/+/48976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2021-01-05mb/google/volteer/var/voema: Enable IPU for voemaDavid Wu
Enable IPU for voema for MIPI camera. BUG=b:169551066 TEST=IPU is enabled and shows in lspci. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I34736bffd4dc61a840003afe5afd6a9c8dc32e62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49002 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-24mb/google/volteer/variant/lindar: Add SSD D3 cold supportKevin Chang
This patch add SSD D3 cold support for lindar. BUG=b:172405687 BRANCH=firmware-volteer-13521.B TEST=Built and booted into OS. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: Ie343bbff3bde4ff2a7e89bd384d5661af372b560 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-24mb/google/volteer/var/voema: Disable PCIe 7 and 8 for WLAN and SD cardDavid Wu
Based on latest schematic, disable PCIe 7 and 8 for WLAN and SD card. BUG=b:169356808 TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I2a4658a382c094c2a5b16b7acaf464f54e9897b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-24mb/google/volteer/var/voema: Enable RTD3 for the NVMe deviceDavid Wu
Enable Runtime D3 for the volteer variants that have GPIO power control of the NVMe device attached to PCIe Root Port 9. Enable the GPIO for power control for variants that do not already have it configured to allow the power to be disabled in D3 state. BUG=b:169356808 TEST=tested on voema Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I28ef074225c533e1a97b6ec4a1a5dd1dcc198168 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48848 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-22mb/google/volteer: Add GPIO to drobit supportFrankChu
Add support for gpio driver for drobit BUG=b:175351914 BRANCH=none TEST=emerge-volteer coreboot Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I54ba182c6da3db282961b3c72a4d2d11d1001e95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-22mb/google/volteer: Update SPD table for drobitFrankChu
drobit memory table as follow: value Vendor Part number 0x00 MICRON MT53E512M32D2NP-046 WT:E 0x00 HYNIX H9HCNNNBKMMLXR-NEE 0x01 MICRON MT53E1G32D2NP-046 WT:A 0x02 HYNIX H9HCNNNCPMMLXR-NEE BUG=b:175351914 BRANCH=none TEST=emerge-volteer coreboot Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Icd9439f8449856d4ec6798a4e4310dd139bce05f Reviewed-on: https://review.coreboot.org/c/coreboot/+/48496 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-22mb/google/volteer: Update drobit device treeFrankChu
Update drobit device tree override to match schematics. BUG=b:175351914 BRANCH=none TEST=emerge-volteer coreboot Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I48a3024df4270b111b90c4fb56847aad6e65bfa1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-21volteer/variants/eldrid: Enable RTD3 for the NVMe deviceNick Chen
Enable Runtime D3 for the volteer variants that have GPIO power control of the NVMe device attached to PCIe Root Port 9. Enable the GPIO for power control for variants that do not already have it configured to allow the power to be disabled in D3 state. BUG=b:161270810 TEST=tested on eldrid Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com> Change-Id: I941c8a9bb3221ad90528c323cd0f267dc77d2af3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-11mb/google/volteer: Clean up romstage and ramstage UPDsTim Wawrzynczak
Move the manual calls to fw_config_probe() into the devicetree; the AUDIO probe is trivial, and the TCSS devices (DMA0, iTBT RP0 & RP1) are already guarded with probe statements in the baseboard devicetree, so the code in romstage.c was redundant. The variants seem to have their USB4 probe statements correct as well, so the manual UPD setting in mainboard.c was also unnecessary. BUG=none TEST=abuild google/volteer Change-Id: I1d067ff3d181b152c784634ff99202bb2b9202f7 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-11mb/google/volteer/variant/lindar: Correct IOM port configurationKevin Chang
Correct IOM setting and TCSS AUX setting to fix type C C0 port display can't output after flip. BUG=b:173093980 BRANCH=firmware-volteer-13521.B TEST=Built and booted into OS, test USB function normally. Change-Id: I827a2d8a5b01dce412b4170fde0f638670ab8baf Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-11mb/google/volteer: Improve type-C Port 1 USB2 Eye Diagram for delbinFrankChu
In order to pass DB type-C Port 1 USB2 eye diagram, DB USB2 PHY register needs to be overridden. port#1 PortUsb20Enable=1 Usb2PhyPetxiset=3 Usb2PhyTxiset=2 Usb2PhyPredeemp=7 Usb2PhyPehalfbit=1 BUG=b:173676539 BRANCH=None TEST=emerge-volteer coreboot chromeos-bootimage Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I41cda27f97287fae5c23dc9843fdf0a8a33057f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-11mb/google/volteer: Assert BT_DISABLE_L (GPP_A13) in early_gpio_tableAlex Levin
BT_DISABLE_L (GPP_A13) has to asserted in early_gpio_table to reset bluetooth on reset. BUG=b:171085081 TEST=volteer2 boots; scope shows assertion of the signal Change-Id: Iaa5799e9cab69c074b7920604c8a6c85ad07358a Signed-off-by: Alex Levin <levinale@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-12-10mb/google/volteer: Fix a few devicetree device refsTim Wawrzynczak
Commit b0e169ac85 included a few small omissions and typos when converting 'device pci xx.y' to 'device ref blah' after adding the new chipset.cb file for TGL. This patch fixes these errors: 1) MIPI camera support requires I2C2 & I2C3 enabled 2) Malefor SAR sensor is on I2C2, not I2C3 BUG=b:175165653 TEST=abuild -p none -t google/volteer -x -a -c max Change-Id: I577957d67f47bbe88bbc2535fb1cb5c8f7390438 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2020-12-09mb/google/volteer/variant/volta: add Synaptics touchpad.Sheng-Liang Pan
add new Synaptics touchpad for volta. BUG=b:174802144 TEST=emerge-volteer coreboot and check touchpad function work. Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I7fc8d08b8b2229ca9252618f159fc9c6f91f9d7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/48395 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08mb/google/volteer/variant/lindar: Add PMC.MUX.CONx device configuration and ↵Kevin Chang
disabling DDI port 1 and 2 HPD. This patch adds the PMC MUX and CONx devices for lindar. Device specific method contains the port and orientation details used to configure the mux. BUG=b:172533907 BRANCH=firmware-volteer-13521.B TEST=Built and booted into OS. Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: Id5ee78b7ece8421144086af9b95f5f0d849be56c Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-12-08mb/google/volteer/var/voxel: Update DPTF parametersSheng-Liang Pan
remove TCC offset setting in overridetree.cb, use default setting(# TCC of 90) in baseboard. BUG=b:174547185 BRANCH=volteer TEST=emerge-volteer coreboot Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Iaac1fae12ccaa8a623bc2dc3105262918523d440 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48264 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08mb/google/volteer: Update I2C5 bus freq and devicetree.Stanley Wu
Update lindar gpio settings for Synaptics trackpad no function issue. Update I2C5 bus freq to 400kHz. Improve Goodix Touchscreen power on sequence. BUG=b:160013582 BRANCH=firmware-volteer-13521.B TEST=emerge-volteer coreboot and check system dmesg and evtest can get device. Verify trackpad function workable. Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I8c1ab6bab1f9de187e2a78ead7b5bbaf758f5fcf Reviewed-on: https://review.coreboot.org/c/coreboot/+/48150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2020-12-08mb/google/volteer: ACPI nodes for volteer2_ti50Jes Klinke
Unique among the Volteer devices, the volteer2_ti50 variant connects to the TPM via I2C. This CL introduces the proper devicestree declarations for the Linux kernel to recognize that. overridetree.cb is shared between "sub"-variants volteer2 and volteer2_ti50, so both will have two TPM nodes, the I2C being disabled by default. The odd _ti50 variant then has code in variant.c to enable the I2C node and disable the SPI node. BUG=b:173461736 TEST=abuild -t GOOGLE_VOLTEER2{_TI50,} -c max -x Change-Id: I5576a595bbabc34c62b768f8b3439e35ff6bcf7b Signed-off-by: Jes Bodi Klinke <jbk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48223 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08mb/google/volteer/variants: Update Power Limit2 minimum valueSumeet R Pawnikar
Update Power Limit2 (PL2) minimum value to the same as maximum value for volteer variants like baseboard, delbin, eldrid, terrador and todor. All other variants uses the DTT entries from baseboard devicetree since there is no override present for those variants. DTT does not throttle PL2, so this minimum value change here does not impact any existing behavior on the system. BUG=None BRANCH=volteer TEST=Build and test on volteer system Change-Id: I568e87c87ef517e96eaab3ff144b1674d26ae1e6 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-07mb/google/volteer/var/elemi: use devtree aliases for PMC MUX connectorsWisley Chen
refer to cb:45878 Now that soc_get_pmc_mux_device() is gone, the PMC MUX connector devices can be hooked up together via devicetree aliases. BUG=b:174735512 BRANCH=volteer TEST=build and type-c display work Change-Id: I0bf84e2691856c9760d8fa9b6d853b04be10390a Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48268 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-05mb/google/volteer/var/voema: Add MIPI camera supportDavid Wu
1. Add VARIANT_HAS_MIPI_CAMERA to Kconfig.name 2. Add mipi_camera.asl BUG=b:169356808,b:169551066 TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I63d133246dbdc6aff7bf97d98f95052edf53bac9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47668 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-05mb/google/volteer: Create copano variantFrankChu
Create the copano variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.3.1). BUG=b:174413884 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_COPANO Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ib06625f492f68a6a6f5c6b382772b68f1eb681ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/48136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
2020-12-05mb/google/volteer/variant/lindar: Correct SD card reader power sequenceKevin Chang
According to the spec provided by Bayhub, the 3.3V power rail must be enabled at least 100ms before reset is released. To ensure this, set the power enable signal in the bootblock GPIO table. BUG=b:173676531 BRANCH=firmware-volteer-13521.B TEST=Built and booted into OS, test USB function normally. Change-Id: I0c536f36c138ace93766f3024f6ec5d47b38269f Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47799 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02mb/google/volteer: Add fw_config entries for boot deviceDuncan Laurie
Add the fw_config entries for the newly added boot device fields. These are added as separate fields since a board may have more than one selected. BUG=b:173129299 TEST=abuild google/volteer Change-Id: I2af9ffcf0b90d4f4b7f2f31613ee110d8f350454 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-02mb/google/volteer: Add additional SD cards to device listDuncan Laurie
The initial commit only focused on GL9755S and RTS5261, but there were recently other cards added to the fw_config and those also need to be added to the probe lists. BUG=b:173207454 TEST=abuild google/volteer Change-Id: Ic27074a016ffbd4c4dd86104a6d85437357c4b82 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-30mb/google/volteer: Create drobit variantFrank Chu
Create the drobit variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:171947885 BRANCH=none TEST=emerge-volteer coreboot Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I63b7312bba236bd5af028359804d042f6850d8ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/47787 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30mb/google/volteer/variants/delbin: Enhance I2C5 bus freq closer 400 kHzFrank Chu
The current I2C5 bus frequency is 367 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, scl_hcnt value for I2C5 to bring the bus frequency closer to 400kHz. BUG=b:173670150 TEST=Verified that I2C5 frequency is between 386-387kHz. Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I6d60abe15645dc51ed9ee30975d2521b8940c2d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47736 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30mb/google/volteer/variant/copano: Add memory part supportNick Vaccaro
Add support for the following 5 LPDDR4x memory parts: - MT53E512M64D4NW-046 WT:E - H9HCNNNCRMBLPR-NEE - MT53D1G64D4NW-046 WT:A - H9HCNNNFBMBLPR-NEE - MT53D512M64D4NW-046 WT:F DRAM Part Name ID to assign ------------------------------------------- MT53E512M64D4NW-046 WT:E 0 (0000) H9HCNNNCRMBLPR-NEE 0 (0000) MT53D1G64D4NW-046 WT:A 1 (0001) H9HCNNNFBMBLPR-NEE 2 (0010) MT53D512M64D4NW-046 WT:F 0 (0000) BUG=b:172993397 TEST=none Change-Id: Iff8f6257c6cff77fc3f0bda7e75434f9f4de1777 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47981 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-29mb/google/volteer: eldrid: use devtree aliases for PMC MUX connectorsScott Chao
Now that soc_get_pmc_mux_device() is gone, the PMC MUX connector devices can be hooked up together via devicetree aliases. BUG=b:172528109 BRANCH=firmware-volteer-13521.B TEST=built and USB3.0, type-c display work. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: Iedf9b972b341064ff62a4443bfa83f69c8c60108 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48066 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-25mb/google/volteer: Update Eldrid USB2 port settings in overridetreeNick Chen
1. Disable M.2 WWAN and Type-A Port A1 2. Change register 4 to 3 and tuning USB2 Port1 eye diagram 3. Lower camera driving BUG=b:169105751 Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com> Change-Id: I6b8a5c0d5e814de232d79a43354f5ec0220fc5ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/47863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-25mb/google/volteer/variant/lindar: change speaker smart amplifier to ALC1011Stanley Wu
Lindar change amp to ALC1011 Add ALC1011 amp acpi info to devicetree BUG=b:171771736 BRANCH=firmware-volteer-13521.B TEST=build and verify ALC1011 can be recognized. Change-Id: I4d83a19b3baa87cc926bb7c3a2cb96bf3165d2f4 Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-11-25mb/google/volteer/var/elemi: Add H5ANAG6NCJR-XNCWisley Chen
Add H5ANAG6NCJR-XNC. BUG=b:165461530 BRANCH=volteer TEST=emerge-volteer coreboot Change-Id: I827158ce0abe764f1e3b5de46abf50dc148a6ff0 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-24mb/google/volteer/var/voxel: Update DPTF parametersSheng-Liang Pan
update the DPTF parameters received from the thermal team. BUG=b:167523658 TEST=emerge-volteer coreboot Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Iafc3fb389ade5cfec79a816a28880262bdce7c74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47858 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24mb/google/volteer: fw_config: Add setting for new sd readersZhuohao Lee
This patch adds three settings for the new sd readers. The new assigned values are: 1. RTS5227S: 3 2. L9750: 4 3. SD_OZ711LV2LN: 5 BUG=b:173676531 BRANCH=volteer TEST=abuild -t google/volteer Change-Id: I595695f99d3298f146fcdb7c2b942ce007ae9327 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-11-22mb/google/volteer: Remove unused devices for terrador and todorDavid Wu
Remove the following devices - Goodix Touchscreen - SAR0 Proximity Sensor BUG=b:173480406 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I6b56ca136533b53ff7e003a665be67fbe12c1ade Reviewed-on: https://review.coreboot.org/c/coreboot/+/47690 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22mb/google/volteer/var/voema: Update gpio and devicetree settingsDavid Wu
Based on latest schematic and gpio table of voema, update gpio and devicetree settings for voema Proto. BUG=b:169356808 TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I719a9948ed0d60e1de5368e096ff60c2345803b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-20mb/google/volteer/var/elemi: Update gpioWisley Chen
1. Config EN_PP3300_SSD (GPP_B2) to gpo 2. EMMC_CLKREQ_ODL(GPP_C1) change to GPP_H11 3. WLAN_PERST_L (GPP_H10) change to GPP_H10 BUG=b:172630765, b:171467336 BRANCH=volteer TEST=emerge-volteer coreboot chromeos-bootimage and boot into emmc Change-Id: I9d112373c4ecd2cea5ce3d2d47b190c061d50da6 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47705 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20mb/google/volteer/var/elemi: enable Genesys Logic GL9763EWisley Chen
Enable Genesys GL9763E as PCI-to-eMMC bridge. BUG=b:171467336 BRANCH=volteer TEST=emerge-volteer coreboot Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: I858c12151df5b6fc19132869317edfa1b090335d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-20mb/google/volteer: Add keyboard layout to fw_configDuncan Laurie
A new field was defined for different keyboard layouts, so add this field to the list and provide the two options that were defined. Change-Id: Ic357446725e34221040705929d54cbce94c5ab8b Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-20mb/google/volteer/variants: Set TCSS PCIe RP0 to hidden by defaultDuncan Laurie
Set the default state of the TCSS PCIe RP0 to hidden so that coreboot does not allocate resources to this hotplug root port. The default behavior on the reference design is that there is only one USB4 port attached to port C1 while port C0 is only a USB3 port. Meanwhile the Voxel and Terrador variants do have USB4 on both C0 and C1 ports, so these boards change the default to 'on' so that coreboot does allocate resources for the hotplug port. BUG=b:159143739 BRANCH=volteer TEST=build volteer and voxel and check the resulting static.c to ensure the device is hidden or not. Also boot with the two different configurations and ensure resources are assigned or not. Finally check that S0ix still functions with the C0 port set to 'hidden' after authorizing a PCIe tunnel on port C1. Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I8bb05ae8cd14412854212b7ed189cfa43d602c1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47198 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20mb/google/volteer: Enable RTD3 for SD cardDuncan Laurie
Enable the PCIe RTD3 driver for the PCIe attached SD card interface and provide the enable/reset GPIOs. These GPIOs are common across all variants so this is implemented in the baseboard devicetree with an fw_config probe if the device is present. The RTS5261 device does not have an enable GPIO so it is disabled in a workaround in mainboard.c, along with marking the SD-Express device as external. BUG=b:162289926, b:162289982 TEST=Tested on Delbin platform to ensure the system can enter the S0i3.2 substate and suspend/resume is stable. enabling this for the regular Genesys Change-Id: I40fe05829783c7bce2a2c4c1520a4a7430642e26 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-20mb/google/volteer/variants: Enable RTD3 for the NVMe deviceDuncan Laurie
Enable Runtime D3 for the volteer variants that have GPIO power control of the NVMe device attached to PCIe Root Port 9. Enable the GPIO for power control for variants that do not already have it configured to allow the power to be disabled in D3 state. BUG=b:160996445 TEST=tested on delbin Change-Id: I6ebf813c6c3364fec2e489a9742f04452be92c45 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46262 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19mb/google/volteer/var/terrador: Correct enable_gpio to GPP_F16David Wu
The GPP_F16 is for enable_gpio after check the schematic. BUG=b:151978872 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I63f43c231e624ed034ef18e8f06942ff3622d821 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-11-18mb/google/volteer: Add new Audio option to FW_CONFIGWisley Chen
Volteer has a new Audio option in FW_CONFIG. This patch adds support for it and when enabled, programs GPIO pins for I2S functionality. BUG=b:171174991 TEST=emerge-volteer coreboot Change-Id: I85bc37980957a3fb6c795858a4e4f44f3e3cc332 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-17mb/google/volteer/variants/volteer2: Tune Volteer2 I2C2 bus frequencyJohnny Li
The current I2C2 bus frequency is 344 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, sda_hold value for I2C2 to bring the bus frequency closer to 400 kHz. BUG=b:153588771 TEST=Verified that I2C2 frequency is 380 kHz. Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com> Change-Id: I96fa5ed586de41324733ac7537b6bd73f39fc176 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47558 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-16volteer/variants/eldrid: Goodix touch panel power-on sequence tuningNick Chen
1. Enable panel stop GPIO in ramstage 2. generic.reset_delay_ms change to 30 BUG=b:171365316 Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com> Change-Id: I90ca39312252c668da6298183e598392bc9f9f28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-11-16mb/google/volteer/var/voema: Add memory parts and generate DRAM IDsDavid Wu
This change adds memory parts used by variant voema to mem_parts_used.txt and generates DRAM IDs allocated to these parts. Added memory 1. H9HCNNNCRMBLPR-NEE 2. H9HCNNNFBMBLPR-NEE 3. MT53D1G64D4NW-046 WT:A BUG=b:172751925,b:172781673,b:172782100,b:172781562 TEST=emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ic832155448fb07152b906aa04ca49d384ec47b34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47351 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13mb/google/volteer/variant/lindar: Update devicetree settingsStanley Wu
Update I2C address for Goodix touchscreen and add ELAN touchscreen & Synaptics trackpad device. Follow CB:47415 to correct HID over I2C device to be level triggerd. BUG=b:160013582 TEST=emerge-volteer coreboot and check system dmesg and evtest can get device. Change-Id: I070fb0e06b588f128253270502c9c2c427c62b84 Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-13mb/google/volteer: Configure IRQs as level triggered for HID over I2CKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: Ie7b82ea07ef97b2096d75229c445bd3a65cb3be0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-09mb/google/volteer/eldrid: Describe the privacy_gpioRicardo Ribalda
Add information regarding the privacy pin on the overridetree and the gpio. BUG=b:171888751 Change-Id: I1ab19a863715ba5a928dd7c16402d398e5475edc Signed-off-by: Ricardo Ribalda <ribalda@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-09mb/google/volteer/var/voema: Add memory parts and generate DRAM IDsDavid Wu
This change adds memory parts used by variant voema to mem_parts_used.txt and generates DRAM IDs allocated to these parts. Added memory 1. MT53E512M64D4NW-046 WT:E 2. MT53E1G64D8NW-046 WT:E BUG=b:171755775 TEST=emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I24d466f92a7e0fa3ab2f6241f0b5af025c53ed98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-11-09mb/google/volteer/variants/volteer2: Tune I2C3 camera bus freq 400 kHzJohnny Li
The current I2C3 bus frequency is 341 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, sda_hold value for I2C3 to bring the bus frequency closer to 400kHz. BUG=b:153588771 TEST=Verified that I2C3 frequency is 394kHz. Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com> Change-Id: Ie1ef95bb39d71fbb113120a0ec88305bc23e7ab9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-11-06mb/google/volteer/var/elemi: Update gpio and devicetreeWisley Chen
Update gpio and devicetree for elemi. BUG=b:170604353 TEST=emerge-volteer coreboot and boot into kernel Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: I5b8880d485ed73aa4e65c1249c58f02c8f0c6501 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-04mb/google/volteer/var/voema: Update dq/dqs mappingsDavid Wu
Update dq/dqs mappings based on voema schematics. BUG=b:169356808 BRANCH=volteer TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I1aae4286278e712bf29ebb15738477828d3f74d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-02mb/google/volteer/var/volteer2: Merge `common_soc_config`Angel Pons
SCONFIG complains because of the duplicate devicetree entry. Change-Id: Ibdd60efdbcee5bda7c570d4b98f29cc8ede584cb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jes Klinke <jbk@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-02mb/google/volteer/variants: Describe USB ports in devicetreeDuncan Laurie
Add the USB ports to the devicetree for describing them in ACPI, including defining the port relationships and defining the reset GPIO for the bluetooth device. BUG=b:151731851 TEST=tested on volteer, all other boards were checked against the latest available schematic. Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: Ia1e5b71e7750a478ff79372c48616bbf5c21b79c Reviewed-on: https://review.coreboot.org/c/coreboot/+/46853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-02mb/google/volteer: Add DB_USB3_NO_C option for DB_USB fieldDuncan Laurie
Define option value 6 for DB_USB where there is a Type-A port but no Type-C port on the daughterboard. BUG=b:151731851 TEST=build volteer boards Change-Id: I489d24316556dedfecd821e502f1461010b1400f Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-02mb/google/volteer: New variant for Volteer reworked with DauntlessJes Klinke
For development of the firmware to run on the Dauntless TPM, a number of Volteer2 devices are being reworked to replace the H1 chip with probe wires to connect to an external Dauntless development board. Some modification to the AP firmware is required, not least because the Dauntless chip is connected via I2C bus, instead of SPI. Most of the Dauntless developers will not otherwise have a Chrome OS chroot. Because of the above, I think it makes sense to have a new variant, for the reworked devices, which I intend to create with this CL. BUG=b:169526865 TEST=abuild -t GOOGLE_VOLTEER2_TI50 -c max -x Change-Id: Ibdcd6c2ce3941c229518f21f0e479890b5d76dd1 Signed-off-by: Jes Bodi Klinke <jbk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-02mb/google/volteer/var/terrador: Enable SaGv supportDavid Wu
Enable SaGv for terrador. BUG=b:171763116 BRANCH=volteer TEST="emerge-volteer coreboot" compiles successfully. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ie00166a619424a67f70f870e55822ae2cc6d023d Reviewed-on: https://review.coreboot.org/c/coreboot/+/46841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-11-02mb/google/volteer/variants/delbin: Update DPTF parameters for delbinFrank Chu
Configure board specific DPTF parameters for delbin BUG=b:168958222 BRANCH=volteer TEST=build and verify by thermal team Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46676 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02volteer: Create voema variantDavid Wu
Create the voema variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:171755775 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_VOEMA Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I4e1872d1ebff6fefdfb232f1ff82fce95a1ec643 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47007 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02mb, soc/intel: Reorganize CNVi device entries in devicetreeFurquan Shaikh
This change reorganizes the CNVi device entries in mainboard devicetree/overridetree and SoC chipset tree to make it consistent with how other SoC internal PCI devices are represented i.e. without a chip driver around the SoC controller itself. Before: chip drivers/wifi/generic register "wake" = "..." device pci xx.y on end end After: device pci xx.y on chip drivers/wifi/generic register "wake" = "..." device generic 0 on end end end Change-Id: I22660047a3afd5994400341de0ca461bbc0634e2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-11-02mb/google/volteer: Disable DPTF active policy for terrador and todorDavid Wu
Terrador and Todor are fanless design, so disable DPTF active policy. BUG=b:171019363,b:170699797 BRANCH=volteer TEST=build and verify by thermal team Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I53a33b8706d7a7d4013a2a5627a620223fcffc3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/46874 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30mb/google/volteer: Remove RIPTO support for cameraDaniel Kang
GPIO D4 was used for camera reset for both front and rear cameras (RCAM_RST_L/FCAM_RST_L) in RIPTO. For later volteer versions, GPIO F15 is dedicated to the rear camera reset (RCAM_RST_L). Before, BOARD_GOOGLE_VOLTEER flag was used for setting the right RCAM_RST_L per volteer version. However, we don't support RIPTO anymore. Also using flags for different volteer version support can be error-prone. Removing RIPTO support. BUG=b:171726823 BRANCH=none TEST=Build and boot volteer proto2 or later version. Camera should work without an issue. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: I961fc17092887b4807c12c95f7139bb7e7b33e91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46826 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30mb/google/volteer: Separate power resource for VCMDaniel Kang
The camera privacy LED blinks during the boot and this gives a wrong impression to the users that the camera is being used during the power up. The blink happens when the camera module is probed and a series of kernel patches and coreboot patches are being submitted to resolve the issue. The kernel patches are submitted to the chromium gerrit. https://chromium-review.googlesource.com/2403386 https://chromium-review.googlesource.com/2403387 https://chromium-review.googlesource.com/2403385 https://chromium-review.googlesource.com/2403384 https://chromium-review.googlesource.com/2403383 https://chromium-review.googlesource.com/2403382 https://chromium-review.googlesource.com/2403381 https://chromium-review.googlesource.com/2403380 This is to separate the power resource for the VCM so that it can be controlled by the driver and suppress the LED turn on. BUG=b:169049942 BRANCH=none TEST=Build and boot volteer board. Monitor camera privacy LED and check if it blinks. It should not blink. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: Id51c98e42c5f20e231d8096c9d2d98deebc7c968 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tomasz Figa <tfiga@google.com>
2020-10-30tigerlake mainboards: switch to devtree aliases for PMC MUX connectorsTim Wawrzynczak
Now that soc_get_pmc_mux_device() is gone, the PMC MUX connector devices can be hooked up together via devicetree aliases. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib51764da5b3c029f9ac7ac60199a0aedfc7f29b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45878 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30mb/google/volteer/variants/volteer2: I2C5 trackpad bus freq 400 kHzJohnny Li
The current I2C5 bus frequency is 367 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, scl_hcnt value for I2C5 to bring the bus frequency closer to 400kHz. BUG=b:153588771 TEST=Verified that I2C5 frequency is between 389-396kHz. Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com> Change-Id: If0803a74ba9071acf15486ce4038261c1681a92f Reviewed-on: https://review.coreboot.org/c/coreboot/+/46142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-29mb/google/volteer: correct memory id for elemiWisley Chen
BUG=b:170604353 BRANCH=volteer TEST=emerge-volteer coreboot, and boot into kernel. Change-Id: If354aa158f3ad60193268f38278a44f9c99bf3db Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46770 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26mb/google/volteer: Add a DPTF policy for EldridNick Chen
1. Enable dptf feature and remove fan control part from overridetree.cb 2. Update tcc offset to 5 3. Follow thermal validation and update PL2 max_power to 51 BUG=b:167931578, b:170357248 Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com> Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-26mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`Michael Niewöhner
The dt option `speed_shift_enable` is obsolete now. Drop it. Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-10-26mb/google/volteer/var/voxel: enable GPP_D17 for FCAM_PWRSheng-Liang Pan
Enable front camera power in ramstage. BUG=b:169170677 BRANCH=volteer TEST="emerge-volteer coreboot" compiles successfully. Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I8b5a9a8333ed518883aa3664a115a4ba2e8a0218 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: YH Lin <yueherngl@google.com>
2020-10-26mb/google/volteer: Use PCIE_CLK_NOTUSED in place of 0xFFDavid Wu
Use PCIE_CLK_NOTUSED in place of 0xFF for unused PCIe ports BUG=none BRANCH=master TEST="emerge-volteer coreboot" compiles successfully. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I35f2bbce35420fa98541a35f77b14df7440e7980 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26mb/google/volteer/var/terrador: Disable SRCCLKREQ1#David Wu
According to the schematic, SRCCLKREQ1# is not connected, so disable it for terrador and todor. BUG=b:171278849 BRANCH=volteer TEST="emerge-volteer coreboot" compiles successfully. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I5f7734d64390bfadbdb8d152261103adb8e75f40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-26mb/google/volteer/var/voxel: Disable SRCCLKREQ1#Sheng-Liang Pan
According to the schematic,SRCCLKREQ1# is not connected,so disable it on voxel. BUG=b:171279034 BRANCH=volteer TEST="emerge-volteer coreboot" compiles successfully. Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Ibc4f766bd737f30a9ac3c7354d54398e0c36d59d Reviewed-on: https://review.coreboot.org/c/coreboot/+/46612 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23mb/google/volteer: Add settings for noise mitgationShaunak Saha
Enable acoustic noise mitgation for volteer platforms. BUG=b:153015585 BRANCH=none TEST= Measure the change in noise level by changing the values in devicetree. Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Change-Id: I69a6453091bf607d3c5847c99bc077e6b7dbc639 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45053 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-20mb/google/volteer/var/terrador: Configure board specific DPTF parametersDavid Wu
Configure board specific DPTF parameters for terrador and todor BUG=b:171019363,b:170699797 BRANCH=volteer TEST=build and verify by thermal team Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I19935ca98ec7a078869e73d65ea471df70f37121 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-20mb/google/volteer/variants/lillipup: add generic SPDsNick Vaccaro
Add generic LPDDR4x SPD support for the following three memory parts: • K4U6E3S4AA-MGCR • H9HCNNNBKMMLXR-NEE • MT53E512M32D2NP-046 WT:F BUG=b:170264065 TEST=none Change-Id: Ie3163763a0ce291f27c43181d35c070c218b461d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-19mb/google/volteer: Enable USB4 retimer driverDuncan Laurie
Enable the USB4 retimer driver with GPP_H10 as the power control. Change-Id: I166bc477f94c159bb411620a6bf77b5d1f194fb2 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-10-19mb/google/volteer/elemi: Add memory.c for DDR4Wisley Chen
Add new memory.c to support DDR4 memory types. BUG=b:170604353 TEST=emerge-volteer coreboot chromeos-bootimage Change-Id: If96b0bda0ce95766f0957c37aa7cbecefc9c03e0 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 01:32:01 +0000