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2023-08-10mb/google/myst: Enable PSP VerstageKarthikeyan Ramasubramanian
Split the signed AMDFW binaries into their own section and enable PSP verstage. BUG=b:284984667 TEST=Build Myst BIOS image with PSP Verstage. Boot to OS successfully with PSP verstage and a separate section for signed AMDFW binaries. Change-Id: Ie0a54c157ebdebf9a0c95933c96865e0782a0f90 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-08-06mainboard: Add SPDX license headers to MakefilesMartin Roth
To help identify the licenses of the various files contained in the coreboot source, we've added SPDX headers to the top of all of the .c and .h files. This extends that practice to Makefiles. Any file in the coreboot project without a specific license is bound to the license of the overall coreboot project, GPL Version 2. This patch adds the GPL V2 license identifier to the top of all makefiles in the mainboard directory that don't already have an SPDX license line at the top. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic451e68b1ad9ccdf34484dd98bd7fca7e177ef22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68982 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-26mb/google/myst: Override PSP_SOFTFUSE_BITS to fix non-serial bootKonrad Adamczyk
With currently set default PSP_SOFTFUSE_BITS for phoenix SoC, the non-serial build does not boot on Myst. Override PSP_SOFTFUSE_BITS by disabling SPIConfig to also get the non-serial build booting. The documentation of PSP_SOFTFUSE_BITS is available in #55758 doc (NDA). BUG=b:292489356 TEST=Flash image-myst.bin, verify that it's able to boot on Myst proto0. Change-Id: Id4472fd85fdefcafb8378199dbaa054fab8b3274 Signed-off-by: Konrad Adamczyk <konrada@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76713 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-07-24mb/google/myst: Disable APOB NVFred Reitberger
Disable the APOB cache for only Myst, and re-enable APOB for other Phoenix SOC mainboards. BUG=b:290763369 TEST=verify APOB cache is disabled Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ie611e0b84611b2f50c989c75612fc2186b2dbfdf Reviewed-on: https://review.coreboot.org/c/coreboot/+/76567 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-07-14mb/google/myst: Remove PRESERVE FMD flag for RW_MRC_CACHEMartin Roth
The PRESERVE flag in the FMD file tells futility not to erase the fmap partition when updating the firmware. Because of an issue on myst right now, we want the RW_MRC_CACHE partition to be erased when the firmware is updated. BUG=b:290763369 TEST=None Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id586ae057b2fd6d513ddbba5e1284dea39467d95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76478 Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-14mb/amd,google/*/port_descriptors: use dxio_link_hotplug_type enum valuesFelix Held
Use the proper dxio_link_hotplug_type enum values for the link_hotplug field in the DXIO descriptors to replace the magic values in the code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ieb1513737e6022a668287dc80a39d96cda2b18d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76439 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-14mb/google: AMD: move tpm_tis to AMD common codeGrzegorz Bernacki
It moves cr50_plat_irq_status() to common code and adds Kconfig option to specify GPIO used for interrupt. BUG=b:277787305 TEST=Build all affected platform and confirm using right GPIO number. Tested on Skyrim. Change-Id: I775c4e24cffee99b6ac3e05b58a75425029a86c8 Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75621 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-07-06util/apcb: Add apcb edit tool for phoenixRob Barnes
Add a new apcb edit tool, apcb_v3a_edit.py, that injects SPDs into an APCB for phoenix platform. The tool makes several assumptions: * Each SPD only uses blocks 0, 1, 3 and 5. All other blocks are zero. * Each block is 64 bytes. * Dimm and socket are always 0 * Unused SPD entries are zero'd BUG=b:281983434 BRANCH=None TEST=build, flash, boot myst Change-Id: Ifb50287de77138170714a702ab87d56427aacfef Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76188 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-06drivers/tpm: Move tis_plat_irq_status to cr50 driverGrzegorz Bernacki
tis_plat_irq_status() function is used only by Google TPM. It should be moved to drivers/tpm/cr50.c. The name of the function was changed to cr50_plat_irq_status(). BUG=b:277787305 TEST=Build all affected platforms Change-Id: I78dc39f2c7b44232b06947d3dfe6afa52807ced8 Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75917 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-06-22vc/amd/fps/phoenix/platform_descriptors: drop logical-physical mappingFelix Held
For Phoenix the lane numbers in the DXIO descriptor match the ones in the schematic, so remove the corresponding text and the table from the comment on the fsp_dxio_descriptor struct. Since there's no logical to physical lane number remapping needed for the lanes in the Phoenix DXIO descriptors, drop the 'logical' from the start_logical_lane and end_logical_lane fields in the DXIO descriptor and rename those to start_lane and end_lane. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I94664fd9d3807370b73f9fae8645d444e5faf7b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-17mb/google/myst: Update WWAN usb entryEric Lai
USB3 is used for both typeA and WWAN based on different DB. BUG=b:287159026 TEST=change FW config and check typeA and WWAN can work. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I5ad3973a9519350794a661ad00f71c0eb34edfba Reviewed-on: https://review.coreboot.org/c/coreboot/+/75819 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-16mb/google/myst: Add additional memory configurationsRob Barnes
Add additional ram parts and generate strapping ids. BUG=b:285216975 TEST=Build myst image Change-Id: I2b3b8c9ffcf81bbd2d6ecfad1b612fbf793857c8 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75821 Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-06-15mb/google/myst: Add PSP verstage callbacksKarthikeyan Ramasubramanian
Lay the groundwork to prepare for enabling PSP verstage. This change adds PSP verstage callback to enable eSPI, TPM etc. BUG=b:284984667 TEST=Build Myst BIOS image with PSP verstage enabled. Change-Id: Ifc800e8bb27cc4c3fbccc2ab9f51138a7c4b03a6 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75585 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-06-13mb/google/myst: Update PCIE_RST_L driveJon Murphy
PCIE_RST_L is attached to a pull down, change the init to NC. BUG=None TEST=Boot to OS Change-Id: I3f7a548a33eb18327139f033d7c0d6a1843f1639 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75700 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-13mb/google/myst: Update PCIe romstage gpiosJon Murphy
Update PCIe GPIOs during rom stage to properly initialize the PCIe devices and allow the NVMe/eMMC to be properly detected. BUG=b:284213391 TEST=Boot to OS Change-Id: I24ad6c1addedb414afade2512b6628022d000a47 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-06-09mb/google/myst: Add pen detect supportJon Murphy
Add pen detect support on the SOC pen detect GPIO. BUG=b:286296762 TEST=Verify pen detect works on Myst Change-Id: I922d643a83c5cd8ea0ab9fe6733f7aa05d935802 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-08mb/google/myst/bootblock.c: Initialize spi flashFred Reitberger
Initialize the SPI Flash in bootblock to ensure that CONFIG_SPI_FLASH_EXIT_4_BYTE_ADDR_MODE will exit 4-byte addressing mode. BUG=b:285110121 TEST=boot myst and verify flash operations work correctly Change-Id: Ia88d2b46884b096b4c558bc86513159ec6d35eb5 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75588 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07mb/google/myst: Correct CROS_WP_GPIO to active highEric Lai
HW has invert the signal, set it to active high. BUG=b:285964562 TEST=check crossystem wpsw_cur change as expected. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I54c578e5df5f1b24743cc9506e1e31b0b18bfb25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75628 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-06-07mb/google/myst: Enable USB WWANEric Lai
Add usb wwan device tree entry. Also set wwan_rst to high due to HW design active high. BUG=b:285792436 TEST=check FM101 is detected by Linux kernel. Bus 002 Device 002: ID 2cb7:01a2 Fibocom Wireless Inc. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I0aa60cb284d4b7f99e16643a92ee58467a355026 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75660 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07mb/google/myst: Enable fingerprint on UARTEric Lai
Add fingerprint into device tree. Also set RST to low per HW requirement. BUG=b:285799911 TEST=check ectool --name=cros_fp version. RO version: bloonchipper_v2.0.5938-197506c1 RO cros fwid: CROS_FWID_MISSING RW version: bloonchipper_v2.0.14348-e5fb0b9 RW cros fwid: bloonchipper_14931.0.0 Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I09819037b80e55edeb56faef9e27fe0753748efc Reviewed-on: https://review.coreboot.org/c/coreboot/+/75629 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-06soc/amd/phoenix: Update USB device aliasEric Lai
Follow 57263_FP8_MBDG_rev_0_92 Table.57 to update the alias. We can match the schematic for now. BUG=b:285793461 TEST=USB still works. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Id1058279fe5b0e3131608a0b9bbd708dbbde7e87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-06-04mb/google/myst: Add USB configJon Murphy
Add the phoenix usb config struct for Myst since the FSP has been updated to accept the config from coreboot and the default values do not work. BUG=None TEST=Boot to OS on Myst, verify devices are seen with lsusb Change-Id: I329aba80f3003a3a5f343b8dcc3efa8502b98e24 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-06-04mb/google/myst: Add PCIe shutdown workaroundJon Murphy
On Myst, the FSP is shutting down the PCIe lanes that the SSD is on. Enable hotplug to force the FSP to keep the lanes active. BUG=b:284213391 TEST=Boot to OS Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Iaf0aca329f05f15a3ce9edfa6a0e782c2edccabe Reviewed-on: https://review.coreboot.org/c/coreboot/+/75583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-06-04mb/google/myst: Enable S0ixJon Murphy
Enable s0ix on Myst. BUG=b:277215113 TEST=builds Change-Id: I3cabc2c3ba75f4490da18b861ef2b82ce240860d Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74279 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-01mb/google/myst: Add ELAN touch screenEric Lai
Follow the eKTH7B18U_Product_Spec_V1.1 to add the device. BUG=b:284381267 TEST=Check touch screen can detect in coreboot. [INFO ] \_SB.I2C1.H010: ELAN Touchscreen at I2C: 02:10 Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I4bd521410953892a477020a872de0d882001b178 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-06-01mb/google/myst: Add ELAN touch padEric Lai
Follow the data sheet SA577C-12C0, Rev. 1.1 to add the device. BUG=b:284381266 TEST=check touch pad can detect in coreboot. [INFO ] \_SB.I2C0.D015: ELAN Touchpad at I2C: 01:15 Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I0eb0ee1e6cb9c15bfe3964af6ce2ed02eee370a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-06-01mb/google/myst: Add codec RTL5682 and amp RTL1019Eric Lai
Follow the schematic_0502 to add the audio codec and amp. BUG=b:270109435 TEST=Check device can detect in coreboot. [INFO ] \_SB.I2C3.RT58: Realtek RT5682 at I2C: 04:1a [INFO ] \_SB.I2C3.D029: Realtek SPK AMP R at I2C: 04:29 [INFO ] \_SB.I2C3.D02A: Realtek SPK AMP L at I2C: 04:2a Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Icfec8d99be8fde986c5516e0c4cd50dae1edfa98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75477 Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-30mb/google/myst: Fix the DRAM Strap IDKarthikeyan Ramasubramanian
Incorrect memory part was used in CB:74745 to generate the DRAM Strap ID. Amend the memory_parts_used.txt and regenerate the DRAM Strap ID. BUG=b:272746814 TEST=Generate the DRAM Strap ID. Change-Id: I0668d7e02345610a11f9113d8bbe99a474f33f1a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-05-18Myst: Update Makefile to remove SPD injectionMartin Roth
The SPD format in the APCB has changed for Phoenix, and the injection tool 'apcbtool' needs to be updated to match. Until this happens, the APCB will be built containing the correct SPD. BUG=b:281983434 TEST=Build Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If575f98511c796e93c5a12cd450a3a7985e39806 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-05-15mb/google/myst: Re-organize the FMAP layoutKarthikeyan Ramasubramanian
By moving certain FW UI assets from RO to RW sections, 4 MiB is sufficient for RO section. Split the resultant available 4 MiB equally between 2 RW sections. This will help in getting to 16 MiB SPI flash for the mainboard. BUG=b:281567816 TEST=Build Myst BIOS image with the updated layout. Cq-Depend: chromium:4519688 Change-Id: I09948ceac0a6a1cb109322fc4856b8b486318664 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75184 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-05-14mb/google/myst/Kconfig: Select SPI_FLASH_EXIT_4_BYTE_ADDR_MODEFred Reitberger
When using a 32-MiB ROM chip, the ABL leaves the SPI flash in 4-byte addressing mode, so ensure the driver exits that mode for regular operation. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I9a846be743a65ffe5b3ef94e20e0b5fc5e273961 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-05-08mb/google/myst: Add selective FP initJon Murphy
Add FW_CONFIG item for FP sensor init and conditionally init the GPIOs based on whether we're using a SPI or UART FP sensor. BUG=b:276939271 TEST=builds Change-Id: I9815bd17df1d15f73529beb15d08cde1ef90efad Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-08mb/google/myst: Add eMMC/NVMe config supportJon Murphy
Add FW_CONFIG item for eMMC/NVMe support and address the init of the lanes based on said config. BUG=b:278877257 TEST=builds Change-Id: Id6452f497cf78549b7d6126f1b55cd6d45b403c3 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74957 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Mark Hasemeyer <markhas@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-05mb/google/myst: Add variant makefileJon Murphy
Add variant makefile to support including the memory folder for Myst. BUG=b:273383819 TEST=Builds in chromium with blobs Change-Id: I03b0cd91dd66f357b15522da36f5118867b6b14c Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74964 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-03Drop many cases of CONFIG_MAINBOARD_PART_NUMBERKyösti Mälkki
We have largely dropped from filling in mainboard_ops.name as unnecessary. A common place should be decided where or if this information is added in the console log. Change-Id: I917222922560c6273b4be91cd7d99ce2ff8e4231 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-02mb/google/myst: Inject SPD binaries to APCBKarthikeyan Ramasubramanian
Add rules to inject the variant specific SPD binaries into APCB. BUG=b:273383819 TEST=Build Myst BIOS image. Currently no APCB is present. So no SPD is injected into APCB. Change-Id: Ic511cdc4fe0989c9abc0cd0531cc0cae40f8dc34 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74746 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-05-02mb/google/myst: Add initial memory configurationKarthikeyan Ramasubramanian
Generate the RAM Strap IDs based on the initial memory configuration. BUG=b:272746814 TEST=Build Myst BIOS image. Change-Id: I8a4fe9a41f101ac10391756f1b815220c8b98612 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-04-26mb/google/myst: Enable tis_plat_irq_statusJon Murphy
This will fix: > [INFO ] Probing TPM I2C: tis_plat_irq_status() not implemented, wasting 20ms to wait on Cr50! BUG=b:277297687 TEST=builds Change-Id: I611a2855d94167748d0f82a478687fe2cdf5846a Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74286 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-26mb/google/myst: Configure WLANJon Murphy
Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used for WLAN. Mapping derived from myst schematic. BUG=b:275965982 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I5059be0bc011978e74ab4245e6ae037aa177ef9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-26mb/google/myst: Enable PCIe devices in devicetreeJon Murphy
Ensure that DXIO descriptors are updated using info from AMD and Myst board schematics. BUG=b:275960920,b:276744321 TEST=builds Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74112 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-24mb/google/myst: Set system type to laptopJon Murphy
BUG=b:277294070 TEST=None Change-Id: I0aa4e0bcfb06e5e5cb7e9d52f2d82b5818925267 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74284 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-24mb/google/myst: Store XHCI PCI resourcesJon Murphy
Implement `smm_mainboard_pci_resource_store_init` to store the resources for XHCI devices. These stored resources are later used by the elog code to log XHCI wake events. BUG=b:277273428 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I608d51f438681ac529323c23cc707845a3d609d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74281 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-24mb/google/myst: Enable gfx_hdaJon Murphy
Enable gfx_hda to allow for audio over hdmi. BUG=b:277219546 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I58096f1408f66f968af1494e487cf2bfc43b9a0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74278 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-24mb/google/myst: Enable crypto in devicetreeJon Murphy
Add the crypto device to the devicetree. BUG=b:277214359 TEST=builds Change-Id: I5394c5f9df64642d8633af84cf662652bd1a5cb2 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74275 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-21mb/google/myst: Expose SKU and board ID to Chrome OSJon Murphy
Select EC_GOOGLE_CHROMEEC_SKUID and EC_GOOGLE_CHROMEEC_BOARDID to provide common routine for reading skudid and boardid from Chrome EC. BUG=b:277293398 TEST=builds Change-Id: I8e42ba23dada9771f335df34275e44e51d645596 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74283 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-21mb/google/myst: Enable mp2 deviceJon Murphy
The mp2 PCI device is still present when no mp2 firmware is loaded. When this device isn't explicitly enabled in the mainboard's devicetree, the chipset devicetree default of the device being disabled is used. This results in coreboot's resource allocator not allocating resources to the device and since the bridge doesn't have enough MMIO space reserved, the Linux kernel can't assign resources to it. Enable the mp2 device in the mainboard's devicetree so that it gets its resources assigned by coreboot. BUG=b:277217097 TEST=builds Change-Id: I21885c51ff08846b456675090946f381843ef5e6 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74277 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-21mb/google/myst: Enable audio co-processor in devicetreeJon Murphy
Enable the audio co-processor in the device tree. BUG=b:277214614 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I1e1749359804960bbd75d869385b9071e7f33be7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74276 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-21mb/google/myst: Enable AP <-> GSC communicationJon Murphy
Configure GSC I2C and Interrupt GPIOs during the early initialization. Add devicetree configuration for GSC device and enable the required config items. BUG=b:275959717 TEST=builds Change-Id: I6e235356b252a7b68a42da128ffd3189a829f117 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74111 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-20mb/google/myst: Add eSPI configurationJon Murphy
Add eSPI configuration for myst. Ensure the additional windows are used and remove unnecessary addresses from the range used on skyrim. BUG=b:275953893 TEST=builds Change-Id: I7b40adec78d4e0b596596fa6e2951c79bd3bd8c7 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74110 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-19mb/google/myst: Add initial fch irq routingJon Murphy
Add initial fch irq routing table for Myst. BUG=b:275946702 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ic81c3cbfbb30a0beb3c4083624cf19abe6d1e694 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74109 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-13mb/google/myst: Disable keyboard reset pinJon Murphy
The keyboard reset is not being used on this board, so disable the functionality. BUG=b:277294460 TEST=None Change-Id: If7fb9ab0c9b1260d342313badb65c55bb9f788c0 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74285 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-13mb/google/myst: Add initial I2C configurationJon Murphy
Add I2C peripheral reset configuration required during early init. Enabled I2C generic and HID drivers. BUG=b:275939564 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I44668295fb6ed03992df9d9fc075792e181d1a8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/74108 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-13mb/google/myst: Enable elogJon Murphy
Enable ELOG for Myst. BUG=b:275938975 TEST=builds Change-Id: I214e2dbaa3bc40c3f4ca68c8ee4b1398446d7090 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74282 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-13mb/google/myst: Add ACPI configuration for USB portsJon Murphy
The USB port configuration was derived from the PPR and schematics. Primary functions are: 2 USB-C ports 1 USB SS+ type A port 2 Cameras (World/User facing) 1 Bluetooth transceiver 1 WWAN BUG=b:275905635 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Iecb256cad7b2daea1fddfc8323e88ff5c38d1e51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-13mb/google/myst: Enable XHCI controllersJon Murphy
Enable the XHCI controllers in the devicetree for myst project. BUG=b:275905635 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I05dc5bb157f0ef955e4b37e34d7b32678e42ebc8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-13mb/google/myst: Enable internal graphicsJon Murphy
Enable internal graphics on the phoenix soc for myst projects. BUG=b:275900162 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ia6ef1ca07b9af491c7d937be5cef4f051852e486 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74104 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-12mb/google/myst: Enable iommuJon Murphy
Enable iommu in devicetree for myst in order to allow kernel to load and initialize IOMMU. Bug=b:276805280 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I94e93afe775b070253464a9d187ad6c028d1b811 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-12mb/google/myst: Enable console UARTJon Murphy
Enable the console UART for myst devices. Bug=b:275900837 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I52c1b86c46907216d88f98917968b833af0d5d41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74103 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-04-12mb/google/myst: Add FW_CONFIGJon Murphy
Add initial FW_CONFIG for the myst program. BUG=b: TEST=builds Cq-Depend: chrome-internal:5674351 Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: If74c3649d4e8d174d9fe00a4b896c2351ee3ab19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-04-12mb/google/myst: Enable eSPI SCI eventsJon Murphy
Enable EC SCI events for eSPI. BUG=b:275894894 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I8fd858c484f6fcf952bcb4f756ba2e4728091d8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74101 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-04-11mb/google/myst: Add smihandlerJon Murphy
Add SMI handler code for Myst platform. BUG=b:275858191 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I92e5e6aef7ab0b84a96d976e29ebf96b56f6f1a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74100 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-04-11mb/google/myst: Enable chromeOS ECJon Murphy
BUG=b:270624655 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Id18a311097d575973087eb92fd446a5c511f570e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-11mb/google/myst: Enable variants for MystJon Murphy
BUG=b:270618107 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I688e9c2fdf203cecfd5f200dec6cde9dbc0a9aa7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-10mb/google/myst: Build for chromeOSJon Murphy
Adjust build configs to build Myst for chromeOS. BUG=b:270618097 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: If4b6917fe024067409bfbb3d2691c37759b5cace Reviewed-on: https://review.coreboot.org/c/coreboot/+/74097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-04-10mb/google/myst: Declare CrOS GPIOsJon Murphy
Declare CrOS GPIOs for Myst, add relevant defines needed by chromeOS for additional control GPIOs. BUG=b:270616013 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ie876883d6ee2e3bc6324c038cefee12d99702dc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74096 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-10mb/google/myst: First pass GPIO configuration for MystJon Murphy
Initial GPIO configuration for Myst. BUG=b:270596581 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ia019704c7b027f14d46281e0de0ffdbc4906a20b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74095 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-10mb/google/myst: Add stubs to configure GPIOsJon Murphy
Add configuration stubs for GPIOs to be implemented later. BUG=b:270596581 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I3228f857da7c8c76cf32faf4a23418aedaf40875 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74094 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-04-10mb/google/myst: Add new mainboardJon Murphy
Myst is a new Google mainboard with an AMD Phoenix SOC. BUG=b:270596106 TEST=util/abuild/abuild -t GOOGLE_MYST --clean Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Id7d731ce4d6cb6d4e9041f46eb5a799865bb0b9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/74093 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-05 01:10:05 +0000