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authorJon Murphy <jpmurphy@google.com>2023-03-29 19:07:06 -0600
committerFelix Held <felix-coreboot@felixheld.de>2023-04-26 12:14:54 +0000
commit0f1826e2518227eaff92f61bbe9800058fbde1be (patch)
treea20ab85913cc78dd13aaf0e609049ea0de4f8e38 /src/mainboard/google/myst
parent462ccbaac26b7ff271453287995bfbe6ff148b55 (diff)
mb/google/myst: Configure WLAN
Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used for WLAN. Mapping derived from myst schematic. BUG=b:275965982 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I5059be0bc011978e74ab4245e6ae037aa177ef9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/myst')
-rw-r--r--src/mainboard/google/myst/Kconfig1
-rw-r--r--src/mainboard/google/myst/bootblock.c3
-rw-r--r--src/mainboard/google/myst/romstage.c13
-rw-r--r--src/mainboard/google/myst/variants/baseboard/Makefile.inc2
-rw-r--r--src/mainboard/google/myst/variants/baseboard/devicetree.cb7
-rw-r--r--src/mainboard/google/myst/variants/baseboard/gpio.c34
-rw-r--r--src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h6
7 files changed, 64 insertions, 2 deletions
diff --git a/src/mainboard/google/myst/Kconfig b/src/mainboard/google/myst/Kconfig
index ce99f6b61d..ae54f9cedf 100644
--- a/src/mainboard/google/myst/Kconfig
+++ b/src/mainboard/google/myst/Kconfig
@@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS
select DISABLE_KEYBOARD_RESET_PIN
select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_HID
+ select DRIVERS_WIFI_GENERIC
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_ESPI
select EC_GOOGLE_CHROMEEC_SKUID
diff --git a/src/mainboard/google/myst/bootblock.c b/src/mainboard/google/myst/bootblock.c
index e9d69e32bc..440466697b 100644
--- a/src/mainboard/google/myst/bootblock.c
+++ b/src/mainboard/google/myst/bootblock.c
@@ -23,6 +23,9 @@ void bootblock_mainboard_early_init(void)
variant_tpm_gpio_table(&gpios, &num_gpios);
gpio_configure_pads(gpios, num_gpios);
+
+ variant_early_gpio_table(&gpios, &num_gpios);
+ gpio_configure_pads(gpios, num_gpios);
}
void bootblock_mainboard_init(void)
diff --git a/src/mainboard/google/myst/romstage.c b/src/mainboard/google/myst/romstage.c
new file mode 100644
index 0000000000..fc3402a3b6
--- /dev/null
+++ b/src/mainboard/google/myst/romstage.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <soc/platform_descriptors.h>
+
+void mb_pre_fspm(FSP_M_CONFIG *mcfg)
+{
+ size_t num_base_gpios;
+ const struct soc_amd_gpio *base_gpios;
+
+ baseboard_romstage_gpio_table(&base_gpios, &num_base_gpios);
+ gpio_configure_pads(base_gpios, num_base_gpios);
+}
diff --git a/src/mainboard/google/myst/variants/baseboard/Makefile.inc b/src/mainboard/google/myst/variants/baseboard/Makefile.inc
index ba096230cf..40a41dfeed 100644
--- a/src/mainboard/google/myst/variants/baseboard/Makefile.inc
+++ b/src/mainboard/google/myst/variants/baseboard/Makefile.inc
@@ -2,4 +2,6 @@ bootblock-y += gpio.c
ramstage-y += gpio.c
+romstage-y += gpio.c
+
smm-y += smihandler.c
diff --git a/src/mainboard/google/myst/variants/baseboard/devicetree.cb b/src/mainboard/google/myst/variants/baseboard/devicetree.cb
index ae5f3416a9..7adb365088 100644
--- a/src/mainboard/google/myst/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/myst/variants/baseboard/devicetree.cb
@@ -86,7 +86,12 @@ chip soc/amd/phoenix
device domain 0 on
device ref gpp_bridge_2_1 on end # WWAN
- device ref gpp_bridge_2_2 on end # WLAN
+ device ref gpp_bridge_2_2 on # WLAN
+ chip drivers/wifi/generic
+ register "wake" = "GEVENT_8"
+ device pci 00.0 on end
+ end
+ end
device ref gpp_bridge_2_3 on end # SD
device ref gpp_bridge_2_4 on end # NVMe
device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
diff --git a/src/mainboard/google/myst/variants/baseboard/gpio.c b/src/mainboard/google/myst/variants/baseboard/gpio.c
index 56b814309c..319635415d 100644
--- a/src/mainboard/google/myst/variants/baseboard/gpio.c
+++ b/src/mainboard/google/myst/variants/baseboard/gpio.c
@@ -179,7 +179,27 @@ static const struct soc_amd_gpio tpm_gpio_table[] = {
/* GPIO configuration in bootblock */
static const struct soc_amd_gpio bootblock_gpio_table[] = {
- /* TODO(b/275965982): Fill bootblock gpio configuration */
+ /* Enable WLAN */
+ /* WLAN_DISABLE */
+ PAD_GPO(GPIO_156, LOW),
+};
+
+/* Early GPIO configuration */
+static const struct soc_amd_gpio early_gpio_table[] = {
+ /* WLAN_AUX_RST_L (ACTIVE LOW) */
+ PAD_GPO(GPIO_38, LOW),
+ /* Power on WLAN */
+ /* EN_PP3300_WLAN */
+ PAD_GPO(GPIO_9, HIGH),
+};
+
+/* PCIE_RST needs to be brought high before FSP-M runs */
+static const struct soc_amd_gpio romstage_gpio_table[] = {
+ /* Deassert all AUX_RESET lines & PCIE_RST */
+ /* WLAN_AUX_RST_L (ACTIVE LOW) */
+ PAD_GPO(GPIO_38, HIGH),
+ /* PCIE_RST0_L */
+ PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH),
};
static const struct soc_amd_gpio espi_gpio_table[] = {
@@ -205,12 +225,24 @@ void baseboard_gpio_table(const struct soc_amd_gpio **gpio, size_t *size)
*gpio = base_gpio_table;
}
+__weak void baseboard_romstage_gpio_table(const struct soc_amd_gpio **gpio, size_t *size)
+{
+ *size = ARRAY_SIZE(romstage_gpio_table);
+ *gpio = romstage_gpio_table;
+}
+
__weak void variant_bootblock_gpio_table(const struct soc_amd_gpio **gpio, size_t *size)
{
*size = ARRAY_SIZE(bootblock_gpio_table);
*gpio = bootblock_gpio_table;
}
+__weak void variant_early_gpio_table(const struct soc_amd_gpio **gpio, size_t *size)
+{
+ *size = ARRAY_SIZE(early_gpio_table);
+ *gpio = early_gpio_table;
+}
+
void variant_espi_gpio_table(const struct soc_amd_gpio **gpio, size_t *size)
{
*size = ARRAY_SIZE(espi_gpio_table);
diff --git a/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h
index 6ce35bb445..a3fd355ef1 100644
--- a/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h
@@ -16,9 +16,15 @@
/* This function provides base GPIO configuration table. */
void baseboard_gpio_table(const struct soc_amd_gpio **gpio, size_t *size);
+/* This function provides GPIO settings in romstage. */
+void baseboard_romstage_gpio_table(const struct soc_amd_gpio **gpio, size_t *size);
+
/* This function provides GPIO init in bootblock. */
void variant_bootblock_gpio_table(const struct soc_amd_gpio **gpio, size_t *size);
+/* This function provides early GPIO init in early bootblock or psp. */
+void variant_early_gpio_table(const struct soc_amd_gpio **gpio, size_t *size);
+
/* This function provides GPIO settings for eSPI bus. */
void variant_espi_gpio_table(const struct soc_amd_gpio **gpio, size_t *size);