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| author | Felix Held <felix-coreboot@felixheld.de> | 2023-04-05 19:57:44 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-06-22 13:45:43 +0000 |
| commit | 4c548919c617d7a19482c23156a7546f0e18164f (patch) | |
| tree | 9488f0c0fe0afb10491d484c28cd70347e9459ef /src/mainboard/google/myst | |
| parent | 4eee50642ff5ac6e7d7830afd38693943fe17b5b (diff) | |
vc/amd/fps/phoenix/platform_descriptors: drop logical-physical mapping
For Phoenix the lane numbers in the DXIO descriptor match the ones in
the schematic, so remove the corresponding text and the table from the
comment on the fsp_dxio_descriptor struct. Since there's no logical to
physical lane number remapping needed for the lanes in the Phoenix DXIO
descriptors, drop the 'logical' from the start_logical_lane and
end_logical_lane fields in the DXIO descriptor and rename those to
start_lane and end_lane.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I94664fd9d3807370b73f9fae8645d444e5faf7b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/myst')
| -rw-r--r-- | src/mainboard/google/myst/port_descriptors.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/mainboard/google/myst/port_descriptors.c b/src/mainboard/google/myst/port_descriptors.c index 6d0d0d6ff9..2c9985c298 100644 --- a/src/mainboard/google/myst/port_descriptors.c +++ b/src/mainboard/google/myst/port_descriptors.c @@ -11,8 +11,8 @@ static fsp_dxio_descriptor myst_dxio_descriptors[] = { [DXIO_WWAN] = { .engine_type = UNUSED_ENGINE, .port_present = true, - .start_logical_lane = 13, - .end_logical_lane = 13, + .start_lane = 13, + .end_lane = 13, .device_number = PCI_SLOT(WWAN_DEVFN), .function_number = PCI_FUNC(WWAN_DEVFN), .link_speed_capability = GEN3, @@ -22,8 +22,8 @@ static fsp_dxio_descriptor myst_dxio_descriptors[] = { [DXIO_WLAN] = { .engine_type = PCIE_ENGINE, .port_present = true, - .start_logical_lane = 14, - .end_logical_lane = 14, + .start_lane = 14, + .end_lane = 14, .device_number = PCI_SLOT(WLAN_DEVFN), .function_number = PCI_FUNC(WLAN_DEVFN), .link_speed_capability = GEN3, @@ -33,8 +33,8 @@ static fsp_dxio_descriptor myst_dxio_descriptors[] = { [DXIO_SD] = { .engine_type = PCIE_ENGINE, .port_present = true, - .start_logical_lane = 15, - .end_logical_lane = 15, + .start_lane = 15, + .end_lane = 15, .device_number = PCI_SLOT(SD_DEVFN), .function_number = PCI_FUNC(SD_DEVFN), .link_speed_capability = GEN1, @@ -48,8 +48,8 @@ static fsp_dxio_descriptor myst_dxio_descriptors[] = { static const fsp_dxio_descriptor emmc_descriptor = { .engine_type = PCIE_ENGINE, .port_present = true, - .start_logical_lane = 16, - .end_logical_lane = 16, + .start_lane = 16, + .end_lane = 16, .device_number = PCI_SLOT(NVME_DEVFN), .function_number = PCI_FUNC(NVME_DEVFN), .link_speed_capability = GEN_MAX, @@ -60,8 +60,8 @@ static const fsp_dxio_descriptor emmc_descriptor = { static const fsp_dxio_descriptor nvme_descriptor = { .engine_type = PCIE_ENGINE, .port_present = true, - .start_logical_lane = 16, - .end_logical_lane = 19, + .start_lane = 16, + .end_lane = 19, .device_number = PCI_SLOT(NVME_DEVFN), .function_number = PCI_FUNC(NVME_DEVFN), .link_speed_capability = GEN_MAX, |