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path: root/src/mainboard/google/guybrush/Kconfig
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2022-09-30mb/google/guybrush: move EC switch selection from ChromeOS to VbootMatt DeVillier
This is a vboot feature, not a ChromeOS one, and unless selected by vboot, compilation will fail in the non-ChromeOS + vboot build case. TEST=build/boot guybrush w/vboot, w/o ChromeOS Change-Id: I3108bcc8dfeacd99c9f5d36bd915d590292fef00 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67994 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-01mb/google/guybrush: select SYSTEM_TYPE_LAPTOPMatt DeVillier
Select SYSTEM_TYPE_LAPTOP so the FADT PM profile is correctly set to mobile (vs the default of desktop). TEST=build/boot google/dewatt, run FWTS and verify FADT PM profile correct Change-Id: I480fbe85782e2c63efa8d2212d503a47d8149ab9 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-07-20mainboard/google/guybrush: Update Wake-On-LAN functionalityRobert Zieba
The generic wifi driver currently contains a lot of intel specific functionality that results in it not working properly on AMD platforms. This commit updates the base device tree to use the generic PCIe driver instead. BUG=none TEST=Ran on nipperkin device, dumped SSDT and checked wakeup sources Change-Id: Iafbc68c1ae33ccc260889f0b39fc5fe8a59d7aca Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65990 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-21tpm: Refactor TPM Kconfig dimensionsJes B. Klinke
Break TPM related Kconfig into the following dimensions: TPM transport support: config CRB_TPM config I2C_TPM config SPI_TPM config MEMORY_MAPPED_TPM (new) TPM brand, not defining any of these is valid, and result in "generic" support: config TPM_ATMEL (new) config TPM_GOOGLE (new) config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE) config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE) What protocol the TPM chip supports: config MAINBOARD_HAS_TPM1 config MAINBOARD_HAS_TPM2 What the user chooses to compile (restricted by the above): config NO_TPM config TPM1 config TPM2 The following Kconfigs will be replaced as indicated: config TPM_CR50 -> TPM_GOOGLE config MAINBOARD_HAS_CRB_TPM -> CRB_TPM config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE Signed-off-by: Jes B. Klinke <jbk@chromium.org> Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-21mb/google/dewatt: Set SPI speed to 100Mhz on board version 3Rob Barnes
After assessing the signal integrity, 100 MHz SPI fast speed can be enabled for SPI ROM. BUG=b:213403891 BRANCH=guybrush TEST=Build and boot to OS in Dewatt board version 3. Change-Id: If0318abf1fed9b1f4ba876f736fdbf92c1ea6933 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63747 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-20Revert "mb/google/guybrush/var/dewatt: Override SPI fast speed"Rob Barnes
This reverts commit d80d88c0fec96b2fff93db87d0c83f4c6754ae7a. Reason for revert: 100Mhz should only be enabled on DeWatt on board version >=3. Enabling it on board version 2 will cause failures. BUG=b:213403891 BRANCH=guybrush TEST=Build dewatt Change-Id: I0b6acd2cda2af35ff33e89e3b339731e35d72cb1 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63746 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-20ChromeEC boards: Drop `IGNORE_IASL_MISSING_DEPENDENCY`Angel Pons
This should no longer be needed because the ASL has been fixed. Change-Id: I4d1500217bef54fa3d2be397e5e2a155da3f965d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-20mb/google/guybrush/var/dewatt: Override SPI fast speedKenneth Chan
After assessing the signal integrity, 100 MHz SPI fast speed can be enabled for SPI ROM. BUG=b:213403891 TEST=Build and boot to OS in Dewatt board version 2. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I7301d873e36bec4ee46c9d18293f924500ea9aba Reviewed-on: https://review.coreboot.org/c/coreboot/+/63685 Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-10mb/google/guybrush: Enable DEBUG_SMI for non-serial firmwareRaul E Rangel
In order to copy the PSP verstage logs into x86 cbmem, we need to enable DEBUG_SMI. This will include the CBMEM console code in SMM. I only enable DEBUG_SMI when UART is disabled because SMM doesn't currently save/restore the UART registers. This will result in clearing the interrupt enable bits and makes it so you can no longer use the TTY. BUG=b:221231786, b:217968734 BRANCH=guybrush TEST=Build serial and non serial firmware and verify DEBUG_SMI is set correctly. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I85a7933e8eb49ff920d00e43a494aaeab555ef3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-25mb/google/guybrush: enable coreboot to request spl fuseJason Glenesk
Enable guybrush based platforms to send fuse spl command to PSP when required. BUG=b:180701885 TEST=On a platform that supports SPL fusing. Confirm that PSP indicates fusing is required, and confirm coreboot sends command. Fusing is required when the image is built with an SPL table requiring newer minimum versions. A message indicating fusing was requested will appear in the serial log. "PSP: Fuse SPL requested" Change-Id: I7bce01513af4e613f546e491d9577c92f50cb85c Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-02-17mb/google/guybrush: Enable SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSPJan Dabros
Guybrush platforms have I2C3 controller which is shared between PSP and X86. In order to enable cooperation, PSP acts as an arbitrator. Enable SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP, so that proper driver is binded on the OS side. With this change in place it is important to use correct kernel version which has I2C-amdpsp driver [1] enabled. Otherwise, we won't have I2C3 available and thus TPM device available in OS, what may end up as a serious error - guybrush refuses to boot without access to TPM. BUG=b:204508404 BRANCH=guybrush TEST=Build proper kernel and firmware. Run on guybrush and verify TPM functionality. [1]: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=78d5e9e299e31bc2deaaa94a45bf8ea024f27e8c Signed-off-by: Jan Dabros <jsd@semihalf.com> Change-Id: I9dd94e47e1a02e790427b67adff84de3eb3ee387 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61965 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-15mb/google/guybrush: Add a mainboard specific SPL tableZheng Bao
Chromebook needs to do some additional check, which is not available in the AMD's PI released SPL table. BUG=b:216096562 Change-Id: Ib8074641b9fc9b38239a6e3837b8569e14af3342 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-08mb/google/guybrush: Enable CONSOLE_CBMEM_DUMP_TO_UARTRaul E Rangel
This will make debugging boot failures with a non-serial firmware easier. If we encounter an error that requires a reboot, this will dump the entire CBMEM contents onto the UART. This is especially helpful during S0i3 resume because the PSP verstage console logs are not exposed anywhere. BUG=b:215599230 TEST=Cause verstage error in S0i3 with non-serial firmware and see that the verstage logs were dumped to the UART before rebooting. Entering PSP verstage S0i3 resume tpm_setup failed rv:1 VB2:vb2api_fail() Need recovery, reason: 0x3f / 0xcc Saving nvdata Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I908037527206cc7bed2302fab60b2912d6dabc73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-02mb/google/guybrush: Enable PSP port 80sRaul E Rangel
Let's re-enable PSP post codes when running PSP verstage. The original reason we disabled POST codes was that it was causing problems during eSPI init in bootblock. Since we now init eSPI in PSP verstage, it's safe to re-enable them. We can now see post codes during S0i3 enter and exit. This will help when debugging resume or suspend hangs. Port 80 writes on suspend: ef000020 ef00ed00 ef00ed01 ef000021 <--new Port 80 writes on resume: 05 eea80025 eea90000 eea90100 eea90200 eea50000 eeae0000 eeae0004 eeaf0000 eeb00000 eec00000 eec00100 eec10000 eec40000 eec40500 eec40200 eefc0000 eefc0100 eec50000 ea00e0fc ea00abc1 ea00e60b ea00e60c ea00abe1 ea00abe2 ea00abe4 ea00abe5 ea00abeb ea00abec ea00abed ea00abee ea00abef ea00e10f ea00e098 ea00e099 ea00abf0 ea00abf2 ea00e10e ea00e60c ea00e101 ea00e090 ea00e091 ea00e098 ea00e099 ea00e098 ea00e099 ea00e100 ea00e60c ea00e0b0 ea00e0b4 ea00e0b7 ea00e60c ea00e0c2 ea00e0c4 ea00e0d3 ea00e60c ea00e10d ea00e0c1 ea00e10c ea00e60c ea00e0c4 e000 eec60000 eec20000 eec20800 b40000 eeb50000 eefc0000 eefc0300 ee070000 eed90000 eed90700 eeda0600 eedd0000 eecb0000 eecf0000 eecf0200 eee30000 eee30900 eee40000 ef000025 BUG=b:215425753 TEST=Boot/suspend/resume guybrush and verify post codes are printed Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie759f66be2b8ffac19145491a227752d4762a5b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-01-31mb/**/Kconfig: Properly override `IGNORE_IASL_MISSING_DEPENDENCY`Angel Pons
Don't unconditionally override `IGNORE_IASL_MISSING_DEPENDENCY`. Change-Id: I02081d0f04be4af9cd765aa3b29295af40f9ca99 Fixes: commit 28fa297901ffd158631cfc9f562f38119eff628e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-01-28IASL: Ignore IASL's "Missing dependency" warningElyes HAOUAS
IASL compiler check for usage of _CRS, _DIS, _PRS, and _SRS objects: 1) If _PRS is present, must have _CRS and _SRS 2) If _SRS is present, must have _PRS (_PRS requires _CRS and _SRS) 3) If _DIS is present, must have _SRS (_SRS requires _PRS, _PRS requires _CRS and _SRS) 4) If _SRS is present, probably should have a _DIS (Remark only) IASL will issue a warning for each missing dependency. Ignore this warnings for existing ASL code and issue a message when the build is complete. Change-Id: I28b437194f08232727623009372327fec15215dd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-12-20mb/google/guybrush: Enable PSP_S0I3_RESUME_VERSTAGERob Barnes
Enable PSP_S0I3_RESUME_VERSTAGE for all guybrush based boards. This will cause verstage to run during s0i3 resume. The TPM will be reinitialized in verstage during s0i3 resume. This is necessary on guybrush boards because the TPM_RST_L pin is asserted by the SOC in S0i3. BUG=b:200578885 BRANCH=None TEST=TPM initialized after s0i3 Change-Id: I9d64fe92ffc67a421be6d5e013e636332ce86dd5 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-09mb/google/guybrush/var/nipperkin: Override SPI fast speedKarthikeyan Ramasubramanian
After assessing the signal integrity, 100 MHz SPI fast speed can be enabled for SPI ROM. BUG=None TEST=Build and boot to OS in Nipperkin board version 2. Perform 250 iterations of warm and cold reset each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Id973acb939b69e0beda26252e57a278892f2f57d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-10-14mb/google/guybrush: Disable HAVE_ACPI_RESUME / S3Rob Barnes
S3 is not currently functional on Guybrush. Remove support from ACPI. BUG=b:202401767 b:181766974 TEST=Boot Guybrush Confirm 'deep' is not in /sys/power/mem_sleep Confirm S0ix suspend/resume still works BRANCH=None Change-Id: I9ed3e051f7f2e411670649ac2528a6f40229bdc6 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-13mb/google/guybrush: Re-arrange override speed configKarthikeyan Ramasubramanian
Currently override speed config is applied only for non EM100 cases. For EM100 case, override speed board version defaults to 0 leading to "comparison of unsigned expression >= 0 is always true" error. Fix this error by defining the override speed config for both EM100 and non-EM100 use-cases. BUG=None TEST=Build Guybrush for both EM100 and non-EM100 cases. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Id8ee7b01c69c4555d6e6a7b0d5f095ea3aaf3405 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58309 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-13mb/google/guybrush: Override SPI Fast speedsKarthikeyan Ramasubramanian
Add support to override SPI fast speeds based on board version from both bootblock and verstage. Overrides apply for Guybrush only and SPI speed is overridden from 66 MHz to 100 MHz starting board version 4. This will help to improve the boot time on board version by ~60 ms and still allow the old boards to boot with 66 MHz. BUG=b:199779306 TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm reset and suspend/resume cycles for 50 iterations each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I5bf03ab8772f27aca346589e9c5662caf014d0d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-29mb/google/guybrush/var/nipperkin: Add ALC5682I and MAX98360 supportPatrick Huang
Add ID "10029836" for machine driver, "RTL5682" for ALC5682I and "MX98357A" for MAX98360. BUG=b:198716348 TEST=Build nipperkin, codec is functional with new machine driver. Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Change-Id: Iab9d11adb7cd08effa2a9b6a627832bd89cb3cb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-28mb/(amd,google): Update SPI Kconfig settings based on devicetreeMartin Roth
This takes the devicetree SPI settings and moves them into Kconfig. BUG=b:195943311 TEST=boot guybrush & majolica and verify spi settings. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Icce1d57761465ae8255e5d9ce8679f3fdcb0ceed Reviewed-on: https://review.coreboot.org/c/coreboot/+/56885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-26mb/google/guybrush: Create dewatt variantBhanu Prakash Maiya
Create the dewatt variant of the guybrush reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:196460993 BRANCH=None TEST=util/abuild/abuild -p none -t google/guybrush -x -a make sure the build includes GOOGLE_DEWATT Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Change-Id: I57860a7cad1bf202bd3ef3eed5f498fbf1d29af8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57108 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-23mb/google/guybrush: Enable PCIe L1 SubstatesMatt Papageorge
This change enables L1.1 and L1.2 on all real Guybrush PCIe devices. BUG=b:188123142 TEST=Boot to ChromeOS and verify L1SS are functional by dumping the settings with "lspci -vv". Leave system on for 20 minutes and no hang. Also perform 20 reboots and suspend operations Cq-Depend: chrome-internal:4012927 Change-Id: I40d19be78bfcb9a30fb59f48530a4413dadbefbc Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-13mb/google/guybrush: Create nipperkin variantKarthikeyan Ramasubramanian
Create the nipperkin variant of the guybrush reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=None BRANCH=None TEST=util/abuild/abuild -p none -t google/guybrush -x -a make sure the build includes GOOGLE_NIPPERKIN Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ie525ea501e6c3d5d94e67c1db1d4e307fb7ccba7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56921 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `VARIANT_DIR` onceAngel Pons
Specify the type of the `VARIANT_DIR` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: Iea2f992a59e41e00fec3cdc9d6a13b5f3ab0a437 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56558 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `FMDFILE` onceAngel Pons
Specify the type of the `FMDFILE` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I810bd3fe8d42102586db6c2c58b7037a60189257 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56557 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `OVERRIDE_DEVICETREE` onceAngel Pons
Specify the type of the `OVERRIDE_DEVICETREE` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I4cbf4e318a30f0cf75aa8690e7454b9caa115c9d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56556 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `DEVICETREE` onceAngel Pons
Specify the type of the `DEVICETREE` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: If68f11a5ceaa67a3e8218f89e1138c247ebb9a25 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56555 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `MAINBOARD_PART_NUMBER` onceAngel Pons
Specify the type of the `MAINBOARD_PART_NUMBER` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I3692f9e82fe90af4d0da1d037018a20aa1b45793 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56554 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `MAINBOARD_DIR` onceAngel Pons
Specify the type of the `MAINBOARD_DIR` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: If1cc538b0c4938dac193699897b690e402b3c1e8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56553 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15mb/google/guybrush: Make VBOOT_STARTS_BEFORE_BOOTBLOCK a defaultMartin Roth
To be able to enable & disable PSP_verstage in the saved .config file, the symbol VBOOT_STARTS_BEFORE_BOOTBLOCK needs to be changed from a select to a default with a prompt. BUG=182477057 TEST=Build, get PSP_verstage, disable VBOOT_STARTS_BEFORE_BOOTBLOCK, verify that VBOOT_STARTS_IN_BOOTBLOCK is set. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Iba735f33f9b079c9868ef2fff099c5298ff72b6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56289 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12mb/google/guybrush: enable psp_verstage by defaultKangheui Won
Select VBOOT_STARTS_BEFORE_BOOTBLOCK to turn on psp_verstage by default. BUG=b:182477057 TEST=boot guybrush Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I08befb93213aeb67e6a1e5fa91273ae61025707e Reviewed-on: https://review.coreboot.org/c/coreboot/+/55832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-29mb/google/guybrush: provide full range backlight settings to kernelPratik Vishwakarma
Utilize the SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF option to provide full range backlight settings to the kernel. BUG=b:190443612 Change-Id: If071b701c383e3a6b78bf45a562f5a9b31397835 Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-23mb/google/guybrush: Add guybrush specific AMDFW config fileMartin Roth
This takes the "generic" AMD firmware config file from the cezanne directory and removes pieces unnecessary for guybrush. Removed: - PSPTRUSTLETS_FILE TypeId0x0C_FtpmDrv_CZN.csbin - PSP_MP2FW0_FILE TypeId0x25_Mp2Fw_CZN.sbin - PSP_KVM_ENGINE_DUMMY_FILE TypeId0x29_KvmEngineDummy.csbin - DRTMTA_FILE TypeId0x47_DrtmTA_CZN.sbin - PSP_MP2CFG_FILE MP2FWConfig.sbin BUG=b:187103438 TEST=Build & Boot Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I5a0ed1edd7616a890f906b7f3e4a7d364758ca47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-22mb/google/guybrush: Only enable early port80s if using psp_verstageMartin Roth
PSP_Verstage will enable eSPI early in the boot sequence. If the platform isn't using psp_verstage, the system can hang on the first port 80h postcode that comes out because they aren't routed to an active device until eSPI is configured. BUG=b:191370340 TEST=Build without PSP_Verstage, verify system doesn't hang. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I37fbb251cd79609b856c4480ca29ce94b08897d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55738 Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17mb/google/guybrush: Add helpers for cbi fw_config settingsMartin Roth
Turn on CBI and add helper functions for determining the board configuration from the firmware config settings in CBI. BUG=b:187316460 TEST=Built Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I212e7f413b4d8a7d15122cde90100a0ec28e88a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54639 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-08mb/google/guybrush: Enable RTD3 support for NVMeRaul E Rangel
This will tell the kernel to ignore PCI ASPM when suspending the device and instead place the device into D3. We don't actually have a pin to control power to the NVMe so we leave it in D3Hot. I'm not sure if `PCI_RST#` is working correctly on S0i3 suspend/resume. If it's not acting as expected we can add the reset GPIO and have the OS do it. BUG=b:184617186 TEST=Run suspend_stress_test on guybrush for 10 cycles Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I29539ac120a9f1b7c1bfeaca745cfc82acfa461a Reviewed-on: https://review.coreboot.org/c/coreboot/+/54967 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-21mb/google/guybrush: Enable some PCIe power saving featuresMatt Papageorge
Enable ASPM, Common Clock and Clock Power Managment. Accomplish this by adding the options in the platform Kconfig as well as dxio descriptors. BUG=b:187743927 TEST=Boot to ChromeOS and see ASPM, CC and Clock PM enabled with lspci Change-Id: Iefc4b5b489cb8caf59f21dd4333d7af66ba47c32 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54282 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20mb/google/guybrush: Add SoC thermal zoneRaul E Rangel
The time constant values were taken from the zork thermal.asl. BUG=b:186166365 TEST=Boot guybrush to OS and verify logs look correct thermal-0294 thermal_trips_update : Found critical threshold [3641] thermal-0321 thermal_trips_update : No hot threshold thermal-0200 thermal_get_temperatur: Temperature is 3060 dK thermal-0219 thermal_get_polling_fr: Polling frequency is 100 dS thermal-0200 thermal_get_temperatur: Temperature is 3060 dK thermal LNXTHERM:00: registered as thermal_zone0 ACPI: Thermal Zone [TM00] (33 C) thermal-0200 thermal_get_temperatur: Temperature is 3070 dK Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iaeed75bdaa16b117d0fa7144ede98db1388f74f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-14mb/google/guybrush,mancomb: select GOOGLE_SMBIOS_MAINBOARD_VERSIONIvy Jian
Select GOOGLE_SMBIOS_MAINBOARD_VERSION allows querying board revision from the EC. BUG=b:187904819 TEST=1. emerge-guybrush coreboot chromeos-bootimage 2. flash the image to the device and check board rev by using command `dmidecode -t 1 | grep Version` Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I48dc83d85cfc49e2e4155e389814fce08693c4bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/54084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-05-12mb/google/guybrush: Configure wake resource for WiFiKarthikeyan Ramasubramanian
In order to support wake on WLAN events, configure the wake resource. BUG=b:186011392 TEST=Build and boot to OS in guybrush. Ensure that WiFi power resource is added to SSDT. Device (\_SB.PCI0.GP20.WF00) { Name (_UID, 0x38B82CBC) // _UID: Unique ID Name (_DDN, "WIFI Device") // _DDN: DOS Device Name Name (_ADR, 0x0000000000000000) // _ADR: Address } Scope (\_SB.PCI0.GP20.WF00) { Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x08, 0x03 }) } Change-Id: Ic238d9606aea20c058e9b47093693f10b14e6288 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2021-05-05mb/google/guybrush: Configure Pen Detect deviceKarthikeyan Ramasubramanian
Pen Detect GPIO is exported through GPIO keys driver to the kernel so that stylus tools is popped on pen eject event. Hence enable the GPIO keys driver and configure the devicetree. BUG=b:186011392 TEST=Build and boot to OS in guybrush. Ensure that PRP0001 device is added to the ACPI SSDT table. Ensure that the Pen Eject events are detected. Event: time 1620159356.243180, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1 Event: time 1620159356.243180, -------------- SYN_REPORT ------------ Event: time 1620159356.735316, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0 Ensure that when the device is suspended, it wake on Pen Eject event and does not wake on Pen Insert event. Change-Id: I4d2aa29c0f1839c563b40734527a687a5618ba5c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-30mb/google/guybrush: Remove the GPIO_SIGN_OF_LIFE codeMartin Roth
Guybrush is pretty definitely alive, so this can be removed, as the TODO line said. BUG=180721202 TEST=Build Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I14f89f3e6f780c2da2136a838950ef2bcebc4c3a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-22guybrush: Add Kconfig for PSP eSPI and port80Rob Barnes
Add PSP_DISABLE_POSTCODES and PSP_POSTCODES_ON_ESPI kconfig options for cezanne. Select PSP_DISABLE_DISABLE_POSTCODES and unselect PSP_POSTCODES_ON_ESPI for guybrush. Port80 codes from PSP can cause bus errors on guybrush. BUG=b:185514903, b:184356693 TEST=Boot guybrush, observe no port80 codes from PSP Change-Id: I7241e47ec1b89782e699135370c796eb251afcaa Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52401 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-19Revert "mb/google/guybrush: Enable early EC Software Sync"Karthikeyan Ramasubramanian
This reverts commit 1e36dc078e4012f884d67a32f1faac5f80406285. With EFS2 already enabled in EC, enabling early EC sync is not required. Also a workaround has been added in payload to address any boot issues. BUG=b:185277224 TEST=Build and boot to OS in Guybrush in both normal and recovery mode. Cq-Depend: chromium:2832032 Change-Id: I921dc5c814e5187dce283eeff43075b59885723a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52418 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18mb/google/guybrush: Enable AMD I2S Machine DriverKarthikeyan Ramasubramanian
Enable AMD I2S machine driver and configure the devicetree with HID information so that the machine driver ACPI objects can be passed to the kernel. BUG=b:182960979 TEST=Build and boot to OS in guybrush. Ensure that the ACPI objects for machine driver is populated. Change-Id: I8ed474d25273082d1e0742ba93746d97930deb19 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-18mb/google/guybrush/var/guybrush: Add FPMCU configrationIvy Jian
Enable CRFP in devicetree and configure GPIOs. BUG=b:182201937 BRANCH=None TEST=Boot into OS and confirm FPMCU is responding. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I7c56b0db193be6804d07c2f333445c2a1dbf9f59 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-16mb/google/{guybrush,mancomb}: Add VBOOT_VBNV_OFFSETRaul E Rangel
This is the same as zork. BUG=b:184126844 TEST=Boot guybrush in developer mode and switch to normal mode. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib11c255ab7e937de334ecd18dc030006f7724275 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-16mb/google/guybrush: Sort VBOOT_EARLY_EC_SYNCRaul E Rangel
BUG=none TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I658372d082a8276f15c7165fe4104de4613fe7d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-02mb/google/guybrush: Enable early EC Software SyncKarthikeyan Ramasubramanian
BUG=None TEST=Build and boot to OS in Guybrush. Ensure that the EC Software Sync is complete. Change-Id: Id8655b6f805e14ce3cb71777c1cc175f45841fcc Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-31mb/google/guybrush: Enable VBOOT_LID_SWITCHRaul E Rangel
Needed so get_lid_switch will actually call the EC. Otherwise it returns -1. BUG=b:183524609 TEST=Depthcharge no longer halts complaining that coreboot didn't sample the pin Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4639b3713d726192e251dcffa14381dd92518fa2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-29mb/google/guybrush: select DISABLE_KEYBOARD_RESET_PINFelix Held
Now that we have the DISABLE_KEYBOARD_RESET_PIN Kconfig option, select it and remove the temporary workaround that was implemented in the mainboard code in commit 39ef89033624a2d14b0c77cdbdf287dd7d7059e1. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I634d11290dad8c93f10979f06243b1bf84737ae2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-29mb/google/guybrush: Enable DISABLE_SPI_FLASH_ROM_SHARINGRaul E Rangel
Guybrush uses GPIO67 as an input. BUG=none TEST=Boot guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I10068bb6870b2cb96033cf3893cde71db5c1d709 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51781 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22mb/google/guybrush: Enable AP <-> H1 communicationKarthikeyan Ramasubramanian
Configure H1 I2C and Interrupt GPIOs during the early initialization. Add devicetree configuration for H1 device and enable the required config items. BUG=b:180528902 TEST=Build Guybrush mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I040a5e6101bab0c7425d7b6cc6fbed3b479a5a44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-22mb/google/guybrush: Add initial I2C configurationKarthikeyan Ramasubramanian
Add I2C peripheral reset configuration required during early init. Enabled I2C generic and HID drivers. I2C GPIOs are configured as required in CB:50091. BUG=b:180531661 TEST=Build guybrush mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I67690fbd25639879a730260aaca4cddb5e47bbc7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-14mb/google/guybrush: Add SPDs into buildMartin Roth
This enables the standard library method of adding SPDs to CBFS. BUG=b:178715165 TEST=Build Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I2ec94fd866409e1dfa5cb65f6960ea07cbe22f2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51022 Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-14mb/google/guybrush: Enable EM100 support on guybrushMathew King
Add the option to build guybrush firmware with support for EM100. This will assist in bringup of the new board. BUG=b:180723776 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I2246d2952f341cd8fff8fd486cf989cdb7929411 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51071 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13mb/amd/majolica,google/guybrush,google/mancomb: select HAVE_ACPI_RESUMERaul E Rangel
Since not all mainboards based on the Cezanne SoC have to support ACPI resume, select this option in the mainboard's Kconfig and not in the SoC's Kconfig. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I988276ccb5b61837d7f3f015d1d1aba783324b02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-11mb/google/guybrush: Enable Chrome EC SKUID and BOARDIDMathew King
BUG=b:181910592 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I7851d3b11ea3b026b999019d02df1144f8393753 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-11mb/google/guybrush: Log mainboard events to elogMathew King
BUG=b:180653357 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Ifd43d9cc1832d8ed8d90c68ba88b5667e3c04f89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-10mb/google/guybrush: Enable Chrome ECMathew King
BUG=b:180507937 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I3cdd6422b1bc53ea934346327359cbc6d86baeeb Reviewed-on: https://review.coreboot.org/c/coreboot/+/51043 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-02mb/google/guybrush: Set up FW_CONFIG fieldsMathew King
BUG=b:180523962 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Ic8f30f6d7c4781d4e8451546b39395a74393608f Reviewed-on: https://review.coreboot.org/c/coreboot/+/50882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-02mb/google/guybrush: Add eSPI configurationMathew King
BUG=b:180507937 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Ic607d6bca5c70255332a6fbee2b63e6daba7d1e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51047 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-02mb/google/guybrush: Add option to toggle GPIO for sign of lifeMathew King
Enabling the GPIO_SIGN_OF_LIFE option will allow for early boot testing. BUG=b:180721202 TEST=builds Change-Id: I069623ae76a4e4d1e43a47dd95fdfcece398ebfb Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-22mb/google/guybrush: Enable console UARTMathew King
BUG=b:180530492 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I468d76d0e061431bc819ec12978203614bfe72b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50919 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22mb/google/guybrush: Enable guybrush variantMathew King
Enable the building of guybrush variants and configure the first variant also called guybrush. BUG=b:180419462 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I3bed620378f9152277b4943ead1017f61a21ea82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50845 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19mb/google/guybrush: Enable CONFIG_CHROMEOSMathew King
BUG=b:175143925 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I8d038126b3e511bd16df2144652992c2d5b56c87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50507 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-23mb/google/guybrush: Set FWM position to an upper addressZheng Bao
Setting other places causes build error. BUG=b:178241112 TEST=Build Change-Id: I85d5d44c458feed38d69f21f899d6b4380963ec7 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-22mb/google/guybrush: Set the ROMSIZE as 16MZheng Bao
Change-Id: Iec8b40bd89c25cd2193aff8af45d0a09b07ad6a3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49797 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21mb/google/guybrush: Add default FMD file to the buildMathew King
BUG=b:175143925 TEST=builds; binary has correct layout Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I4f3826c8ed0dfd7219eaa5f0cc285f1fe89a4e1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/49491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-12-17mb/google/guybrush: Add new mainboardMathew King
Guybrush is a new Google mainboard with an AMD SOC. BUG=b:175143925 TEST=builds Change-Id: I1792f21ff7616f364ddc8b0c04481049b2a5fb04 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48479 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 16:47:36 +0000