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authorZheng Bao <fishbaozi@gmail.com>2022-02-15 00:38:54 +0800
committerFelix Held <felix-coreboot@felixheld.de>2022-02-15 17:14:35 +0000
commitb09166d0e62ba8ebe0c27bb7b1e20cac4885aa08 (patch)
treecd84fb70aa23aed2dae82431e474d29e0ee59743 /src/mainboard/google/guybrush/Kconfig
parent6c5efcd26856aef56dd88c231b6e9dc453e80f71 (diff)
mb/google/guybrush: Add a mainboard specific SPL table
Chromebook needs to do some additional check, which is not available in the AMD's PI released SPL table. BUG=b:216096562 Change-Id: Ib8074641b9fc9b38239a6e3837b8569e14af3342 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/google/guybrush/Kconfig')
-rw-r--r--src/mainboard/google/guybrush/Kconfig9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig
index b2fce84c85..a0040bf51b 100644
--- a/src/mainboard/google/guybrush/Kconfig
+++ b/src/mainboard/google/guybrush/Kconfig
@@ -99,6 +99,15 @@ config AMDFW_CONFIG_FILE
string
default "src/mainboard/google/guybrush/variants/baseboard/amdfw.cfg"
+config HAVE_SPL_FILE
+ bool
+ default y
+
+config SPL_TABLE_FILE
+ string
+ depends on HAVE_SPL_FILE
+ default "3rdparty/blobs/mainboard/google/guybrush/TypeId0x55_SplTable_Prod_CZN_Chrome.sbin"
+
if !EM100 # EM100 defaults in soc/amd/common/blocks/spi/Kconfig
config EFS_SPI_READ_MODE
default 4 # Dual IO (1-2-2)