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2021-09-13mb/google/dedede/var/bugzzy: Generate SPD ID for K4U6E3S4AA-MGCRSeunghwan Kim
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: 1. K4U6E3S4AA-MGCR (Samsung) BUG=b:192521391 BRANCH=dedede TEST=Build and boot bugzzy board Change-Id: Ic0b02559c671845a73a71bd57cd7237850c76645 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-09mb/google/dedede/var/gooey: Add fw_config probe for ALC5682-VD & VSStanley Wu
ALC5682-VD/ALC5682-VS load different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. Define SSFC bit 9-11 in coreboot for codec within ec. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:193694180 TEST=ALC5682-VD/ALC5682-VS audio codec can work Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: Ib458cf47909a2d7a65f086c5f30f85a16f78d589 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-08mb/google/dedede/var/magolor: Generate SPD ID for supported partTyler Wang
Add supported memory parts in mem_parts_used.txt, and generate SPD id for this part. MT53E512M32D1NP-046 WT:B BUG=b:199032134 TEST=emerge-dedede coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Ic9ccee7c0957119a69ee179854cf13d30db40621 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-08mb/google/dedede/var/cret: Update DPTF parametersDtrain Hsu
Update DPTF parameters from internal thermal team and Intel suggestion. BUG=b:198249129 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I25d3909144d6e38d7a6eb859d33585c319a84b04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-08mb/google/dedede/var/cappy2: Add fw_config probe for ALC5682I-VSSunwei Li
Based on commit b9c22e09 (util/sconfig: Compare probe conditions for override device match), add fw_config probe for ALC5682I-VS headphone Audio Codec. BUG=b:197546020 BRANCH=dedede TEST=ALC5682I-VD/VS and CS42l42 work normally according fw_config Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: Iac09663b095e758f1bc0cfaf7adb6e84d203788a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57105 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Henry Sun <henrysun@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-07mb/google: Add board name comments for each boardMartin Roth
Roughly half the boards had a "title" comment for the board. This adds it for the rest of the boards to make everything consistent. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ib941318842136212727f56fc6130381c5c9cd55b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-05mb/google/dedede/var/gooey: Configure I2C times for I2C devicesstanley.wu
Configure I2C high / low time in device tree to ensure I2C CLK runs under I2C_SPEED_FAST (400 kHz). Measured I2C frequency just as below after tuning: Touchpad: 386.7kHz Touchscreen: 387.4kHz Audio: 385.7kHz P-sensor: 378.1kHz BaUG=b:197247706 BRANCH=dedede TEST=Build and check I2C clock is under 400kHz Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: Ic5d5660181f36f161ae04cbf5003f6d7ad4bc16f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-05mb/google/dedede/var/gooey: Add MT53E512M32D1NP-046 as supported mem moduleStanley Wu
Add MT53E512M32D1NP-046 WT:B supported memory part in the mem_parts_used.txt and generate the SPD ID for the part. Manufacturer is Micron, and the memory part is 1anm Tech, difference to 1xnm Tech on MT53E512M32D2NP-046. BUG=b:194223174 BRANCH=dedede TEST=Build the gooey board. Change-Id: I7b83126a2bf98bb9d0ca05d397c288e0d99ed781 Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57310 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-05mb/google/dedede/var/drawcia: change LTE reset pin to GPP_H17Wisley Chen
Drawper change LTE reset pin from GPP_H0 to GPP_H17 from DVT phase. BUG=b:198117092 TEST=emerge-dedede coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Ib65580babf7d21535df2bd8d33bb19261bebfe15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Henry Sun <henrysun@google.com>
2021-09-03mb/google/dedede/var/bugzzy: Configure DDI port A as MIPI DSISeunghwan Kim
Override DdiPortAConfig as MIPI DSI BUG=b:192521391 BRANCH=None TEST=Built test coreboot image and boot on bugzzy board Change-Id: If308f9d69fea56176527e7b67f36b29c43adb525 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-03src/*: Specify type of `DIMM_SPD_SIZE` onceAngel Pons
Specify the type of the `DIMM_SPD_SIZE` Kconfig symbol once. Change-Id: I619833dbce6d2dbe414ed9b37f43196b4b52730e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-31mb/google/dedede/var/cret: Modify Wifi SAR conditionIan Feng
Using tablet mode of fw config to decide to load custom wifi sar or not. BUG=b:194163604 TEST=build and test on cret and cret360 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: Ie94c2a07ad43fe1cb426e543dd97ed0434c42f2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-30mb/google/dedede/var/driblee: Configure thermal sensor settingFrank Wu
According to schematics, TSR2 thermal sensor is not present in driblee. BUG=b:191732473, b:197180925, b:195868075 BRANCH=keeby TEST=FW_NAME="driblee" emerge-keeby coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I343a6161f71f66b77d23f1fa2f581aaee5eddf1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57091 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-30mb/google/dedede/var/driblee: Configure audio settingFrank Wu
Update the combination audio CS42L42 and amp. MAX98360. BUG=b:195619349, b:191732473 BRANCH=keeby TEST=FW_NAME="driblee" emerge-keeby coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I264c680ed5638b71c912253a38c27152a9015d4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-08-28mb/google/{dedede,hatch}: Remove unneeded documentationFelix Singer
This documentation doesn't add any more value. Thus, remove it. Change-Id: I0402bc736c6cc77d88a836bddce8eadae8ec5d7c Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-28soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by defaultFelix Singer
Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the default by changing its enum value to 0 and remove its configuration from all related devicetrees. If `common_soc_config.chipset_lockdown` is not configured with something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT` is used. Also, add a release note for the upcoming 4.15 release. Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-28mb/google/dedede/var/drawcia: Add fw_config probe for ALC5682-VD/ALC5682-VSWisley Chen
ALC5682-VD/ALC5682-VS use different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:194356991 TEST=ALC5682-VD/ALC5682-VS audio codec can work Change-Id: I71b824c42c13cc2a8bebe0072de4a65ce238f074 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-28mb/google/dedede/var/boten: Generate SPD ID for supported partstanley.wu
Add supported memory part in the mem_parts_used.txt and generate the SPD ID for the part. The memory part being added is: MT53E512M32D1NP-046 WT:B BUG=b:194223174 BRANCH=dedede TEST=Build the boten board. Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I36fcbf7333fd9e85b28baa64676f8435aca63889 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-28mb/google/dedede/var/driblee: Configure I2C ports and touchpadFrank Wu
Update the I2C ports and touchpad based on the schematic. BUG=b:195622489, b:191732473 BRANCH=keeby TEST=FW_NAME="driblee" emerge-keeby coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I8778ad6564e526e029c46c36c78e38f764e3c6b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56998 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/google/dedede/var/driblee: Configure USB port settingsFrank Wu
Update the USB port configuration based on driblee schematic. USB2 [0]: USB Type C Port 0 USB2 [1]: None USB2 [2]: USB Type A Port 1 USB2 [3]: None USB2 [4]: None USB2 [5]: Camera UFC USB2 [6]: None USB2 [7]: None USB3 [0]: USB Type C Port 0 (M/B side) USB3 [1]: None USB3 [2]: USB Type A Port 0 (M/B side) USB3 [3]: None BUG=b:195622487, b:191732473 BRANCH=keeby TEST=FW_NAME="driblee" emerge-keeby coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Id9f4f8db98cb20db1c3936c65689a847a7802b9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56997 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/google/dedede/var/corori: Generate RAM ID and SPD fileIan Feng
Add the support RAM parts for Corori. Here is the ram part number list: DRAM Part Name ID to assign H9HCNNNBKMMLXR-NEE 0 (0000) K4U6E3S4AA-MGCR 0 (0000) lp4x-spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR BUG=b:196744958 BRANCH=keeby TEST=emerge-keeby coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: Ia11b5db145deeea838a8f5949accdb11e13342f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56988 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/google/dedede/var/corori: Configure thermal sensor settingIan Feng
According to schematics, TSR2 thermal sensor is not present in corori. BUG=b:197281317 BRANCH=keeby TEST=FW_NAME="corori" emerge-keeby coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: Id69f9d6ace738ef1e792addd782d05c2d03d2b3a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57110 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/google/dedede/var/corori: Configure I2C ports and touchpadIan Feng
1. Support Elan touchpad. 2. Follow schematic to disable I2C1, I2C2 and I2C3. BUG=b:197052531 BRANCH=keeby TEST=FW_NAME="corori" emerge-keeby coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: Ideef57c275432e21f8580d4c5c937909b168d91f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57031 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/google/dedede/var/corori: Configure audio settingIan Feng
Select the drivers for ALC5682 codec and MAX98360A spk amp BUG=b:197037090 BRANCH=keeby TEST=FW_NAME="corori" emerge-keeby coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I0659a05fbcc28702d922a23d74885ba65a4254f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57015 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/google/dedede/var/corori: Configure USB port settingsIan Feng
Follow schematic to modify USB port settings. USB2 [0]: USB Type C Port 0 USB2 [1]: None USB2 [2]: USB Type A Port 0 USB2 [3]: None USB2 [4]: None USB2 [5]: Camera UFC USB2 [6]: None USB2 [7]: Integrated Bluetooth USB3 [0]: USB Type C Port 0 (M/B side) USB3 [1]: None USB3 [2]: USB Type A Port 0 (M/B side) USB3 [3]: None BUG=b:196998272 BRANCH=keeby TEST=FW_NAME="corori" emerge-keeby coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I2045b2be9d79bfd394fa4520faa0fb552a704206 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57010 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/google/dedede/var/corori: Configure GPIO settingsIan Feng
Updated the GPIO pins based on the latest schematic. BUG=b:196867404 BRANCH=keeby TEST=FW_NAME=corori emerge-keeby coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I683a7da4fcb2e4e0efdb3547b1de15796c6b55e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-27mb/google/dedede/var/driblee: Configure GPIO settingsFrank Wu
Updated the GPIO pins based on the latest schematic. BUG=b:191732473, b:195619827 BRANCH=keeby TEST=FW_NAME=driblee emerge-keeby coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I20baeb6b13c8c0a70c7555aa8f7f5557768c0083 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56996 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27mb/google/dedede/variant/drawcia: Include SPD for MT53E512M32D1NP-046 WT:BWisley Chen
Add SPD support to drawcia for MT53E512M32D1NP-046 WT:B. This part is already in global_lp4x_mem_parts.json.txt, and use /util/spd_tool/lp4x/gen_part_id to assigns DRAM IDs. BUG=b:196951879 BRANCH=firmware-dedede-13606.B TEST=FW_NAME=drawcia emerge-dedede coreboot chromeos-bootimage Change-Id: Ic42e6357943ba651ffd92fb2974e9ea52fa19020 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56905 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27mb/google/dedede/var/sasukette: Add FW_CONFIG probe for EXT_VRZhi Li
commit df520855 (soc/intel/jsl: Add disable_external_bypass_vr config) Add FW_CONFIG probe for don't stuffing ANPEC APW8738BQBI IC. BUG=b:190727416 BRANCH=dedede TEST=test for enter S0ix and resume normally by powerd_dbus_suspend Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com> Change-Id: I15ab30f14df9dc02157009091aa8398e2fa75188 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56804 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-26mb/google/dedede/var/bugzzy: Configure USB portsSeunghwan Kim
Override USB port configurations based on the latest bugzzy schematics. BUG=b:192521391 BRANCH=None TEST=Built test coreboot image Change-Id: I4368946f4175f4f065a3483dc7ca6068c6de3123 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-25mb/google/dedede/var/galtic: modify touchscreen to native I2C protocolFrankChu
Touchscreen will be no function with R93-14092.19.0 image or be later. It just happened to work because elants_i2c driver would bind to the device first based on "ELAN0001" HID ID BUG=b:195994810 TEST= verify only update RW FW can fix touchscreen no function issue 1.Build test firmware 2.prepare DUT enviroment (R93 image + update RW to test firmware) 3.verify touchscreen function normally Signed-off-by: FrankChu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Ie9e0fe726854d0128ad1bb430544640dc8f034ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/57011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
2021-08-25mb/google/dedede/var/sasukette: Update DPTF parametersZanxi Chen
Update DPTF parameters from internal thermal team. BUG=b:180875580 BRANCH=dedede TEST=emerge-dedede coreboot Change-Id: I06d8a543dbd77137cb97c4ea695a1f2b9f8ee76c Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57116 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-24mb/google/dedede/var/cret: Add new G2Touch touchscreenDtrain Hsu
Add G2Touch G7500 touchscreen into devicetree for cret. BUG=b:180547621 BRANCH=dedede TEST=Built cret firmware and verified touchscreen function. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I57638bf8a3eb4efcd819f5433fa54c22b7af3054 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-23mb/google/dedede: add gooey variantstanley.wu
gooey is the same design as boten, and differs only in replacing Cr50 with discrete TPM. BUG=b:193366710, 197247706 TEST=FW_NAME=gooey emerge-keeby coreboot Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I2a54f872a7d5c0bee76a9e6e309613d9357b380b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-23mb/google/dedede/var/bugzzy: Configure GPIO settingsSeunghwan Kim
Override GPIO pad configurations based on the latest bugzzy schematics. BUG=b:192521391 BRANCH=None TEST=Built test coreboot image and boot on bugzzy board Change-Id: I7c3580e7eb34efed0441ead243343d2d7875d50f Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-19mb/google/dedede/var/driblee: Generate RAM ID and SPD fileFrank Wu
Add the support RAM parts for Driblee. Here is the ram part number list: 1. Hynix H9HCNNNBKMMLXR-NEE 2. Micron MT53E512M32D2NP-046 WT:F 3. Samsung K4U6E3S4AA-MGCR 4. Micron MT53E512M32D1NP-046 WT:B BUG=b:195619346 BRANCH=keeby TEST=emerge-keeby coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I683acb91ec13cbd772e732d7f81152ceb3cefc1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56924 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-18mb/google/dedede/var/sasukette: Add fw_config probe for ALC5682I-VD & VSZhi Li
Update the `_HID` value of device in SSDT depending on the fw_config. According to value of AUDIO_CODEC_SOURCE field in fw_config(SSFC) which stored in CBI: AUDIO_CODEC_ALC5682: _HID = "10EC5682" /* ALC5682I-VD */ AUDIO_CODEC_ALC5682I_VS: _HID = "RTL5682" /* ALC5682I-VS */ BUG=b:193623380 BRANCH=dedede TEST=ALC5682I-VD or VS audio codec can work normally Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com> Change-Id: Ic8840454e4934162ea59c742634a56f70b153238 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
2021-08-17mb/google/dedede/variant/lantis: Include SPD for MT53E512M32D1NP-046 WT:BWisley Chen
Add SPD support to lantis for MT53E512M32D1NP-046 WT:B BUG=None BRANCH=firmware-dedede-13606.B TEST=FW_NAME=lantis emerge-dedede coreboot chromeos-bootimage Change-Id: I22c50a55dd3b8bbda64ba1b607c8b22cc6592f98 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-17mb/google/dedede/var/cappy2: Fix the DUT with cirrus codec PLT failSunwei Li
irq(ACPI_IRQ_LEVEL_LOW) -> ACPI_DESCRIPTOR_INTERRUPT -> IO-APIC, will assert interrupt frequently; irq_gpio(ACPI_GPIO_IRQ_EDGE_BOTH) -> ACPI_DESCRIPTOR_GPIO -> INT34C8; will not assert interrupt frequently; Because IRQ configuration can't be setted to both EDGE trigger. BUG=b:195635555 BRANCH=dedede TEST=Cirrus audio codec PLT pass Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: I65bca519f75af84848284f039b6ad67cb1887823 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56973 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16mb/google/dedede: Create driblee variantFrank Wu
Create the driblee variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:191732473 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_DRIBLEE Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I1ad9a4e0cf7999337b55d62d5cc94e4f6c2e98f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-16mb/google/dedede: Create corori variantIan Feng
Create the corori variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:194356176 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_CORORI Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I8380d5aab61c99d545625789ff1251ec1caa84a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56796 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-13mb/google/dedede: allow MKBP devices and disable TBMC deviceBoris Mittelberg
Enable MKBP (Matrix Keyboard Protocol) interface for all dedede family to use for buttons and switches. Disable TBMC (Tablet Mode Switch device), as it is not needed anymore. BUG=b:170966461 TEST=manual test on Madoo: Volume Up/Down and Power buttons, Tablet Mode switch Cq-Depend: chromium:3069163 Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: I9d1f43e4dd56318af4c1d5f5c1c3a2c237a05c5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56840 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12mb/google/dedede/var/galtic: Add charger throttling functionFrankChu
Add charger current throttling support for galtic control charger index * 64 = Value mA 32*64=2048 28*64=1792 24*64=1536 20*64=1280 BUG=b:187231627 TEST=Built and tested on boten system Cq-Depend: chrome-internal:3846209 Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I5e1849551ff051bca591f19f9e40da4c89ab74e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-08-12mb/google/dedede/variants/haboki: add discrete TPM in overridetreeWisley Chen
Haboki is project which use discrete TPM, so add discrete TPM and disable cr50 in overrideree. BUG=b:187094464 TEST=FW_NAME=haboki emerge-keeby coreboot chromeos-bootimage Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I08f2a562c3f62c60402350151ea260b70890a744 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-08-10mb/google/dedede/var/cret: Fix DPTF passive and critical policiesDtrain Hsu
TSR2 thermal sensor doesn't define in cret. Fix DPTF passive and critical policies for getting negative temperatures in OS. BUG=b:195868075 BRANCH=dedede TEST=Build and boot to OS in cret. Ensure that the DPTF entries look correct in both static.c and SSDT tables i.e. passive and critical policies for applicable devices only are present. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I849662cbb3adc8e528d65af2c90e7c8e4880d607 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-10mb/google/dedede/var/cappy2: Add fw_config probe for multi audio codecSunwei Li
Compatible headphone codec "Realtek ALC5682I-VD" and "cirrus CS42L42" Compatible AMP codec "ALC1015Q-VB" and "MAX98360" BUG=b:193373320 BRANCH=dedede TEST=Both realtek and cirrus audio codec can work normally Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: I9121e75eaf46b43e6dc5ef2e31029a153c7a807d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-08-09mb/google/dedede/var/storo: Fixed iasl can not run on DutTao Xia
The TSR1._PSV has been redefined. It will report errors when disassembling the ACPI tables with the iasl. It is OK when Removing the TSR1._PSV and adding the TSR0._PSV BUG=b:194509417 BRANCH=dedede TEST=The iasl can run on Dut successfully Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I524255c79d3c71573d122944da5058389f79d95d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Evan Green <evgreen@chromium.org>
2021-08-09mb/*/jslrvp/dedede: Remove hardcoding of BSP APIC IDMAULIK V VAGHELA
coreboot always assumes that BSP APIC ID will be 0 and core enumeration logic will look for lapic id from the mainboard. As per Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 3: 8.4.1 BSP and AP Processors, this assumption might not hold true and we may have any other core as BSP. To handle this, we need to remove hardcoding of APIC ID 0 from mainboard. BUG=None BRANCH=None TEST=Check if there is no functional impact on the board. Change-Id: I726d70b4ffc35a28a654abbd20c866f1410e1aee Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-06mb/google/dedede/var/cappy2: Add camera supportSunwei Li
Add camera support in devicetree and associated GPIO configuration. BUG=b:193397569 BRANCH=dedede TEST=Camera function is OK Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: I3275ab408f6a03735a35eaa8025c36df09c9898c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-05mb/google/dedede: Create bugzzy variantRaymond Chung
Create the bugzzy variant of the waddledoo reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:192521391 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_BUGZZY Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Change-Id: I851b9a75c387586d2fb84b762788e962f33472b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56762 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-04mb/google/dedede/var/magolor: Modify SSFC for camera and touchscreenRen Kuo
The all shipped magolor and maglia has SSFC= 0x840. The value is defined as 5M MIPI camera.But the value:0x840 will conflict with the updated touchscreen field. It will cause some touchscreen no function if make auto-update new firmware.The CL would correct the field error. The original fields: CAMERA_WFC 38 40 TS_SOURCE 41 44 Correct fields: MIPI Cam CAMERA_WFC 38 40 CAMERA_UFC 41 42 CAMERA_VCM 43 44 Touch-screen TS_SOURCE 45 48 The SSFC value of Magolor: CAMERA_OVTI5675 5M AF (SSFC = 0x840) CAMERA_OVTI8856 8M AF (SSFC = 0x880) BUG=b:194639170 TEST=Build firmware and verify on camera and touch-screen devices Change-Id: I13d76ce8b932f483e20ca5388f1c67eb39ba12a1 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56685 Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-03Revert "mb/google/dedede/var/cret: Disable SDCard controller"Dtrain Hsu
This reverts commit f29437862269de24f85392d49f6afa6fa60ac43e. Reason for revert: It makes cret can't boot to os without depthcharge change. The depthcharge change related with fw_config and will effect other variants. BUG=b:194961854 TEST=Build and boot to OS. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I929369c9419375e74be61a4ff3e5566b0f41ce65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-02mb/google/dedede/var/cappy2: Disable external bypass VRSunwei Li
The cappy2 removed the anpec apw8738bqbi and "disable_external_bypass_vr" should be set to "1" to disable BUG=b:194146867 BRANCH=dedede TEST=VCCIN_AUX is disable Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: Ieb4182a989459db629e3b69757c293ca26e8b0cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/56687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aseda Aboagye <aaboagye@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
2021-08-02mb/google/dedede/var/cappy2: Add Tpm2.0 device supportSunwei Li
Using Tpm2.0 device instead of the Cr50 in cappy2 BUG=b:191743435 BRANCH=dedede TEST=tpm2.0 device function is ok Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: I216ceb6386ad57c9f1982187a4525d89869fa9c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56658 Reviewed-by: Aseda Aboagye <aaboagye@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-31mb/google/dedede/var/boten: Set the xHCI LFPS period sampling off time to 0msstanley.wu
LTE module L850-GL may encounter U3 wakeup race condition with the host. Setting xHCI LFPS periodic sampling off time to 0ms so that the host would not miss the device-initiated U3 wakeup thus avoid the race condition. BUG=b:187801363 BRANCH=dedede TEST=flash the image to the device. Run following command to check the bits[7:4] is 0x0: iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I9328e758ed92389e44b25ff4daf6ec19b37ae7d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Ben Kao <ben.kao@intel.corp-partner.google.com>
2021-07-29mb/google/dedede/var/cappy2: Add I2C devicesSunwei Li
Add tp and audio devices support in devicetree. BUG=b:193099842 BRANCH=dedede TEST=i2c devices function is OK Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: I995e93b5a4c4294d6f6b97c48d14fabf48004d92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56513 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/google/dedede: Configure VCCIOSEL for EN_SPKR GPIO PadKarthikeyan Ramasubramanian
Realtek speaker amplifiers under auto mode operation have Absolute Max Rating (AMR) at 1.98 V. Hence probe the firmware config for speaker amplifier and program the VCCIOSEL accordingly. BUG=b:194120188 TEST=Build and boot to OS in Storo. Ensure that the VCCIO selection is configured as expected and probing the GPIO reads the configured voltage. Change-Id: Ibd3bc90bd0bbc9a35922b29e3d1e106321bc7a06 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56616 Reviewed-by: Evan Green <evgreen@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/google/dedede/var/storo: Set the xHCI LFPS period sampling off time to 0msTao Xia
LTE module L850-GL may encounter U3 wakeup race condition with the host. Setting xHCI LFPS periodic sampling off time to 0ms so that the host would not miss the device-initiated U3 wakeup thus avoid the race condition. BUG=b:193898133 BRANCH=dedede TEST=flash the image to the device. Run following command to check the bits[7:4] is 0x0: iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: Ic84dc83b749cf3c6029a06730096b64ef8cb8cd9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-29mb/google/dedede/var/pirika: Configure I2C times to 380-400 kHz for touchpadAlex1 Kao
Configure I2C high / low time in the device tree to ensure I2C CLK runs accurately between 380 kHz and 400 kHz. Audio codec:388.91 kHz Touchpad:394.48 kHz BUG=b:193864546 BRANCH=dedede TEST=Build and check after tuning I2C clock is between 380 kHz and 400 kHz Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Change-Id: Ia57c90ead44ceb0990878dc0566e595bae5a9099 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56383 Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-28Revert "mb/google/dedede: Program VCCIO selection for EN_SPKR GPIO"Karthikeyan Ramasubramanian
This reverts commit ce79ceec86a38145b3a27aa4c78cf83a76cd51d0. This has introduced a regression in mainboards using JSL SoC such that it overrides the soft straps for all the GPIOs. This in turn has led to some of the peripherals not working. Change-Id: Ifea5d4d0f474873f8bf4818ec1986e534f455216 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56615 Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-28mb/google/dedede/var/magolor: Add custom Wifi SAR for magisterDavid Wu
Add wifi sar for magister. Due to fw-config cannot distinguish between magolor and magister. Using sku_id to decide to load magister custom wifi sar. BUG=b:192290227 TEST=build and test on magolor/magister Cq-Depend: chrome-internal:3986580 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I4510cc2ad42a11ec802ecd439b353f8e87d63868 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-28mb/google/dedede/var/sasukette: Set the xHCI LFPS period sampling off time ↵Tao Xia
to 0ms LTE module L850-GL may encounter U3 wakeup race condition with the host. Setting xHCI LFPS periodic sampling off time to 0ms so that the host would not miss the device-initiated U3 wakeup thus avoid the race condition. BUG=b:191426542 BRANCH=dedede TEST=flash the image to the device. Run following command to check the bits[7:4] is 0x0: iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I3be7adad49f87956a6764ad91fec6e76681b393f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Chiasheng Lee <chiasheng.lee@intel.com>
2021-07-26mb/*: Specify type of `VARIANT_DIR` onceAngel Pons
Specify the type of the `VARIANT_DIR` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: Iea2f992a59e41e00fec3cdc9d6a13b5f3ab0a437 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56558 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `FMDFILE` onceAngel Pons
Specify the type of the `FMDFILE` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I810bd3fe8d42102586db6c2c58b7037a60189257 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56557 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `OVERRIDE_DEVICETREE` onceAngel Pons
Specify the type of the `OVERRIDE_DEVICETREE` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I4cbf4e318a30f0cf75aa8690e7454b9caa115c9d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56556 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `DEVICETREE` onceAngel Pons
Specify the type of the `DEVICETREE` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: If68f11a5ceaa67a3e8218f89e1138c247ebb9a25 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56555 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `MAINBOARD_PART_NUMBER` onceAngel Pons
Specify the type of the `MAINBOARD_PART_NUMBER` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I3692f9e82fe90af4d0da1d037018a20aa1b45793 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56554 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `MAINBOARD_DIR` onceAngel Pons
Specify the type of the `MAINBOARD_DIR` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: If1cc538b0c4938dac193699897b690e402b3c1e8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56553 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/google/dedede: Program VCCIO selection for EN_SPKR GPIOKarthikeyan Ramasubramanian
Realtek speaker amplifiers under auto mode operation have Absolute Max Rating (AMR) at 1.98 V. Hence probe the firmware config for speaker amplifier and program the VCCIOSEL accordingly. BUG=b:194120188 TEST=Build and boot to OS in Gallop. Ensure that the VCCIO selection is configured as expected and probing the GPIO reads the configured voltage. Change-Id: Ifa0b272c23bc70d9b0b23f9cc9222d875cd24921 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-26mb/google/dedede/var/pirika: Add USB2 PHY parametersAlex1 Kao
This change adds fine-tuned USB2 PHY parameters for pirika. BUG=192601233 TEST=Built and verified USB2 eye diagram test result Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Change-Id: Icf9fb41cd0ae40728e4ec5bd72a15ec3c45c963b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-26mb/google/dedede/var/cappy2: Generate SPD ID for supported memory partsSunwei Li
Add supported memory 'K4U6E3S4AA-MGCR' for cappy2 BUG=None TEST=Build the cappy2 board. Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: Ie76a4dca607bb2c3261bbe5478209a43e8430591 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-26soc/intel/jasperlake: Set xHCI LFPS period sampling off timeBen Kao
Provide an option to set xHCI LFPS period sampling off time (SS_U3_LFPS_PRDC_SAMPLING_OFFTIME_CTRL in JSL EDS revision 2.0). If the option is set in the devicetree, the bits[7:4] in xHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated. The host will sample LFPS for U3 wake-up detection when suspended, but it doesn't sample LFPS at all time due to power management, the default xHCI LFPS period sampling off time is 9ms. If the xHCI LFPS period sampling off time is not 0ms, the host may miss the device-initiated U3 wake-up and causes some kind of race condition for U3 wake-up between the host and the device. BUG=b:187801363, b:191426542 TEST=build coreboot with xhci_lfps_sampling_offtime_ms and flash the image to the device. Run following command to check the bits[7:4]: iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Ben Kao <ben.kao@intel.com> Change-Id: I0e13b7f51771dc185a105c5a84a8e377ee4d7d73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-22mb/google/dedede/var/cret: Add Wifi SAR for cretIan Feng
Add wifi sar for cret. BUG=b:194163601 TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: Ic2f3dbc5822c1f4b1c935c87295ba9916e0e359e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-07-07mb/google/dedede/var/boten: Modify Wifi-SAR sku conditionstanley.wu
Due to new sku id apply for AMP ALC1015Q-VB. Modify correct WIFI-SAR detect condition for boten/botenflex sku. BUG=b:186174768 TEST=build and test on boten/botenflex Change-Id: I0a4fb08e558fee26534564aa5e37cac814c5a98a Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-07mb/google/dedede/var/storo: Update DPTF parametersTao Xia
Update DPTF parameters from internal thermal team. BUG=b:180875582 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I6d87bc63a66ff38bc2f706d58b8537c052bf4594 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-07mb/google/dedede/var/sasukette: Configure I2C times for touchpadTao Xia
Configure I2C high / low time in the device tree to ensure I2C CLK runs accurately between 380 kHz and 400 kHz. Measured I2C frequency just as below after tuning: touchpad:390.4 kHz BUG=b:192601250 BRANCH=dedede TEST=Build and check after tuning I2C clock is between 380 kHz and 400 kHz Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: Ibe1603a48a3e841b6a50aa0c703697ec615b2854 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-05mb/google/dedede: Fix the pointer/address used in memcpyKarthikeyan Ramasubramanian
The caller is already passing the address to the required LTE reset and enable GPIO. During memcpy, the address to that pointer is used which will lead to copying undefined data. Fix the pointer/address used in memcpy. BUG=None BRANCH=dedede TEST=Build Kracko, Drawcia and Metaknight mainboards which use this function. Change-Id: I79d6d9af03acd59ab5e1cd7df97bf451011dfeaa Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Found-by: Coverity CID 1458053, 1458054. Reviewed-on: https://review.coreboot.org/c/coreboot/+/56046 Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-05mb/google/dedede/var/cret: Disable SDCard controllerDtrain Hsu
Cret doesn't support SDCard. Disable SDCard contorller for Cret. BUG=b:191232222 TEST=Build and boot to check lspci Cq-Depend: chromium:2993724 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I889f0545883aa75813dd91dc3e6a4dcfc246687f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-02mb/google/dedede/var/magolor: Enable G2 touchscreen for magmaTyler Wang
Add G2 touchscreen support for magma. BUG=b:189852808 TEST=Build and verify that touchscreen works. Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I3e032bff7f3e97f54f3e544035e862058ea0dbfc Reviewed-on: https://review.coreboot.org/c/coreboot/+/55976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2021-07-01mb/google/dedede: Create cappy2 variantSunway
Create the cappy2 variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:192035460 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_CAPPY2 Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: I772801152b9ca9c2c6afe76a353cb2b62d6210ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/55886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-01mb/google/dedede/var/drawcia: Add LTE modem support for drawperKevin Chiu
Add LTE modem to devicetree. Configure GPIO control for LTE modem by fw_config. Update LTE USB port configuration at run-time after probing FW_CONFIG. By default the concerned USB port takes the Type-A port configuration. BUG=b:186393848 TEST=Build image and check with command modem status Change-Id: I20450ae37e5047dba67211316515994bd2a09600 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-01mb/google/dedede/var/kracko: Update LTE USB port configurationTony Huang
Update LTE USB port configuration at run-time after probing FW_CONFIG. By default the concerned USB port takes the Type-A port configuration. BUG=b:178092096 BRANCH=dedede TEST=Build and boot to OS to check LTE by modem status Change-Id: If12cc29ddda6d5c32c0bda840a3680e7bf932f89 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54671 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-30mb/google/dedede/var/storo: Add USB2 PHY parameters for LTE USB2.0Tao Xia
This change adds fine-tuned USB2 PHY parameters for storo. BUG=191089827 TEST=Built and verified USB2 eye diagram test result Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I38dd8ad59b32f635e641765e0a1bd13651180d23 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-30mb/google/dedede/var/storo: Enable Wifi SAR for storoTao Xia
BUG=b:190027970,b:178175837 BRANCH=dedede TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I7084f9b7be2b66adda2d9d5a83ce5dd9c31d01b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-28mb/google/dedede/var/blipper: Update devicetree and gpio settingZanxi Chen
To reduce power load, set unused GPIOs to NC and close unused interface in devicetree. GPIOs and interfaces are as below: GPIO: GPP_C18/C19/D12/D14/D15/D19/D20/D21/E00/E02/H06/H07 Interface: I2C1/I2C3/I2C5 USB: port2_3/2_4/2_6 BUG=b:185044041 BRANCH=dedede TEST=Built bios and test, it reduces power load without affecting device function. Change-Id: Ib5999f0e129bf3e660fe293eda7af3e8e1426151 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Ben Kao <ben.kao@intel.com>
2021-06-28mb/google/dedede/var/sasukette: Update DPTF parametersTao Xia
Update DPTF parameters from internal thermal team. BUG=b:180875580 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I4dbe3947779395903d7999627948d3e97d6cc985 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-28mb/google/dedede/var/cret: Add ssfc codec cs42l42 supportDtrain Hsu
Add cs42l42 codec support in cret. BUG=b:188623237, b:189073353 TEST=Build and boot to check functional with cs42l42 EV board. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I2c53291e07fd785c1360c05171eed634788bc665 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55091 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-28mb/google/dedede/var/pirika: Update DPTF parametersAlex1 Kao
Update DPTF parameters from internal thermal team. BUG=b:190518303 BRANCH=None TEST=emerge-dedede coreboot Change-Id: I4005047e0c5f39a12c161a92fbd0afaaec1dc976 Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com>
2021-06-28mb/google/dedede/var/pirika: Support audio AMP auto modeAlex1 Kao
Support audio AMP selection with fw_config. BUG=b:188446060 BRANCH=None. TEST=built pass Change-Id: Idf0eb2a87bfa9665e61d185e37adb90987f3cefb Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com>
2021-06-28mb/google/dedede/var/blipper: Enable ELAN touchscreenZanxi Chen
Modify driver from hid to generic(ELAN0001 that used generic driver without hid). BUG=b:191620724 BRANCH=dedede TEST=build bios and boot, touchscreen will work properly. Change-Id: Ife77d514d9906049f237edd169bc07bb53c48579 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
2021-06-23mb/google/dedede/var/magolor: Enable weida touchscreen for magisterDavid Wu
Add weida touchscreen support for magister. BUG=b:191633024 BRANCH=dedede TEST=Build and verify that touchscreen works on magister. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I3de6a84d2d58ef87f0ae13e8a117a980a0210ac4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Randy Lai <randy.lai@weida.corp-partner.google.com>
2021-06-23mb/google/dedede/var/sasukette: Change ELAN touchpad driverZhi Li
Use drivers/i2c/hid can't update firmware by kernel update script, so change to drivers/i2c/generic. BUG=b:188602529 BRANCH=dedede TEST=can update ELAN touchpad firmware(277.0_1.0) by kernel script Change-Id: I3592403fe5d0f8d0f67059f8296277e3c028c117 Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55248 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-21mb/google/dedede/var/storo: Update DPTF parametersTao Xia
Update DPTF parameters from internal thermal team. BUG=b:180875582 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: Ica2f2856000c8dcbf4d23b7b4a3c479dc7d4862b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-06-21mb/google/dedede/var/blipper: Configure Acoustic noise mitigation UPDsZanxi Chen
Enable Acoustic noise mitigation for blipper and set slew rate to 1/8 which is calibrated value for the board. BUG=b:187760191 BRANCH=dedede TEST=build firmware to UPD and Acoustic noise test Change-Id: I187702c23712416eaaaaf1e210dcfc6b2c560041 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-19mb/google/dedede: Configure CBI EEPROM WPAseda Aboagye
On dedede boards without Cr50, the CrOS Board Info (CBI) EEPROM write protect signal is decoupled from the hardware write protect signal. Instead, we'd like for it to mirror the software write protect status. This commit simply checks the software write protect status of the SPI flash and sets the CBI EEPROM write protect if it's enabled. To prevent changing the WP signal at run-time, the GPIO configuration is also locked down after the level has been set. If HW WP is deasserted, the CBI EEPROM WP will be deasserted as well. BUG=b:191189275,b:184592299 BRANCH=None TEST=Build and flash lalala, disable SW WP by running `flashrom -p host --wp-disable` from a root shell and verify that the GPIO is asserted after a reboot. Export the gpio via sysfs and verify that attempting to change the value of the GPIO is futile. Enable SW WP via `flashrom -p host --wp-enable` and reboot the DUT. Again, export the GPIO via sysfs and verify that attempts to change the GPIO value are futile. localhost ~ # iotools mem_read32 0xfd6e08d0 0x44000200 localhost ~ # cd /sys/class/gpio/ localhost /sys/class/gpio # echo 217 > export localhost /sys/class/gpio # cd gpio217/ localhost /sys/class/gpio/gpio217 # echo out > direction localhost /sys/class/gpio/gpio217 # cat value 0 localhost /sys/class/gpio/gpio217 # echo 1 > value localhost /sys/class/gpio/gpio217 # cat value 1 localhost /sys/class/gpio/gpio217 # iotools mem_read32 0xfd6e08d0 0x44000200 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: Ic103037921ec7d2f96f86178675c11a3a1357d1b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-17mb/google/dedede/var/kracko: Configure I2C high and low timesTony Huang
Configure I2C high / low time in device tree to ensure I2C CLK runs under I2C_SPEED_FAST (400 kHz). Touchpad: 387.7kHz Touchscreen: 389.4kHz Audio: 387.6kHz P-sensor: 372.5kHz BaUG=b:178092096 BRANCH=dedede TEST=Build and EE check after tuning I2C clock is under 400kHz Change-Id: I4f6bdd3802cd94671325a89458cde981a2ffa929 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-17mb/google/dedede: Create cappy variantZhi Li
Create the cappy variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:190515828 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_CAPPY Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com> Change-Id: Id5a3b0cb475ee77a9f62523d8322a5e4123ce3be Reviewed-on: https://review.coreboot.org/c/coreboot/+/55451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-17mb/google/dedede/var/pirika: Add camera supportAlex1 Kao
Add camera support in devicetree. BUG=b:190797339 BRANCH=None. TEST=built pirika firmware and verified camera function is OK. Change-Id: I66ded32105f3166e2faec3ea5dcfb93c29822366 Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55450 Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17mb/*: Fix some indirect includesKyösti Mälkki
Fix build failures in the case <vc/.../chromeos.h> is removed. Change-Id: Ie45066f39cd6fb92cca697a6bd5bc8bb8c60b4e7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-10mb/google/dedede/var/pirika: Support Realtek audio codec ALC5682I and ↵Alex1 Kao
speaker L/R Add Realtek audio codec ALC5682I and speaker L/R the same way as in waddledee BUG=b:188446060 BRANCH=dedede TEST=Boot to check ALC5682I and speaker L/R are functional Change-Id: I8173ffbfb1a8f18978a5e35c69972d4a6d8cb04a Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54529 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>