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authorKarthikeyan Ramasubramanian <kramasub@google.com>2021-07-26 16:01:57 -0600
committerPatrick Georgi <pgeorgi@google.com>2021-07-29 09:14:19 +0000
commitba9b476d1bdb5c3f666c16f4d5579616300e4569 (patch)
tree9e5e499d9be57af78b087c3e3477634952a5cca8 /src/mainboard/google/dedede
parent0b39a5a23ac8eb06b06757b94f641151d8603c10 (diff)
mb/google/dedede: Configure VCCIOSEL for EN_SPKR GPIO Pad
Realtek speaker amplifiers under auto mode operation have Absolute Max Rating (AMR) at 1.98 V. Hence probe the firmware config for speaker amplifier and program the VCCIOSEL accordingly. BUG=b:194120188 TEST=Build and boot to OS in Storo. Ensure that the VCCIO selection is configured as expected and probing the GPIO reads the configured voltage. Change-Id: Ibd3bc90bd0bbc9a35922b29e3d1e106321bc7a06 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56616 Reviewed-by: Evan Green <evgreen@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/dedede')
-rw-r--r--src/mainboard/google/dedede/Makefile.inc1
-rw-r--r--src/mainboard/google/dedede/fw_config.c23
2 files changed, 24 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/Makefile.inc b/src/mainboard/google/dedede/Makefile.inc
index 1b5503d40f..290f2a3b68 100644
--- a/src/mainboard/google/dedede/Makefile.inc
+++ b/src/mainboard/google/dedede/Makefile.inc
@@ -9,6 +9,7 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-y += mainboard.c
ramstage-y += ec.c
ramstage-y += board_info.c
+ramstage-y += fw_config.c
VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR))
diff --git a/src/mainboard/google/dedede/fw_config.c b/src/mainboard/google/dedede/fw_config.c
new file mode 100644
index 0000000000..895f4891f5
--- /dev/null
+++ b/src/mainboard/google/dedede/fw_config.c
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/mmio.h>
+#include <bootstate.h>
+#include <console/console.h>
+#include <fw_config.h>
+#include <gpio.h>
+#include <intelblocks/gpio.h>
+
+#define PAD_CFG_DW2_OFFSET (2 * sizeof(uint32_t))
+#define VCCIOSEL_1V8 (1 << 8)
+
+static void fw_config_handle(void *unused)
+{
+ void *pad_conf_offset = gpio_dwx_address(GPP_D17) + PAD_CFG_DW2_OFFSET;
+ uint32_t pad_conf = read32(pad_conf_offset);
+
+ if (fw_config_probe(FW_CONFIG(AUDIO_AMP, RT1015P_AUTO))) {
+ pad_conf |= VCCIOSEL_1V8;
+ write32(pad_conf_offset, pad_conf);
+ }
+}
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);