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path: root/src/mainboard/google/brya
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2022-04-19mb/google/nissa: Add gpio lock pinsEric Lai
Followed the Brya series to lock the gpio pins in baseboard. Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. BUG=b:216671701 TEST='emerge-nissa coreboot chromeos-bootimage', flash and verify that nivviks boots successfully to kernel. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ib34ca287596a6958407a944d0caf53f4bcc60d9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-19mb/google/brya: Add Kconfig for TPM I2C busRaihow Shi
Add TPM I2C for crota to avoid TPM I2C fail. BUG=b:229200525 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I8054e623fb0c3c549c3373982ce9d4fbd57e0fd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-19mb/google/brya/var/crota: Kconfig: Select TPM I2C bus driverTerry Chen
Add TPM I2C for crota to avoid TPM I2C fail. BUG=b:226315394 TEST=USE="project_crota emerge-brya coreboot" and verify it builds without error. Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I7eb3ce6c2faf857c8f5d789af395e315caea4102 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-14mb/google/brya/var/kano: Configure Acoustic noise mitigationDavid Wu
Setup the following acoustic noise mitigation features: 1) Slew rate for both IA and GT domains to 1/8 2) Disable Fast package C ramp BUG=b:229046516 TEST=build and verified by power team Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ifb5700391e33818878994f205acae7ee3b1b96d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-14mb/google/brya: Add variant_init and variant_finalize callbacksTim Wawrzynczak
Some brya variants may need to initialize and finalize some variant-specific devices during ramstage, therefore add the commonly-used hooks and callbacks to support this. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iede6dc5a5b9a7385fedd59d4eeaaba118eff0e20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-13mb/google/brya/baseboard/nissa: Configure I2C lcnt and hcntReka Norman
Configure lcnt and hcnt directly to give the required frequency, tHIGH and tLOW, instead of using rise and fall times. Aim for a frequency of 390 kHz to make sure it doesn't exceed 400 kHz on different boards. BUG=b:227517802 TEST=Probe the clock line and check that it meets the requirements for frequency, tHIGH and tLOW. Change-Id: I4d4f877c1f0cd9aacd3fa152890b7ef82e059f78 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-13mb/google/brya: Create craask variantTyler Wang
Create the craask variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:None BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_CRAASK Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Icf03e3f18468d7dd207ab200fa2dcf96afd02f8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-13mb/google/brya: Add missing parameter name to variant_generate_s0ix_hookReka Norman
Fixes the following build error: src/mainboard/google/brya/mainboard.c: In function 'variant_generate_s0ix_hook': src/mainboard/google/brya/mainboard.c:157:40: error: parameter name omitted void __weak variant_generate_s0ix_hook(enum s0ix_entry) ^~~~~~~~~~~~~~~ BUG=None TEST=`abuild -a -x -c max -p none -t google/brya` now succeeds Change-Id: Id578766e2a3b7647e920740dde3e356a7db39d4d Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-13mb/google/brya/var/nereid: Enable OZ711LV2LN SD card controllerReka Norman
Select the Bayhub LV2 driver, and implement power sequencing as per the datasheet. BUG=b:223304542 TEST=Check that connecting an SD card works as expected in the OS. Probe the EN and RST signals and check the timing requirements are met. Change-Id: Id1cca2024e06e5b2c7cefd22aa0b735bc542dc3b Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-04-13mb/google/brya/var/brya0: Change MAX98360 AMP interface to I2S1Amanda Huang
Based on the latest schematic, change MAX98360 AMP interface from I2S2 to I2S1 due to Intel BT offload concern. BUG=b:202671753 BRANCH=firmware-brya-14505.B TEST=dmidecode -t 11 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Change-Id: I9ee45dbceabdedd39a9befffb8002b8bc3d4bfb4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-12mb/google/brya/var/vell: add WWAN power sequence setting for vellRobert Chen
Add WWAN power sequence setting to meet spec BUG=b:220084872 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: If6d3f965b8f6b6753446f55a8bd47d3b0c1ae7be Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-07mb/google/brya/var/taniks: Enable Genesys L1 max entry delayJoey Peng
The workaround causes the eMMC controller to not enter its L1 during the boot process BUG=b:220079865 TEST=Build FW and run stress exceed 2500 cycles. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I2a5888e943c1ebf83a54f9b172f986f8b13d9b6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-07ChromeOS: Add DECLARE_x_CROS_GPIOS()Kyösti Mälkki
Change-Id: I88406fa1b54312616e6717af3d924436dc4ff1a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-07mb/google/brya/var/nereid: Add WLAN power sequenceReka Norman
There are currently two issues related to the WLAN power sequencing on nereid: - If the EN pin GPP_B11 is not high during cold boot, the SoC gets stuck in S3. - During warm reboot, if we only assert RST without pulling the power low, then the kernel crashes. As a workaround while we investigate these issues, we pull the EN high in S5, then actively drive it low in bootblock and high in romstage to make sure it goes low during warm reboot. BUG=b:227694137, b:225261075 TEST=Cold boot succeeds, and there's no kernel crash during warm reboot. Change-Id: I1ca46d9649eff3f96a0e77db594d87288b29a83a Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Sam McNally <sammc@google.com>
2022-04-07mb/google/brya/var/nereid: Enable pen garageReka Norman
BUG=None TEST=evtest works: Select the device event number [0-14]: 9 Input driver version is 1.0.1 Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100 Input device name: "PRP0001:00" Supported events: Event type 0 (EV_SYN) Event type 5 (EV_SW) Event code 15 (SW_PEN_INSERTED) state 1 Properties: Testing ... (interrupt to exit) Event: time 1649153020.275201, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0 Event: time 1649153020.275201, -------------- SYN_REPORT ------------ Event: time 1649153025.848689, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1 Event: time 1649153025.848689, -------------- SYN_REPORT ------------ Event: time 1649153028.383195, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0 Event: time 1649153028.383195, -------------- SYN_REPORT ------------ Event: time 1649153080.869155, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1 Event: time 1649153080.869155, -------------- SYN_REPORT ------------ Change-Id: I0d5134737fc758a43e1fff95e9f2a20200991bb1 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-04-07mb/google/brya/var/nereid: Configure descriptor for either Type-C or HDMIReka Norman
Some bytes in the descriptor need to be set differently for Type-C and HDMI. To allow using a single firmware variant for both cases, update the descriptor at runtime based on fw_config. This is a temporary workaround while we find a better solution. The byte values were determined by changing the following CSE strap and comparing the generated descriptors: Type-C: TypeCPort2Config = "No Thunderbolt" HDMI: TypeCPort2Config = "DP Fixed Connection" The default value before updating the descriptor is Type-C, but this was chosen arbitrarily. BUG=b:226848617 TEST=Type-C and HDMI both work on nereid with fw_config set correctly. Change-Id: I2cc230e3bd35816c81989ae7e01df5d2c152062e Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sam McNally <sammc@google.com>
2022-04-06ChromeOS: Promote variant_cros_gpio()Kyösti Mälkki
The only purpose of mainboard_chromeos_acpi_generate() was to pass cros_gpio array for ACPI \\OIPG package generation. Promote variant_cros_gpio() from baseboards to ChromeOS declaration. Change-Id: I5c2ac1dcea35f1f00dea401528404bc6ca0ab53c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-06mb/google/brya: Enable dynamic debug capability for brya familySridhar Siricilla
The patch enables dynamic debug capability for Brya family of boards. BRANCH=MAIN BUG=b:153410586 TEST= Verified the CSE firmware update functionality on Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I51b0e0bb4392d3fbdb50577d3644491ab90a33c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-04-04mb/google/brya/var/vell: Tune I2C1/I2C7 bus speed for 1 MHzEddy Lu
Tune I2C parameters to make sure I2C1 and I2C7 bus speed is around 1MHz. BUG=b:207333035 BRANCH=none TEST=built and verified adjusted I2C speed around 1MHz Change-Id: I09a9edf723bb1198bbf5d71248abc07276cd94ff Signed-off-by: Eddy Lu <eddylu@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63241 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-01mb/google/brya/var/nereid: Add separate VBT for HDMIReka Norman
BUG=b:226848617 TEST=HDMI works on nereid Cq-Depend: chrome-internal:4650256 Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I6a90d3d86b32f73ec0130e582539d1c5b045da62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-04-01mb/google/brya/var/nereid: Disable C1 PMC mux conn for HDMIReka Norman
BUG=b:226848617 TEST=HDMI works on nereid Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I039c30f95d959dba489b24b6938d08da937c5e03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-04-01mb/google/brya/variants/baseboard/brask: Turn off NFC power in S0ixAlan Huang
Turn off the NFC power which is controlled by GPP_D3 to save power in S0ix states. For an USB device, the S0ix hook is needed for the on/off operations to take place. BUG=b:202737385 BRANCH=firmware-brya-14505.B TEST=measure the voltage of GPP_D3 in S0ix states Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Change-Id: I69588c82dfde1744c45c7aff3ac05b80bb16a8f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-01mb/google/brya/var/primus{4es}: Decrease touchscreen T3 timing to 200msCasper Chang
We set T3 as 300ms to meet Elan's spec, but the resume/suspend times are greater than 500ms, which is the spec for Chromebooks. The actual kernel timing has been measured, and given the ACPI delay after deasserting reset in addition to the delay until the kernel driver accesses the device, delaying only 200ms in the ACPI method is also sufficient to meet the 300ms requirement. BUG=b:223936777 BRANCH=none TEST=build and test touchscreen function on DUT. TEST=suspend, wake DUT and check touchscreen function. Change-Id: I6b04cf6392d924aed01ca36b720f889b88d92311 Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-01mb/google/brya/var/nereid: Enable AUX DC biasing on C0 and C1Reka Norman
C0 has no redriver, so enable SBU muxing in the SoC. C1 has a redriver which does SBU muxing, so disable SBU muxing in the SoC. However, this also disables AUX biasing when the pins are configured as NF6. So instead configure the C1 AUX bias pins as GPO. BUG=b:227259673 TEST=Voltages are correct on the C0 and C1 AUX bias pins Change-Id: Ic0af662ecc1c6cee15b4ae98cb02deeefc93a71e Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2022-03-31mb/google/brya/var/agah: Replace amp max98390 with max98360Tony Huang
Based on the latest schematic, agah will replace the Maxim 98390 speaker amps with Maxim max98360. This patch updates the devicetree entries to reflect that. BUG=b:210970640 BRANCH=brya TEST=emerge-draco coreboot Change-Id: I7ea36d276f7ffeae1510483027092e2bc59690fc Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-31mb/google/brya/var/agah: Add GL9750 SD card reader supportTony Huang
BUG=b:210970640 TEST=emerge-draco coreboot Change-Id: I881c2c1ad7b0d10b7ae38fcd9814f757cf56feb5 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-31mb/google/brya/var/kinox: set GPP_D0 to NCDtrain Hsu
Brask set GPP_D0 to GPO in commit b0769db4, but Kinox doesn't support fingerprint. This patch sets GPP_D0 to NC for matching schematic. BUG=b:214025396 BRANCH=firmware-brya-14505.B TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I38b9eb2df83cfbdb58d95cb178c1d767299aa4da Reviewed-on: https://review.coreboot.org/c/coreboot/+/63195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-03-30mb/google/brya/var/kano: Remove SAR sensorDavid Wu
RF team comfirmed that SAR sensor is not necessary for MP, therefore remove the corresponding entries from the devicetree. BUG=b:202978964 TEST=Build pass. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I31faf18563848f8d6787fe70bfb28006efea8427 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30mb/google/brya/variants/crota: Add memory config for crotaTerry Chen
Fill in the memory config based on the the schematic by bernadino 14 adl-p 20220112.pdf BUG=b:219891328 Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I981d2cd6feafee8c10ec9724a3dec9a23ba0ddd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30Revert "mb/google/brya/var/kano: adjust I2C3 speed"David Wu
This reverts commit 65aaccda5910e9c74aaa2a44ea84119d9476c902. Reason: 1. Fix firmware messages show [ERROR] dw_i2c:invalid bus speed 390000 2. Measure DVT I2C3 speed < 400KHz. BUG=b:215095284 TEST=There isn't ERROR messages and verify I2C3 speed < 400KHz. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I5982c82a55710824692b41e263418e4b4d420b02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30mb/google/brya/variants/crota: init overridetree for crotaTerry Chen
init overridetree.cb based on the schematic bernadino 14 adl-p 20220112.pdf BUG=b:226315394 Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: Ibca9d93a81469730e472a645c607a97a624e9a1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30mb/google/brya/var/banshee: Update the GPP_D12 as USB_C3_LSX_RXFrank Wu
Update the GPP_D12 according to USB_C3_LSX_RX. BUG=b:225081954 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage The device can be recognized when it is attached in port3. localhost /sys/bus/thunderbolt/devices # ls 0-0 1-0 1-0:3.1 1-3 domain0 domain1 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I38caa76c855e683eb0587eb67ee9abc91af4545d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-30mb/google/brya/var/taeko: Add new FW_CONFIG option for THERMAL for tarloJoey Peng
Add thermal table settings for tarlo which shares the same firmware with taeko BUG=b:215033683 TEST=emerge-brya coreboot Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I37f79cde502115bbf65bb97216eddb6ea22b1648 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30mb/google/nissa/var/nivviks: Move WWAN power on sequence forwardEric Lai
Move WWAN power on sequence from OS to coreboot. This can save the WWAN initial time about 10S. Another purpose is power resource be removed because we don't power off the LTE in S0ix. BUG=b:223490884 TEST=FM101-GL work as expected. Enumerate time from [ 17.747145] usb 4-2: new SuperSpeed USB device number 2 using xhci_hcd [ 17.760192] usb 4-2: New USB device found, idVendor=2cb7, idProduct=01a2, bcdDevice= 5.04 [ 17.760210] usb 4-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3 [ 17.760215] usb 4-2: Product: Fibocom FM101-GL Module [ 17.760220] usb 4-2: Manufacturer: Fibocom Wireless Inc. [ 17.760224] usb 4-2: SerialNumber: 9c88998f to [ 3.936409] usb 4-2: new SuperSpeed USB device number 2 using xhci_hcd [ 3.966695] usb 4-2: New USB device found, idVendor=2cb7, idProduct=01a2, bcdDevice= 5.04 [ 3.989989] usb 4-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3 [ 4.003813] usb 4-2: Product: Fibocom FM101-GL Module [ 4.019760] usb 4-2: Manufacturer: Fibocom Wireless Inc. [ 4.019762] usb 4-2: SerialNumber: 9c88998f Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I0f3fe999ae3a109b739629948b619a389a9059b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-03-30mb/google/brask/variants/moli: update GPIOs for moliRaihow Shi
Follow the Moli GPIO Table_20220324.xlsx to update it. 1.Set A15 as the default value. 2.Set A14, A19 NC. 3.Set C3, C4 as the default value. 4.Set D9 as the default value. 5.Set E5, E13 as the default value. 6.Set R4, R5 as the default value. 7.Update E14. 8.Set E12 as the default value. 9.Set D16 as the default value. BUG=b:220821454 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Ia54256244111a99cb130b74f78c37815099a021a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-30mb/google/brya/var/agah: Fix GPU GPIOsTim Wawrzynczak
While adding this train of patches to program the dGPU power sequences, I noticed some of the GPU GPIOs are incorrectly programmed in ramstage, so this patch fixes the settings. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I622b1f5cfba84727bb31792358ca4162c7fa9f52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-29mb/google/brya/var/felwinter: Update GPP_E19 from NF to NCJohn Su
Configure GPIO according to b:224107199 comment#15. - GPP_E19 from NF to NC. BUG=b:224107199 TEST=emerge-brya coreboot Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I06d02c5a8b6cf65d5643eaf30fb277c3321dac8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-03-27mb/google/brya/var/banshee: Add mic mute switch settingFrank Wu
Using the GPP_F22 as mic mute switch based on the latest schematic. BUG=b:223737606, b:216110896 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage The mic_mute event is changed when the mic_mute GPIO pin is switched. Event: time 1647939954.639995, type 5 (EV_SW), code 14 (SW_MUTE_DEVICE), value 0 Event: time 1647939954.639995, -------------- SYN_REPORT ------------ Event: time 1647939954.648152, type 5 (EV_SW), code 14 (SW_MUTE_DEVICE), value 1 Event: time 1647939954.648152, -------------- SYN_REPORT ------------ Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I6f7176afbd64f7c080f02369f195043a2df88e5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-03-27mb/google/brya/variants/baseboard/brask: set GPP_D0 to GPOZhuohao Lee
Currently, we control the GPP_D0 in the flash_fp_mcu in order to program the component's firmware. If we set this pin to NC, then we can't control the GPP_D0 output low/high and that make the system fails to program the component's firmware. This patch sets the GPP_D0 to GPO to fix it. BUG=b:204679292 BRANCH=firmware-brya-14505.B TEST=program the component's firmware Change-Id: I2f58c324f807a067dbe338f044a33dc9622ca469 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-03-27mb/google/brya/var/brya0: Replace amp max98357 with max98360Amanda Huang
Based on Brya EVT schametic, replace audio amp max98357 with max98360. Add a new audio FW_CONFIG field to support ALC5682I+MAX98360. BUG=b:224423056 BRANCH=firmware-brya-14505.B TEST=dmidecode -t 11 Change-Id: I3033e31cf5c2dade02dc19531f5e5365eeeb7a78 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-03-25mb/google/brya: Adjust FMD file to chromeos.fmd for kanoDavid Wu
The separate FMD file for Kano is no longer required, as it was only required for early prototype testers, and those devices will be retired soon, therefore switch back to the original FMD file. BUG=b:226018550 TEST=Build pass. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I09833039a450fa014e8e501bde9fec6e7ed59c7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-25drivers/i2c/tpm: Work around missing board_cfg in Ti50 FW under 0.15Eric Lai
Ti50 FW under 0.15 is not support board cfg command which causes I2C errors and entering recovery mode. And ODM stocks are 0.12 pre-flashed. Add workaround for the old Ti50 chip. BUG=b:224650720 TEST=no I2C errors in coreboot. [ERROR] cr50_i2c_read: Address write failed [INFO ] .I2C stop bit not received Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ieec7842ca66b4c690df04a400cebcf45138c745d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-03-24mb/google/brya/var/gimble: Include 4 new SPDsMark Hsieh
Add the four SPD files for LPDDD4 memory parts below to gimble: 1. Hynix H54G56CYRBX247 2. Hynix H54G46CYRBX267 3. Samsung K4UBE3D4AB-MGCL 4. Samsung K4U6E3S4AB-MGCL BUG=b:191574298 TEST=USE="project_gimble emerge-brya coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I143207cda066603051803b9008eb2e2364f16e46 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-23mb/google/brya/var/taniks: Increase TSR2 threshold from 40 °C to 70 °CJoey Peng
Change settings according to thermal team test results BUG=b:215033682 TEST=build and tested fan works normally on taniks Change-Id: I567815782ece4ab7fcec7da6b787ee9eec27aba4 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-23mb/google/brya/var/primus{4es}: add delay time to rtd3-coldTerry Chen
This CL adds the delay time into the RTD3 sequence, which will turn off the eMMC controller (a true D3cold state) during the RTD3 sequence.We checked power on sequence requires enable pin prior to reset pin, added delay to meet the sequence and test passed on various eMMC SKUs.Base on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2. BUG=b:224648680 TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage test suspend stress 2500 cycles passed on primus Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I1ab4fdf0ee73b819b3c203e995ac9d5ae0d24bd0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-22mb/google/brya/var/moli: Fix overridetreeTim Wawrzynczak
Commit 5a0ad1186 missed one chip config member that got converted to snake case in commit 215a97ee1. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ie92106f0fee0bb18863b7063c07673e0f7995c74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63005 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Martin L Roth <martinroth@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-22mb/google/brask/variants/moli: init overridetree for moliRaihow Shi
init overridetree.cb based on the schematic adl_rfq_mb_20220310.pdf BUG=b:220814038 Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I8829d4b39d48ae574eeccbfc62e79b671211ae2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-22mb/google/brya/variants/crota: set up gpioTerry Chen
Set the GPIO configuration of crota by bernadino 14 adl-p 20220112.pdf BUG=b:219891328 Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I164bc7a8b682eb8682f02b06708bc7c72a5c449a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-22mb/google/brya/var/kinox: Modify DDR4 to non-interleavedDtrain Hsu
Kinox is designed to 8-layer PCB. In order to reduce the length of memory singals, the DDR4 is designed from interleaved to non-interleaved. BUG=b:210094309 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I03c6fcccf8b1646cec1a35cc1f9cbb1cfb942c4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-22mb/google/brya/var/taeko: Disable GL9763e PCIE port L0sKevin Chang
GL9763e doesn’t support L0s state, so disable L0s at the root port. BUG=b:220079865 TEST=Build FW and run stress exceed 2500 cycles. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I6ed790c833d1c01a30aed0fd09cac260a3837ead Reviewed-on: https://review.coreboot.org/c/coreboot/+/62973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
2022-03-22mb/google/brya/var/taeko: Enable Genesys L1 max entry delayKevin Chang
The workaround causes the eMMC controller to not enter its L1 during the boot process BUG=b:220079865 TEST=Build FW and run stress exceed 2500 cycles. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I142a816611e204e6c8577d15b3f0a0e08251f848 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <martinroth@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
2022-03-21mb/google/brya/var/banshee: Add WiFi SAR tableFrank Wu
Add WiFi SAR table BUG=b:225285426 TEST=emerge-brya chromeos-config chromeos-config-bsp-private coreboot-private-files-baseboard-brya coreboot chromeos-bootimage and checked SAR table can load by WiFi driver. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I8fa833409bd69e080fda735c89015b9548252190 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-03-21mb/google/brya/vell: Move WWAN devices for vellRobert Chen
This was to merge PCIe ACPI code to WWAN device. Also, RTD3 devices are add to overridetree.cb where WWAN is present for vell. BUG=none BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Change-Id: If27abcf31ed948899bfaecbe8ef494fe8a80609b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-21mb/google/brya: Deselect ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTORSridhar Siricilla
The patch deselects ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR Kconfig which updates PMC settings in the IFD for Alder Lake A0 silicon. As Alder Lake A0 is intermediate stepping, and the IFD is locked in the production systems, so the Kconfig is deselected. BUG=b:190588098 BRANCH=firmware-brya-14505.B TEST=Build the coreboot for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I81fe7c792dd82d9d547d318ebda55ee4a0f3ac96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-18mb/google/brya/nivviks/overridetree: update tcss_aux_ori register nameFelix Held
Commit 215a97ee1c4cd87b266d63e32bf0b379e18fe849 (soc/intel/adl/chip.h: Convert all camel case variables to snake case) converted the camel case used in the parameter name to snake case, but commit bd529e2e200a8fbfd455dd62be0494a2b727b9a5 (mb/google/nissa/var/ nivviks: Add TcssAuxori for nivviks) still used the old names which breaks the upstream build. his patch is intended to be merged via fast-path before the 24h are over to fix the tree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2b9049553889c77bd8c59a2c4564d36d836a4eea Reviewed-on: https://review.coreboot.org/c/coreboot/+/62927 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-18mb/google/nissa/var/nivviks: Add TcssAuxori for nivviksUsha P
Enable SBU orientation handling by SoC for both USBC port0 and USBC port1. Nivviks USBC port0 do not have retimer, USBC port1 has redriver, but that do not flip the data lines. Hence we need to set bits for both the USBC ports. BRANCH:None TEST=emerge-nissa coreboot chromeos-bootimage. Flash the image on nivviks board and verified USBC display is working on both the ports in normal and inverted connections. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I219de6092ac9a9c773adbaa99f5a7d6196a2c937 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62731 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-18mb/google/brya/var/banshee: Replace amp max98357 with max98360Frank Wu
Based on the latest schematic, replace amp max98357 with max98360. BUG=b:224692387, b:216110896 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Id265a4276c3f8b5553a0e5d7ed824b1d9a520d44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62887 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-18mb/google/brya/var/volmar: Disable thunderboltRen Kuo
Volmar does not support Thunderbolt, therefore disable all of the TBT devices in the devicetree. The volmar fit image had been disabled already, cf. chrome-internal:4459289. BUG=b:2233193 TEST=Build and run on DUT. Change-Id: Ic1bba80707b1d4a97c486e22f79feccf6241865e Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-18mb/google/brya/var/kinox: Reconfigure GPIO settingsDtrain Hsu
Configure GPIOs according to updated schematics. - GPP_A21 from NC to TCP_DP1_CTRLCLK. - GPP_A22 from NC to TCP_DP1_CTRLDATA. - GPP_E22 from DDIA_DP_CTRLCLK to NC. - GPP_E23 from DDIA_DP_CTRLDATA to NC. BUG=b:214025396 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I9d2d73820fbb191b682713e4e351c6375927ddf4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-18mb/google/brya/var/vell: Change AMP driver settingShon Wang
1.Change I2S GPP_Sx (S0-S3) Native PAD Configuration from NF2 to NF4 2.Select CS35l53 AMP driver for Vell variant. Change-Id: I96d49bd1a2ba061c4fd52b450b31d0885f49552c Signed-off-by: Shon.Wang <shon.wang@quanta.corp-partner.google.com> Signed-off-by: Vitaly Rodionov <vitaly.rodionov@cirrus.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-17mb/google/brya: Remove mainboard.aslEric Lai
Use C code to generate MS0X entry and provide variant hook. BUG=b:207144468 TEST=check SSDT table has the same entry. Scope (\_SB) { Method (MS0X, 1, Serialized) { If ((Arg0 == One)) { \_SB.PCI0.CTXS (0x148) } Else { \_SB.PCI0.STXS (0x148) } } } Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ic36543e5cbaf8aaa7d933dcf54badc5f40e8ef02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-17mb/google/brya: Remove Pcie Generic driver for WWANCliff Huang
This was to merge PCIe ACPI code to WWAN device. But, now use recent _DSD generation changes in FM driver instead. PCie generic driver is not used for WWAN at this time. Also, RTD3 devices are moved to overridetree.cb where WWAN is present. BUG=b:221250331 BRANCH=firmware-brya-14505.B TEST= Check that _DSD is added to WWAN device in SSDT for the variants. Check that RTD3 is added to WWAN device in SSDT for the variants. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ia343c7545cf30bdbcd1de19e5eb84049dbb2977f Reviewed-on: https://review.coreboot.org/c/coreboot/+/62330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-17mb/google/brya/var/banshee: Update DPTF parametersFrank Wu
Follow thermal team design to update thermal table. BUG=b:223492897 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I5da776e7ae3368ce00cd29ec0ccdb5b7a725ff88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-03-17mb/google/brya/var/kinox: Modify 15W SOC power control settingDtrain Hsu
Modify 15W SOC default power settings for kinox. - PL2 39W - PL4 100W - Psys_PL2 65W - Psys_imax_ma 5000ma - bj_volts_mv 20000mv BUG=b:213417026, b:222599762 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I2956705f7d26929c7cf2dd4e852fc61b619a83e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62627 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-17mb/google/brask/variants/moli: set eMMC pin in bootblockRaihow Shi
1.Assert eMMC enable pin in bootblock 2.Deassert eMMC reset pin in bootblock BUG=b:220821454 Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I924fcdadaae8ed29b50369a55bad00983cf6ba19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-17mb/google/nissa/var/nivviks: Set gpio override to board_0Eric Lai
Follow the latest schematic change, gpio will match the baseboard. Return the current table as override. BUG=b:223677877 TEST=audio is functional on board_0. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I91dc2c9c8811d403c60a4b4f3a7c5ed8de4e527e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-03-16mb/google/brya/var/kinox: Enable PCIe-eMMC bridgeDtrain Hsu
Enable PCIe-eMMC bridge for Kinox. BUG=b:218786363, b:211176722 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Iec34708e5879c47f5339c48fd996eb6d7ef0ee86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-16mb/google/brya/var/kinox: Modify the DPTF/Fan parametersDtrain Hsu
Follow the Thermal_paramters_list-0314.xlsx to modify DPTF/Fan parameters. BUG=b:221180425, b:222020226, b:221182596 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I5f44120430029130d38b89d0eab6bbf205aca929 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-16mb/google/brya: set GPP_D0 to GPOMark Hsieh
Based on the schematic carbine_adl-p_dvt_20211104.pdf, the GPP_D0 is directly connected to FP module, Set GPP_D0 to GPO, DUT can flash FP firmware successfully. BUG=b:222188263, b:223906569 TEST=USE="project_gimble emerge-brya coreboot" and run the Fingerprint Firmware Test. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I164ffff6bd3b4058d6e28247eb7c3ed46d3891b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-15mb/google/brya/var/banshee: Add camera privacy settingFrank Wu
Using the GPP_F19 as privacy switch for camera in banshee. BUG=b:223712143, b:216110896 TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I67d65347ceac7152f1951018a633a2e93ee84e14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-03-15mb/google/brya: Disable C1-state auto demotion for Brya & BraskMAULIK V VAGHELA
C1-state auto demotion feature allows hardware to determine C1-state as per platform policy. Since Brya sets performance policy to balanced from hardware, auto demotion can be disabled without performance impact. Also, disabling this feature results in 110 mW power savings during video playback. Note that C1state Autodemotion feature is not applicable for ADL-P SoC. Hence recommendation is to keep it disabled. BUG=b:221876248 BRANCH=firmware-brya-14505.B TEST=Code compiles and correct value of c1-state auto demotion is passed to FSP. Also power and performance impact has been measure by respective teams. Change-Id: I41eea916cdfe4a86e4d263e3191f5cb40fa33a90 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-03-15soc/intel/adl/chip.h: Convert all camel case variables to snake caseMAULIK V VAGHELA
coreboot chip.h files mainly contains variable which allows board to fill platform configuration through devicetree. Since many of this configuration involves FSP UPDs, variable names were in camel case which aligned with UPD naming convention. By default coreboot follow snake case variable naming, so cleaning up file to align all variable names as per coreboot convention. During renaming process, this patch also removes unused variables listed below: -> SataEnable // Checked in SoC code based on PCI dev enabled status -> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used Note: Since separating out changes into smaller CL might break the compilation for the patch set, this is being pushed as a single big CL. BUG=None BRANCH=firmware-brya-14505.B TEST=All boards using ADL SoC compiles with the CL. Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-03-15{mb, soc}: Move mrc_cache invalidating logic into `memory` common codeSubrata Banik
Commit hash b8b40964 ( mb, soc: Add the SPD_CACHE_ENABLE) introduced per mainboard logic to invalidate the mrc_cache. This patch moves mrc_cache invalidating logic into IA common code and cleans up the code to remove unused argument `dimms_changed` from SoC and mainboard directory. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6f18e18adc6572571871dd6da1698186e4e3d671 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-15{mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototypeSubrata Banik
This patch modifies `memcfg_init` and `variant_memory_init`functions argument from FSP_M_CONFIG to FSPM_UPD. This change in `memcfg_init()` argument will help to update the architectural FSP-M UPDs from common code blocks rather than going into SoC and/or mainboard implementation. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-14mb/google/brya/var/primus{4es}: add eMMC enable pin in ramstageCasper Chang
Currently the BayHub eMMC enable pin is using the default configuration from the baseboard, which leads to RTD3 not being able to control the GPIO when exiting and entering suspend. To fix this, program the GPIO in the ramstage GPIO table. BUG=b:222436260 TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage scope enable pin while performing suspend stress and enable pin works as expected. test suspend stress 1000 cycles passed on primus. Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I1b6f164cc326bd368addb1e143ad2cbd449bb08d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14mb/google/brya/var/kinox: update overridetreeDtrain Hsu
1. Update override devicetree based on schematics. 2. ALC5682I-VS is for audio codec. BUG=b:218786363, b:214025396, b:212183045 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I08a1c2f784175b208ccdc562668041f432618dfc Reviewed-on: https://review.coreboot.org/c/coreboot/+/62553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14mb/google/brya: Set EPP to 45% for all Brya variantsCliff Huang
This sets EPP value to be 45% for all Brya variants. Historically, EPP Ratio has always been 50% (128) on Chrome platforms. But on Intel Alderlake EPP ratio of 45% is recommended for optimal power and performance on Chrome platforms. BUG=b:219785001 BRANCH=firmware-brya-14505.B TEST= Use 'iotools rdmsr [cpu id] 0x774' command and check field 32:24 = 0x73. Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: I973cfec72a0be24c56c4cd3283d2fe6e18400d02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14mb/google/nissa/var/nivviks: Hook up SD host controller GL9750Eric Lai
Select GL9750 driver and add power sequence according to datasheet: GL9750S-OIY04 rev1.22. BUG=b:223304292 TEST=check GL9750 can get enumerated by kernel 5.15. 01:00.0 SD Host controller: Genesys Logic, Inc Device 9750 (rev 01) Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ib6d461a56f6aeba30994daafe8993c36df4b309d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-03-14mb/google/nissa/var/nivviks: Enable pen garageEric Lai
Enable pen garage. Pen detect is active low. And wake system when eject. BUG=b:223476974 TEST=evtest work as expected. Input driver version is 1.0.1 Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100 Input device name: "PRP0001:00" Supported events: Event type 0 (EV_SYN) Event type 5 (EV_SW) Event code 15 (SW_PEN_INSERTED) state 0 Properties: Testing ... (interrupt to exit) Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1 Event: -------------- SYN_REPORT ------------ Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0 Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I2f676301c3372a4760853ce9c10b75f94e22bbcd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-10mb/google/brask/variants/moli: Change DDR4 Interleave to Non-Interleavezoey wu
The Brask DDR4 setting are interleave, due to Moli PCB layer limited and the routing need to smooth, we will use non-interleave for Moli DDR4. BUG=b:219831754 Signed-off-by: zoey wu <zoey_wu@wistron.corp-partner.google.com> Change-Id: Iab153f16a3b729e7fa9daaa3dbfbccc70e6d789d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-10mb/google/brask/variants/moli: Reduce PSysMax to 11 ARaihow Shi
Decrease PSysMax from 13.52 A to 11 A for Moli variant according to its power circuitry, implying Psys_Pmax = 11A * 19.5V = 214.5W BUG=b:215258941 Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I61f4813f3527123a590d80b4a6e49d76ebb71c99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-09drivers/wifi,soc/intel/adl: Move CnviDdrRfim property to driversTim Wawrzynczak
Some non-SoC code might want to know whether or not the CNVi DDR RFIM feature is enabled. Also note that future SoCs may also support this feature. To make the CnviDdrRfim property generic, move it from soc/intel/alderlake to drivers/wifi/generic instead. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Idf9fba0a79d1f431269be5851b026ed966600160 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
2022-03-09mb/google/brya/var/kano: Update TDP PL1, PL2, and PL4 for U28 SKUsDavid Wu
Based on testing results from the thermal team, they have decided to update PL1, PL2 and PL4 for U28 SKUs. BUG=b:221338290 TEST=Run with U28 and ensure the PL1/PL2/PL4 settings are correct Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ib82e2dbacd6cbc39390eb28f27ca9db48d6c215c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-03-09mb/google/brya/variants/felwinter: Fix stylus UI behavior bugJohn Su
Fix stylus UI behavior bug. 1) it appears the kernel's gpio_key driver is not expecting an IRQ descriptor for the `gpio` property, therefore change to an active-low input. 2) The wakeup event was configured backwards. Change list - Configure GPP_A7 as "ACPI_GPIO_INPUT_ACTIVE_LOW". - Change wakeup_event_action from ASSERTED to DEASSERTED. BUG=b:220992812 TEST=emerge-brya coreboot chromeos-bootimage and verify pass Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I6f5e2992584d759eb1a559684d1cda08c7cbe3f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-09mb/google/brya/var/redrix{4es}: Config VR_DOMAIN_GT's slew rate to 1/8Wisley Chen
Config VR_DOMAIN_GT's slew rate to 1/8 as well. BUG=b:204009588 TEST=build and verified by Power team. Change-Id: I766b828ad83710913323cf1485e09c1e0fd5e4c2 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-09mb/google/bry/anahera{4es}: Disable TCSS port1Wisley Chen
Disable unused TCSS Port1. BUG=b:223082190 TEST=Build Change-Id: I63f4b7d89a1e37a00c58201ecc88bb336d0932c9 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-09mb/google/brya/var/anahera{4es}: Configure Acoustic noise mitigationWisley Chen
Enable Acoustic noise mitigation and set slew rate to 1/8 BUG=b:223082189 TEST=build and verified by power team Change-Id: I256cc57fb54e5d62e22470a01e7efef359d57083 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-09mb/google/nissa: Add fmd file for nissaKrishna Prasad Bhat
Nissa boards are curretly using chromeos.fmd file of brya. The SPI flash layout for brya is of 32MB size, and nissa is expected to have 16MB SPI NOR flash. The current composition of AP firmware exceeds 16MB. To get an estimate of the unutilized region in the current flash layout for nissa, added RW_UNUSED regions. The idea is to reduce the AP firmware size to under 16MB and to remove the RW_UNUSED regions from the final fmd file. Below table gives the size reduction from brya fmd to nissa fmd: +----------------+-------------------+---------------+ | Region | Earlier size (KB) | New size (KB) | +================+===================+===============+ | SI_ME | 5116 | 3772 | +----------------+-------------------+---------------+ | RW_SECTION_A/B | 8192 | 4344 | +----------------+-------------------+---------------+ | VBLOCK_A/B | 64 | 8 | +----------------+-------------------+---------------+ | ME_RW_A/B* | 3008 | 1434 | +----------------+-------------------+---------------+ | RW_LEGACY | 2048 | 1024 | +----------------+-------------------+---------------+ | RW_ELOG | 16 | 4 | +----------------+-------------------+---------------+ | SHARED_DATA | 8 | 4 | +----------------+-------------------+---------------+ | VBLOCK_DEV | 8 | 0 | +----------------+-------------------+---------------+ | RW_SPD_CACHE | 4 | 0 | +----------------+-------------------+---------------+ | RW_NVRAM | 24 | 8 | +----------------+-------------------+---------------+ | WP_RO | 8192 | 4096 | +----------------+-------------------+---------------+ | GBB | 448 | 12 | +----------------+-------------------+---------------+ *Based on LZMA compression on ME_RW_A/B regions. With LZMA compression, this region can be 1434K. Without this, ~665K will be more in each of these regions. Patch: https://review.coreboot.org/c/coreboot/+/62358/ BUG=b:202783191 BRANCH=None TEST=Build and boot Nivviks. Cq-Depend: chrome-internal:4584911 Change-Id: I24b1c19cb71a54fc916a12668f72193f9689e755 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-03-09mb/google/nissa: Select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW KconfigKrishna Prasad Bhat
Change-Id: Ib27149c527015bd54f839994e047f815e8922dc4 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-08mb/google/brask/variants/moli: set up gpioRaihow Shi
Set the GPIO configuration of moli BUG=b:220821454 Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I7ec41cb843419c32337b66f3877eda5d730cea35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-08mb/google/brya/var/nivviks: Change bluetooth USB2 port from 8 to 10Reka Norman
When using CNVi WLAN on ADL-N, the internal USB2 port 10 is used for bluetooth. So update the nivviks overridetree to enable port 10 instead of port 8, which is the external port used for bluetooth with PCIe WLAN. BUG=b:222595137 TEST=Bluetooth works on nivviks Change-Id: Ica2067023125c04fc753eabc944ae29ff59dc864 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2022-03-08mb/google/brya/var/primus{4es}: add enable pin to rtd3-coldCasper Chang
Currently the BayHub eMMC controller is only going into its reset state when the RTD3 sequence is initiated. This causes it to still consume too much power in suspend states. This CL adds the power enable GPIO into the RTD3 sequence as well, which will turn off the eMMC controller (a true D3cold state) during the RTD3 sequence. BUG=b:222436260 TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage test suspend stress 100 cycles passed on primus. Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I2fec6a30707fb1a258cdcc73b0ce38252b6f77c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-07mb/google/brya: Enable GPIO PM dynamically based on cr50 FW versionTim Wawrzynczak
cr50 firmware revisions starting at 0.5.5 and later are able to extend their IRQ pulses to be a minimum of 100us long. This change will enable cr50 long interrupt pulses when it detects the feature is supported by the detected firmware version. If the capability was detected, then GPIO PM will be enabled for the device, otherwise it will be disabled. BUG=b:202246591 TEST=boot brya0, check console logs for the correct message, and verify the GPIO PM registers. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iaf333dc0f177e17cd03b36ec7e487fc33bde2b93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61722 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-07mb/google/brya/var/taniks: Add GL9750 SD card reader supportJoey Peng
Add GL9750 SD card reader support. BUG=b:222402409 TEST=Build FW and check device function normally. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ied36719914de214ae7d810f3d03a508e95fbf66a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-07mb/google/brya/var/redrix{4es}: Disable TCSS PCIe port1Wisley Chen
Disable unused TCSS PCIe port1 BUG=b:217238553 TEST=FW_NAME=redrix emerge-brya coreboot chromeos-bootimage Change-Id: I2bdfdb23d010a1e24c986ab52b5cef6eedcb674e Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-07mb/google/brya/vell: Enable USB2 port for KBD MCUDaisuke Nojiri
Vell has a keyboard MCU connected to USB2 port 7. This patch enables the port. localhost# usb_updater2 -f Found device. found interface 0 endpoint 1, chunk_len 64 READY ------- start target running protocol version 6 (type 1) maximum PDU size: 4096 Flash protection status: 0000 version: prism_v2.0.12137+c4ae1432f5 key_version: 1 min_rollback: 0 offset: writable at 0xc000 Current versions: Writable prism_v2.0.12137+c4ae1432f5 BUG=b:203664745,b:211496726 TEST=Run 'usb_updater2 -f' on Vell. Change-Id: Iad2140dbdf5e34332388f3f43b3ede3d22e73087 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-07mb/google/brya/var/{brya*,redrix*}: Add DmaProperty for WWANTim Wawrzynczak
ChromeOS considers the WWAN devices to be untrusted, therefore enable the new DmaProperty in the WWAN's _DSD to indicate to the OS that these devices should have IOMMU restrictions applied to them. BUG=b:215424986 BRANCH=brya TEST=dump SSDT Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I9c9e73b7ea0575ab87cc980fb4786338047155de Reviewed-on: https://review.coreboot.org/c/coreboot/+/62437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-03-07mb/google/brya/var/redrix{4es}: Re-enable USB2 port for BluetoothWisley Chen
BT didn't work due to commit 03c0853f4d58c73. Commit 03c0853f4d58c73 accidentally set the Bluetooth USB2 port to "empty", therefore re-enable USB2 port 9. BUG=b:217238553, b:222238381 TEST=build and verfied BT work/suspend successfully Change-Id: Ie94ef847fc130019f1e06983fc5039f1f564cd3a Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-07mb/google/brya: Move ACPI MPTS method from DSDT to SSDT for Brya and RedrixCliff Huang
This change is to move MPTS (Mainboard Prepare To Sleep) method from wwan_power.asl to SSDT. MPTS is mainboard-specific method, while wwan_power.asl is meant for WWAN from its name. Having fixed MPTS method (i.e. DSDT) can not cover the case where device only presents and certain CBI bit(s) is(are) set. In Redrix and Brya, there are SKUs with or without 5G, 4G device. For those with 4G, MPTS method should be different. For those with no WWAN device, no MPTS is needed. Having MPTS generating in SSDT also eliminates the need for introducing Kconfig flags to support different devices in the future. MPTS method is created inside mainboard_fill_ssdt function in which the corresponding variant function is called. This will generate the following for the mainboard: Scope (\_SB) { Method (MPTS, 1, Serialized) { Local0 = \_SB.PCI0.RP01.RTD3._STA () If ((Local0 == One)) { \_SB.PCI0.RP01.PXSX.DPTS (Arg0) } } } Test: Check the SSDT for MPTS method under \_SB after boot to OS Use shutdown command and check the GPIO pins from logical analyzer Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I0f0b7638e90a7862173fca99305398bb250373e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-07src: Make PCI ID define names shorterFelix Singer
Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with PCI_{DID,VID}_ using the commands below, which also take care of some spacing issues. An additional clean up of pci_ids.h is done in CB:61531. Used commands: * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g' * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g' Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-14 07:17:44 +0000