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authorTerry Chen <terry_chen@wistron.corp-partner.google.com>2022-03-16 17:19:09 +0800
committerTim Wawrzynczak <twawrzynczak@chromium.org>2022-03-22 19:01:25 +0000
commitf613ce04791e5253d1df94f9a236e4f2014f2fc6 (patch)
treed63896ef1c6a0ad2470b03e5269aaff5ca3323fa /src/mainboard/google/brya
parent390a28057cddc89995c23aa75f8abc4b6cf44028 (diff)
mb/google/brya/variants/crota: set up gpio
Set the GPIO configuration of crota by bernadino 14 adl-p 20220112.pdf BUG=b:219891328 Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I164bc7a8b682eb8682f02b06708bc7c72a5c449a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya')
-rw-r--r--src/mainboard/google/brya/variants/crota/Makefile.inc5
-rw-r--r--src/mainboard/google/brya/variants/crota/gpio.c167
2 files changed, 172 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/crota/Makefile.inc b/src/mainboard/google/brya/variants/crota/Makefile.inc
new file mode 100644
index 0000000000..6c29346470
--- /dev/null
+++ b/src/mainboard/google/brya/variants/crota/Makefile.inc
@@ -0,0 +1,5 @@
+bootblock-y += gpio.c
+
+romstage-y += gpio.c
+
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/brya/variants/crota/gpio.c b/src/mainboard/google/brya/variants/crota/gpio.c
new file mode 100644
index 0000000000..ad13426b16
--- /dev/null
+++ b/src/mainboard/google/brya/variants/crota/gpio.c
@@ -0,0 +1,167 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config override_gpio_table[] = {
+ /* A19 : DDSP_HPD1 ==> NC */
+ PAD_NC(GPP_A19, NONE),
+ /* A20 : DDSP_HPD2 ==> NC */
+ PAD_NC(GPP_A20, NONE),
+ /* A21 : DDPC_CTRCLK ==> NC */
+ PAD_NC(GPP_A21, NONE),
+ /* A22 : DDPC_CTRLDATA ==> NC */
+ PAD_NC(GPP_A22, NONE),
+
+ /* C3 : SML0CLK ==> SML0_SMBCLK */
+ PAD_CFG_GPO(GPP_C3, 0, DEEP),
+ /* C4 : SML0DATA ==> SML0_SMBDATA */
+ PAD_CFG_GPO(GPP_C4, 0, DEEP),
+
+ /* D3 : ISH_GP3 ==> NC */
+ PAD_NC(GPP_D3, NONE),
+ /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+ /* D6 : SRCCLKREQ1# ==> EMMC_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+ /* D13 : ISH_UART0_RXD ==> NC */
+ PAD_NC(GPP_D13, NONE),
+ /* D14 : ISH_UART0_TXD ==> NC */
+ PAD_NC(GPP_D14, NONE),
+ /* D15 : ISH_UART0_RTS# ==> NC */
+ PAD_NC(GPP_D15, NONE),
+ /* D19 : I2S_MCLK1_OUT ==> NC */
+ PAD_NC(GPP_D19, NONE),
+
+ /* E3 : PROC_GP0 ==> NC */
+ PAD_NC(GPP_E3, NONE),
+ /* E5 : SATA_DEVSLP1 ==> NC */
+ PAD_NC(GPP_E5, NONE),
+ /* E7 : PROC_GP1 ==> NC */
+ PAD_NC(GPP_E7, NONE),
+ /* E20 : DDP2_CTRLCLK ==> NC */
+ PAD_NC(GPP_E20, NONE),
+ /* E21 : DDP2_CTRLDATA ==> NC */
+ PAD_NC(GPP_E21, NONE),
+ /* E22 : DDPA_CTRLCLK ==> NC */
+ PAD_NC(GPP_E22, NONE),
+ /* E23 : DDPA_CTRLDATA ==> NC */
+ PAD_NC(GPP_E23, NONE),
+
+ /* F20 : EXT_PWR_GATE# ==> NC */
+ PAD_NC(GPP_F20, NONE),
+
+ /* H21 : IMGCLKOUT2 ==> VPRO_STRAP */
+ PAD_CFG_GPI(GPP_H21, NONE, DEEP),
+ /* H22 : IMGCLKOUT3 ==> NC */
+ PAD_NC(GPP_H22, NONE),
+
+ /* R4 : HDA_RST# ==> DMIC_CLK0_R */
+ PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),
+ /* R5 : HDA_SDI1 ==> DMIC_DATA0_R */
+ PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
+ /* R6 : I2S2_TXD ==> NC */
+ PAD_NC(GPP_R6, NONE),
+ /* R7 : I2S2_RXD ==> NC */
+ PAD_NC(GPP_R7, NONE),
+
+ /* S0 : SNDW0_CLK ==> I2S_SPKR_SCLK_R */
+ PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4),
+ /* S1 : SNDW0_DATA ==> I2S_SPKR_SFRM_R */
+ PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4),
+ /* S2 : SNDW1_CLK ==> I2S_PCH_TX_SPKR_RX_R */
+ PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4),
+ /* S3 : SNDW1_DATA ==> I2S_PCH_RX_SPKR_TX */
+ PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4),
+ /* S4 : SNDW2_CLK ==> NC */
+ PAD_NC(GPP_S4, NONE),
+ /* S5 : SNDW2_DATA ==> NC */
+ PAD_NC(GPP_S5, NONE),
+ /* S6 : SNDW3_CLK ==> NC */
+ PAD_NC(GPP_S6, NONE),
+ /* S7 : SNDW3_DATA ==> NC */
+ PAD_NC(GPP_S7, NONE),
+
+ /* T2 : GPP_T2 ==> eMMC_CFG */
+ PAD_CFG_GPI(GPP_T2, NONE, DEEP),
+
+ /* GPD11: LANPHYC ==> NC */
+ PAD_NC(GPD11, NONE),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+ /* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */
+ PAD_CFG_GPO(GPP_A12, 1, DEEP),
+ /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
+ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+ /* B3 : PROC_GP2 ==> eMMC_PERST_L */
+ PAD_CFG_GPO(GPP_B3, 0, DEEP),
+ /* B4 : PROC_GP3 ==> SSD_PERST_L */
+ PAD_CFG_GPO(GPP_B4, 0, DEEP),
+ /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */
+ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+ /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */
+ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+ /*
+ * D1 : ISH_GP1 ==> FP_RST_ODL
+ * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
+ * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
+ * early on in bootblock, followed by enabling of power. Reset signal is deasserted
+ * later on in ramstage. Since reset signal is asserted in bootblock, it results in
+ * FPMCU not working after a S3 resume. This is a known issue.
+ */
+ PAD_CFG_GPO(GPP_D1, 0, DEEP),
+ /* D2 : ISH_GP2 ==> EN_FP_PWR */
+ PAD_CFG_GPO(GPP_D2, 1, DEEP),
+ /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
+ PAD_CFG_GPO(GPP_D11, 1, DEEP),
+ /* D18 : UART1_TXD ==> SD_PE_RST_L */
+ PAD_CFG_GPO(GPP_D18, 0, PLTRST),
+ /* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */
+ PAD_CFG_GPO(GPP_E0, 0, DEEP),
+ /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
+ PAD_CFG_GPI(GPP_E13, NONE, DEEP),
+ /* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */
+ PAD_CFG_GPO(GPP_E16, 0, DEEP),
+ /* E15 : RSVD_TP ==> PCH_WP_OD */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
+ /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+ PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+ /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */
+ PAD_CFG_GPO(GPP_F21, 0, DEEP),
+ /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
+ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+ /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
+ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+ /* H13 : I2C7_SCL ==> EN_PP3300_SD */
+ PAD_CFG_GPO(GPP_H13, 1, PLTRST),
+};
+
+static const struct pad_config romstage_gpio_table[] = {
+ /* B4 : PROC_GP3 ==> SSD_PERST_L */
+ PAD_CFG_GPO(GPP_B4, 1, DEEP),
+ /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
+ PAD_CFG_GPO(GPP_F21, 1, DEEP),
+};
+
+const struct pad_config *variant_gpio_override_table(size_t *num)
+{
+ *num = ARRAY_SIZE(override_gpio_table);
+ return override_gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(early_gpio_table);
+ return early_gpio_table;
+}
+
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(romstage_gpio_table);
+ return romstage_gpio_table;
+}