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2021-12-24mb/google/taniks,vell;mb/intel/adlrvp_n_ext_ec: fix build errorFelix Held
Commit d448f8ce0fe9955e7792f54cc278897152d53590 (drivers/intel/pmc_mux/ conn: Change usb{23}_port_number fields to device pointers) changed the way the pmc_mux/conn driver gets the corresponding USB ports from the devicetree. This change didn't include the corresponding change for the Taniks and Vell variants of the Google Brya project and the Intel adlrvp_n_ext_ec board which probably weren't in the tree at the time the patch referenced above was created. This patch ports the needed change forward to those boards to fix the build of the upstream tree. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id295cd11fbbfe038534b154215a6de7c1ac13e0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/60329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-12-23ChromeOS: Refactor ACPI CNVS generationKyösti Mälkki
Remove chromeos_dsdt_generator() calls under mainboard, it is possible to make the single call to fill \CNVS and \OIPG without leveraging device operations. Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-23mb/google/brya/var/taniks: Include driver for GL9763E for eMMC boot diskJoey Peng
Support GL9763E as a eMMC boot disk BUG=b:210089379 TEST=enable DRIVERS_GENESYSLOGIC_GL9763E and check eMMC on taniks. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Iab0fd88ac88e07a8580426234adc9c21df6c11d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-23mb/google/brya/var/brask: Customize LEDs of RT8125Rory Liu
Add Kconfig item RT8168_SET_LED_MODE to enable LED customization. Update the LED settings in devicetree. BUG=b:193750191 TEST=Try different register values to verify LED feature. Signed-off-by: Rory Liu <rory.liu@quanta.corp-partner.google.com> Change-Id: If80ace497c7481ce40b55af7e17e12a286aa9164 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-23mb/google/brya/var/vell: Add Hynix LP5 DRAM supportKevin Chiu
Add Hynix H9JCNNNCP3MLYR-N6E LP5 DRAM part for vell: DRAM Part Name ID to assign H9JCNNNCP3MLYR-N6E 1 (0001) BUG=b:204284866 TEST=emerge-brya coreboot Change-Id: I1ec2985fa1f1c488ee3a9c5e34f7b370d16cf98e Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-23mb/google/brya/variants/primus: remove board_id check for ALC5682I-VSMalik_Hsu
The board ID check for audio codec is no longer required, therefore remove it. BUG=b:210705216 TEST=emerge-brya coreboot chromeos-bootimage and check audio function Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: Ifbe838186da2e64737a9ffb557cf324124e79a9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/60128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-23mb/google/brya/var/gimble4es: Configure Acoustic noise mitigationMark Hsieh
- Enable Acoustic noise mitigation - Copied from gimble set slow slew rate VCCIA and VCCGT to 8 BUG=b:206704930 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I156859ce6894a6ed5270fe0242de4aef9656bbeb Reviewed-on: https://review.coreboot.org/c/coreboot/+/59949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-23mb/google/brya/var/anahera: Enable SaGvWisley Chen
Enable SaGv support for anahera/anahera4es. BUG=b:211362081 TEST=FW_NAME=anahera emerge-brya coreboot Change-Id: I68c916dbc570759dba3a4c32fbb8ebfc6e387be4 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-23mb/google/brya/var/taeko4es: Fix PLD group order (W/A)Joey Peng
In commit 667471b8d8 (ec/google/chromeec: Add PLD to EC conn in ACPI table), PLD is added to ACPI table. It causes the DUT to not boot into the OS. So fix the USB3/USB2 Type-C Port C2 PLD group order from 3 to 2 to solve this issue. Fixes: 667471b8d8 ("ec/google/chromeec: Add PLD to EC conn in ACPI table") BUG=b:209723556 BRANCH=none TEST=build coreboot and boot into OS. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Iff1302fa758bcde1ce8b03c16f7cc6eac807e5c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60187 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-23drivers/intel/pmc_mux/conn: Change usb{23}_port_number fields to device pointersReka Norman
Currently, the pmc_mux/conn driver uses integer fields to store the USB-2 and USB-3 port numbers from the SoC's point of view. Specifying these as integers in the devicetree is error-prone, and this information can instead be represented using pointers to the USB-2 and USB-3 devices. The port numbers can then be obtained from the paths of the linked devices, i.e. dev->path.usb.port_id. Modify the driver to store device pointers instead of integer port numbers, and update all devicetrees using the driver. These are the mainboards affected (all are Intel TGL or ADL based): google/brya google/volteer intel/adlrvp intel/shadowmountain intel/tglrvp system76/darp7 system76/galp5 system76/lemp10 Command used to update the devicetrees: git grep -l "usb._port_number" src/mainboard/ | \ xargs sed -i \ -e 's/register "usb2_port_number" = "\(.*\)"/use usb2_port\1 as usb2_port/g' \ -e 's/register "usb3_port_number" = "\(.*\)"/use tcss_usb3_port\1 as usb3_port/g' BUG=b:208502191 TEST=Build test all affected boards. On brya0, boot device and check that the ACPI tables generated with and without the change are the same. Change-Id: I5045b8ea57e8ca6f9ebd7d68a19486736b7e2809 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-12-23mb/google/brya/var/vell: update overridetree for SSD setting=
Change CLKSRC#3 to CLKSRC#1 in override devicetree based on schematics BUG=b:208756696 TEST=emerge-brya coreboot Change-Id: I4d452eaa690a91814739cc1b80966fc3a9f1be37 Signed-off-by: = <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-23mb/google/brya/var/vell: update overridetree for touchpad=
update override devicetree for touchpad based on schematics BUG=b:209554950 TEST=emerge-brya coreboot Change-Id: I835958349537ed490191db7c8e35847630de64ed Signed-off-by: = <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-22mb/google/brya/var/taeko: Enable Bayhub LV2 driverTim Wawrzynczak
Some SKUs of google/taeko have a Bayhub LV2 card reader chip, therefore enable the corresponding driver for the mainboard. BUG=b:204343849 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I738af7e77a3c076742a3d6c6f48fad29dfc978ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/60017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-22mb/google/brya/var/gimble: Configure GPIO to release PERST# earlierMark Hsieh
This change in power sequencing appears to fix issues with power consumption of the SD card controller. Possibly this change ensures the device has enough time to properly initialize itself after reset is deasserted but before it is accessed. BUG=b:206014046 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I90e5dd074ceda365283fe7e1f43dfd8c692d7338 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-21mb/google/brya/variant/taniks: Add devicetree settingsJoey Peng
Based on schematic G570_MB_CHROME_1207_1630_ADC and gpio table of taniks, generate overridetree.cb settings for taniks. BUG=b:209926534 TEST=FW_NAME=taniks emerge-brya coreboot chromeos-bootimage Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ib333150117832480f70fbe13bdbdf2982a7f70e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-20mb/google/brya/var/brask: Add wake-on-lan functionRory Liu
Add a wake-on-lan GPIO in devicetree for RTL8125. Modify GPIO A7 for wake-on-lan. BUG=b:204289108 TEST=emerge-brask coreboot chromeos-bootimage Signed-off-by: Rory Liu <rory.liu@quanta.corp-partner.google.com> Change-Id: Ic40301888a138df4a67398485f2a484d69b83fc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-20mb/google/brya/var/vell: update memory settingsShon Wang
DQ/DQS info from Intel_Platform_DQ_DQS_RCOMP_Info_Utility GPIO_MEN_CONFIG_0 GPP_E11 to GPP_E3 GPIO_MEN_CONFIG_3 GPP_E12 to GPP_E7 GPIO_MEM_CH_SEL_GPP_E5 GPP_E13 to GPP_E5 BUG=b:205908918 TEST=emerge-brya coreboot Change-Id: Ic0bbac5eaebc77639be6c1bc399658ac90e72fbb Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-20mb/google/brya/var/vell: update gpio overrideKevin Chiu
Configure GPIOs according to schematics BUG=b:205908918 TEST=emerge-brya coreboot Change-Id: Icc91866f7555c294af7eed9e5d1550e73d8059d0 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-20mb/google/brya/var/*: Add disable_gpio_export_in_crs to all devicetreesTim Wawrzynczak
None of the touchscreens used in the brya program (any brya board) should require exporting of GPIOs in the ACPI _CRS method for any i2c device. This can cause i2c devices to malfunction or cause timing sequence violations if: 1) ACPI exports a PowerResource for the device that uses GPIOs that are also exported in _CRS 2) The kernel driver for the device uses the GPIOs exported in _CRS for its own purposes. This means the state of the pin is out of sync between platform firmware and the kernel. The Linux ELAN I2C touchcsreen driver (https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/upstream/drivers/input/touchscreen/elants_i2c.c;l=1429) is one example of this. Therefore, add disable_gpio_export_in_crs to all brya variants that use the drivers/i2c/generic or drivers/i2c/hid chip drivers. Change-Id: Ib4475bd0dc885e230911de6298fd95baa868ef29 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-20mb/google/brya/var/primus: Update thermal table for primusAriel_Fang
- Because primus have five sensors,we need to define 5 sensors. BUG=b:200836803 TEST=USE="project_primus emerge-brya coreboot" and verify it builds without error. Signed-off-by: Ariel_Fang <ariel_fang@wistron.corp-partner.google.com> Change-Id: I02fb8eee644f9999d9c5d48e3a056499d968f85d Reviewed-on: https://review.coreboot.org/c/coreboot/+/60101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-20mb/google/brya/variants/brask: Disable autonomous GPIO power managementZhuohao Lee
We experienced the `Cr50 i2c TPM IRQ timeout!` error when the device executed the reboot test even though we have updated the Cr50 firmware to the latest version 0.6.70. Besides, we also experienced the device failed with the IRQ timeout when using the 0.3.22 Cr50 firmware in the factory. In order to fix these issues, we disable the gpio power management from the devicetree. BUG=b:210540890 TEST=reboot 100 cycles without the error message. Change-Id: I5f18fea5bc28493107c6d4951805de640a0b8ae5 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-16mb/google/brya/var/felwinter: Add stylus probe for garageEric Lai
Felwinter has non-stylus sku. Add a FW_CONFIG field to indicate stylus presence and add a probe statement to the devicetree for the corresponding device. BUG=b:208937710 TEST=non-stylus doesn't register garage driver. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I06a2c125f2b5a73f9f7c27bf1b20ff8712664809 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-16mb/google/brya/var/vell: update overridetreeKevin Chiu
Init basic override devicetree based on initial schematics BUG=b:205908918 TEST=emerge-brya coreboot Change-Id: Ibaa910eb1c5584197907963781258035c668298e Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-15mb/google/brya/var/primus{4es}: Configure Acoustic noise mitigationCasper Chang
- Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to 8 BUG=b:204844399 TEST=USE="project_primus emerge-brya coreboot" and verified the setting meets the audible noise specification Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I0e0baf78a841278efda912cc5e4e9970329aacf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-15mb/google/brya/var/taniks: Configure DRIVER_TPM_I2C_BUSJoey Peng
Add I2C bus for taniks in Kconfig BUG=b:210390520 TEST=emerge-brya coreboot and can boot to OS. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I9b1719c3140c13f67e7cb0e6a69257774884bd4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/60077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-15mb/google/brya/variant/taniks: Add memory settingsJoey Peng
Based on the Taniks's schematic, generate memory settings. Schematic version is G570_MB_CHROME_1207_1630_ADC. BUG=b:209531192,b:209553289 TEST=FW_NAME=taniks emerge-brya coreboot chromeos-bootimage Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I0c0794fb94d1f6271de604835ae1d2b20696ee70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-15mb/google/brya/variants/taniks: Configure GPIOs according to schematicsJoey Peng
Add initial gpio configuration for taniks according to schematics G570_MB_CHROME_1207_1630_ADC. The schematics reserved HPS and FP but taniks doesn't use them, so set FP and HPS related pins to NC. BUG=b:209492408, b:209553289 TEST=FW_NAME=taniks emerge-brya coreboot Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ic5c4ead4ad59137e1764e1226415ab6041c68aab Reviewed-on: https://review.coreboot.org/c/coreboot/+/59938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-10mb/google/brya/var/taeko: Fix PLD group order (W/A)Kevin Chang
In commit 667471b8d8 (ec/google/chromeec: Add PLD to EC conn in ACPI table), PLD is added to ACPI table. It causes the DUT to not boot into the OS. So fix the USB3/USB2 Type-C Port C2 PLD group order from 3 to 2 to solve this issue. Fixes: 667471b8d8 ("ec/google/chromeec: Add PLD to EC conn in ACPI table") BUG=b:209723556 BRANCH=none TEST=build coreboot and boot into OS. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: Ia4cf2d735de524ae721800600536923d1d47f04b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-10mb/var/gimble4es: Set PsysPmax to 143 WMark Hsieh
This patch adds the setting of PsysPmax to 143 W according to gimble board design. BUG=b:206990759 TEST=emerge-brya coreboot chromeos-bootimage & ensure the value is passed to FSP by enabling FSP log & Boot into the OS Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I851e0871461a9a9769c6b84f7d8287d989c23f06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09mb/google/brya4es: sync change from brya0 (CB:58374)YH Lin
CB:58374 (for mb/google/brya0) was merged before brya4es is available (CB:59728). And since brya4es is forked from brya0, brya0's change need to be brought into brya4es as well. BUG=b:203014972 TEST=build Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: I97489343b8f7a5b9457cd6f4a61cc37cd10ab450 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09mb/google/brya/var/brask: Configure the ISOLATE pin of LANAlan Huang
1. Copy the default configuration from Puff. 2. Update the 'stop_gpio' to GPP_H22. BUG=b:193750191 BRANCH=None TEST=Update kernel for 8125 outbox driver and test with command suspend_stress_test. Change-Id: I2e82dbc1e6c68cbd84b603adc7fdc3ee1d4d3392 Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09mb/google/brya/var/redrix4es: sync change from redrixYH Lin
The original change was for mb/google/redrix (commit 0167f5adbb), "The ChromeOS kernel platform driver is adding support for a ChromeOS privacy screen device, and in order to locate that device, the driver uses the GOOG0010 reserved HID for this" But it was merged before redrix4es is available. As redrix4es is forked from redrix, relevant change in redrix need to be brought into redrix4es as well. BUG=b:206850071 TEST=build Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: I5ac90c249273bf4e75cccb5889844a7f196f56fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/59987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09mb/google/brya: keep the same TPM I2C for 4ES variantsYH Lin
Since 4ES variants were forked from their own original variants, use the same TPM I2C as well. BRANCH=none BUG=b:201767461 TEST=emerge-brya coreboot and check the artifacts Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: Iddd6d8c22a181aba596b836f20392f76539b8549 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-08mb/google/brya/var/primus: Fix PLD group orderScott Chao
In ec/google/chromeec: Add PLD to EC conn in ACPI table(667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. It causes the DUT to not boot into the OS. So fix the USB3/USB2 Type-C Port C2 PLD group order from 3 to 2 to solve this issue. BUG=b:209568644 BRANCH=none TEST=build coreboot and system boot into OS. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: If5ce6ca061d9d56ba0bbb1f157b2ba278d3fa9c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59953 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-07mb/google/brya: add list of gpios to lockNick Vaccaro
Add a list of gpios to lock for brya. This currently includes GPIOs connected to the FPMCU. BUG=b:201430600 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that brya0 boots successfully to kernel. Change-Id: Idea42a58575c280be0770d38f934acdf5508c45d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-06mb/google/brya/var/gimble: Configure Acoustic noise mitigationMark Hsieh
- Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to 16 BUG=b:206704930 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I2be3d30403284b98276c837adefd91aa62c971e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59535 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-06mb/google/brya/var/redrix: Swap TPM I2C with touchscreen I2CWisley Chen
According to the latest schematic, exchange I2C port for TPM/touchscreen. TPM: I2C3 -> I2C1 Touchscreen: I2C1 -> I2C3 BUG=b:205648040 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I3a8339c23522019da884944246427512170510b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-06mb/var/gimble: Set PsysPmax to 143 WChia-Ling Hou
This patch adds the setting of PsysPmax to 143 W according to gimble board design. BUG=b:206990759 TEST=emerge-brya coreboot chromeos-bootimage & ensure the value is passed to FSP by enabling FSP log & Boot into the OS Change-Id: Id6a203f05ecfcc1020a422850d35fa3fa64e01d0 Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ryan Lin <ryan.lin@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-06mb/google/brya/var/felwinter: Correct garage wake eventEric Lai
Eject event is high. Set wake event to active high. The polarity of the SCI and the wakeup_event_action for the pen ejection feature were both backwards, and was causing the system to fail to enter sleep states because the event was always asserted. BUG=b:208937710 TEST=only release switch can wake system. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I568e9175c7a66599f7a525c32e4def7a79b55a0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/59861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03mb/google/brya/var/felwinter: Add WiFi SAR table for felwinterIan Feng
Add WiFi SAR table for felwinter. BUG=b:206901900 TEST=emerge-brya chromeos-config chromeos-config-bsp-private coreboot-private-files-baseboard-brya coreboot chromeos-bootimage and checked SAR table can load by WiFi driver. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I0de710f4447302ee545a67cbd79373bdd2077637 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-12-03mb/google/brya: Update camera NVM parametersBernardo Perez Priego
Change HID name from INT3499 to PRP0001 along with size and address width. Size decreased from 10K to 2K, address width decreased from 14 to 8. BUG=b:203014972 Test= Boot board and issue commands: `cat /sys/bus/i2c/devices/i2c-PRP0001:02/eeprom > ./brya_imx208_eeprom.bin` `hexdump -C brya_imx208_eeprom.bin > brya_imx208_eeprom_dump.log` You should see the result in brya_imx208_eeprom_dump.log to be same as module nvm file by vendor provided or meet the Intel nvm calibration format. (e.g. first 4 bytes be 0x01, 0x03, 0x01, 0x00) Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Ib2366ba4c8bb70d8cc82e64ca585b118a96260c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03mb/google/brya/var/brask: Enable LAN driver to program MACAlan Huang
Turn on the LAN device in devicetree and add Kconfig item RT8168_GET_MAC_FROM_VPD to support programming MAC address. BUG=b:193750191 BRANCH=None TEST=Use 'vpd -s ethernet_mac0=...' to write MAC to VPD. Use 'ifconfig' to check if the MAC written successfully. Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Change-Id: Ibb95b02fd6d61621ef46db4d63b48456a0a72732 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03mb/google/brya/var/brask: Set vGPIO reset typeKane Chen
Due to the vGPIO is not reset when we power on through S5, we would met MCA when PCIE send L1 request without following Ack BUG=b:207625007 TEST=S0->S3->S5->power key->S3->S0, see if boot up normal Change-Id: I20cdd1650d1ca774065a6c051006dfd0b7a3fd79 Signed-off-by: Curtis Chen <curtis.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03mb/google/brya/variants/primus: Swap TPM I2C with touchscreen I2CMalik_Hsu
In next build phase, primus will exchange i2c port for touchscreen and cr50. BUG=b:207834727 TEST=build pass Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: Ief1b156b866a9aaa2919f0e209b6439c7019e939 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03mb/google/brya/var/taeko: Set vGPIO reset typeKevin Chang
Due to the vGPIO is not reset when we power on through S5, we would met MCA when PCIE send L1 request without following Ack BUG=b:207070967 TEST=S0->S3->S5->power key->S3->S0, see if boot up normal Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: Ice522260f288b165ae66dddc3e1979e806b53f9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/59749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03mb/google/brya: Create taniks variantJoey Peng
Create the taniks variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:207402720 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_TANIKS Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I797051f93019ccf72f1007d9c0b98cfb071717b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-02mb/google/brya/var/brask: Set PL and PsysPLAlan Huang
1. Set the PL1, PL2 and PL4 according to issue b:193864533 comment#55 and Intel's doc #626774. 2. Set PsysPL2 and PsysPmax according to the conclusion in issue b:193864533 comment#23 and comment#29. BUG=b:193864533 BRANCH=none TEST=Compare the measured power from adapter with the value of 'psys' from the command 'dump_intel_rapl_consumption'. Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Change-Id: I9261902b8c892d0b866f326b24988039c1d30b56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-02mb/google/brya/var/baseboard/brask: Add power limits functionsAlan Huang
Copy function variant_update_power_limits from brya to set power limits. Add function variant_update_psys_power_limits and copy the algorithm from puff. Add structure system_power_limits and psys_config to define and configure the psys power limits. BUG=b:193864533 BRANCH=none TEST=Build pass Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Change-Id: I183017068e9c78acb9fa7073c53593d304ba9248 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-02mb/google/brya/var/gimble: Swap TPM I2C with touchscreen I2CMark Hsieh
DVT schematic will exchange TPM_I2C3 to TPM_I2C1, that may need swap TPM I2C with touchscreen I2C to avoid TPM I2C fall on muxed ISH I2C, need change I2C map, sch amd GPIO map. b/196293623 BUG=b:207613972 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I26d059a7ea5a3fdf00de260214c00d3bba9aa7f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59580 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-02mb/google/brya/var/felwinter: Swap TPM and touchscreen I2C busEric Lai
Follow the latest HW schematic change. BUG=b:208556921 TEST=build pass Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ic05843487ea540b8cd9a50d5f73803905fd80d49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-02mb/google/brya: Fix S0i3 regressionMeera Ravindranath
Keeping the PM timer enabled will disqualify an ADL system from entering S0i3, and will also cause an increase in power during suspend states. The PM timer is not required for brya boards, therefore disabling it. Fixes: 0e905801 (soc/intel: transition full control over PM Timer from FSP to coreboot) BUG=b:206922066 TEST=Boot gimble to OS and verify S0i3 counter incrementing after exiting S0ix suspend states. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I8005dacd732c033980ccc479375ff5b06df8dac1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59790 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-02soc/intel/alderlake: Add Kconfigs for all PCH typesAngel Pons
The Alder Lake code currently supports the PCH-M and PCH-P types, which have some differences (so far, only the amount of PCIe I/O). Mainboards can use the `SOC_INTEL_ALDERLAKE_PCH_M` Kconfig option to specify which PCH type they use: select the option to choose PCH-M, do not select the option to choose PCH-P. While this works, it can be confusing once more PCH types are added. Introduce the `SOC_INTEL_ALDERLAKE_PCH_P` Kconfig option so that boards have to explicitly choose a PCH type. Also, use this option to restrict the PCH-P defaults for PCH-dependent settings to avoid unintended reuse of the PCH-P defaults when adding a new PCH type. To make sure only one PCH type is selected, add some preprocessor in `bootblock.h` to provoke a build-time error if this requirement is not met. Kconfig doesn't seem to have a mechanism to describe sets of mutually-exclusive bool options that allows said options to be selected (a `choice` block doesn't allow its elements to be selected). Finally, adapt the ADL boards accordingly. Change-Id: I7deca820e08ce2b5a220f3c97a511a4f3464a976 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-12-01mb/google/brya/redrix: Add _HID for privacy screen deviceTim Wawrzynczak
The ChromeOS kernel platform driver is adding support for a ChromeOS privacy screen device, and in order to locate that device, the driver uses the GOOG0010 reserved HID for this. Patch for 5.10 kernel can be found at: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3289984 BUG=b:206850071 TEST=dump SSDT, see _HID instead of _ADR Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: If988ca94b6c70d08a7b07cc9f6bbb077fac84e5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59731 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-30mb/google/brya/var/kano: Enable USB2 port 9 for BlueToothDavid Wu
BlueTooth disappeared after disabled USB2 port 9, so we need to re-enable it. BUG=none TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I7971509d7428562c80e781339ead059a189cea13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-30brya: add various ES variantsYH Lin
Fork multiple "4ES" variants off some brya devices to properly support ES SoC. BRANCH=none BUG=b:201767461 TEST=emerge-brya coreboot and check the artifacts Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: Ic9516fec591429238bde1478eca2522d8ed10127 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-26mb/google/brya/var/kano: swap TPM i2c with TS i2c for the next build phaseDavid Wu
Kano EVT will exchange i2c port for touchscreen and cr50. BUG=b:195853169 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I500f0721689ca66b65b8fb1deb79bef2bd988465 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-25mb/google/brya/variants/primus: update gpios for power consumptionMalik_Hsu
In different sku, some unused GPIO pins are processed by NC for power consumption. BUG=b:196790249 TEST=emerge-brya coreboot chromeos-bootimage and check power Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I753e41dec1825299e6cd437b5f67e2d957bc6148 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-25src/mb/brya: Enable crashlog on brya0Kane Chen
Enabling crashlog helps partners to debug hang issues efficiently. BUG=b:195327879 TEST=Found BERT table is created and the tcss function is ok in depthcharge. Warm/cold/suspend_stress test pass 50 cycles on gimble Change-Id: Ib4bbe5d7cece0c6c5fc170460d55ac820054abb9 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-25mb/google/brya/variants/primus: add fw config probe for speaker ampMalik_Hsu
Added fw config probe for MX98360A. BUG=b:205883511 TEST=emerge-brya coreboot chromeos-bootimage and check audio function Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I2452b752ce58a5d0f1008cf187fb79ace6c4285f Reviewed-on: https://review.coreboot.org/c/coreboot/+/59613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-25mb/google/brya/var/felwinter: Add DPTF parameters for FelwinterJohn Su
The DPTF parameters were verified by the thermal team. BUG=b:207463762 BRANCH=brya TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I634d6d98c28e75ad41488921df6b8e836e253ff1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-25mb/google/brya/var/primus: Update thermal table for primusAriel_Fang
- Add 4 TEMP_SENSORs - Configure granularity of power limits BUG=b:200836803 TEST=USE="project_primus emerge-brya coreboot" and verify it builds without error. Signed-off-by: Ariel_Fang <ariel_fang@wistron.corp-partner.google.com> Change-Id: Id4d8dbe678b7f0870aeffa0a0118e65de9d5c22d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-11-25mb/google/brya/var/kano: Update thermal tableDavid Wu
Update thermal setting from thermal team. BUG=b:205648035 TEST=build and verified by thermal team. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: If5082462b79c88ecf510f7a552381c792604366e Reviewed-on: https://review.coreboot.org/c/coreboot/+/59572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-11-25mb/google/brya/var/kano: set power limits for thermalDavid Wu
Set power limits for kano based on CPU SKUs. BUG=b:205648035 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I25cf9be68f8981d8307b4c15ab9f65b59058fb19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-24mb/google/brya/var/gimble: Enable DRIVERS_GENESYSLOGIC_GL9750Mark Hsieh
Enable DRIVERS_GENESYSLOGIC_GL9750 support for Gimble. BUG=b:206014046 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ifc490e6e081b6a8534656417603d2916c3edcb05 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59579 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-23mb/google/brya/var/redrix: Disable autonomous GPIO power managementWisley Chen
With cr50 fw 0.3.22 or older version, it needs to disable autonomous GPIO power management and then can update cr50 fw successfully. BUG=b:202246591 TEST=FW_NAME=redrix emerge-brya coreboot chromeos-bootimage. Change-Id: Idc01ebb4d3ef990f24f18bef5424b7d6ba683d49 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-22mainboard/google/brya: Enable dev screen in bios-stage for BraskAdam Liu
Add Kconfig item ENABLE_TCSS_DISPLAY_DETECTION. TEST=Build with the VBT provided in issue b:199490251. Check the dev screen in bios-stage. BUG=b:199490251, b:206014054 Signed-off-by: Adam Liu <adam.liu@quanta.corp-partner.google.com> Change-Id: I5f34be030a6d819a0e93a2d479c4ff41bb14cfe2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-22mb/google/brya: Move cr50 configuration to variantDavid Wu
Brya schematic will swap TPM I2C with touchscreen I2C, so move into variant level. BUG=b:195853169 TEST=build pass. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ie5276527da135ec15045a81985ae006722871b0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-22mb/google/brya/variants/primus: add fw_config_probe for ALC5682I-VSMalik_Hsu
Added fw_config_probe method to distinguish different audio codecs to facilitate the use of different topology files by the OS. BUG=b:205883511 TEST=emerge-brya coreboot chromeos-bootimage and check audio function Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I0d5b95e89154b2cb6b371f24cc1b151c23ff642f Reviewed-on: https://review.coreboot.org/c/coreboot/+/59367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-22mb/google/brya/var/felwinter: Add ALC5682I-VS codec supportEric Lai
ALC5682I-VS will use in next build. BUG=b:194367025 TEST=none. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I34d736fe1c39860443dac07435a21ccd0ee2f21c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-19mb/google/brya: Move EC_HOST_EVENT_USB_MUX wake event to S0ix onlyJoey Peng
If a USB_MUX_EVENT happens while the AP is in S3 during powerdown transtion (S0->S3->S5), this will cause the device to boot again after it has finished sequencing down to S5. Since S3 is not POR for ChromeOS devices anymore, change this event to wake from S3 and S0ix to just S0ix. BUG=b:206867635 TEST=emerge-brya coreboot Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Icdab40b6a845a34246d7da336f43e970f7908301 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-19mb/google/brya/var/redrix: Configure _DSC for CAM devices to ↵Varshit B Pandya
ACPI_DEVICE_SLEEP_D3_COLD Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips initial probe during kernel boot and prevent privacy LED blink. BUG=b:199823938 TEST=Build and boot redrix to OS. Verify entries in SSDT and monitor LED during boot. Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I88ea1b87698c63e1bd69367ee857fba3f25c84ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/59260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-18mb/google/brya/var/felwinter: Correct USB3 TCSS settingEric Lai
Based on Intel Kit#615686, USB3 only needs to disable TBT and DMA per port. And if uses USB3 directly you need to set TcssAuxOri accordingly. BUG=b:206716691,b:205235144 TEST=USB function work as expected at USB3 only sku. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I303d042d6c80194ff48130fe4e9c04b49ca13ee8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-18mb/google/brya/var/gimble: Include 2 new SPDsMark Hsieh
Add SPD support to gimble for LPDDR4 memory part MT53E1G32D2NP-046 WT:B and MT53E512M32D1NP-046 WT:B. BUG=b:191574298 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Id3fc35605675b953bf993a29f35140f7721eedab Reviewed-on: https://review.coreboot.org/c/coreboot/+/59299 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-18mb/google/brya/var/redrix: De-assert SSD PERST# in romstageWisley Chen
After CB:57539 applied, it can support romstage GPIO table override. We can move SSD PERST# de-assertion to romstage. The reason for this is to give enough time after PERST# deassertion so that the SSD has enough time to initialize before the FSP scans the RPs for downstream devices. BUG=b:199714453 TEST=build Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I242cb1517f564d9d135d523b1e7f95ac34d601f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-18mb/google/brya/var/redrix: Correct WWAN power sequenceWisley Chen
Correct the WWAN power sequence to meet spec BUG=b:206079177 TEST=build Change-Id: Ibba1ecc04b563ae4eedd7596594f33812cbac150 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-18mb/google/brya/var/redrix: Configure Acoustic noise mitigationWisley Chen
Enable Acoustic noise mitigation for redrix and set slew rate to 1/8 BUG=b:204009588 TEST=build and verified by power team Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I0fc0bb68c4de6fca60ee290eb46a77200d748ca8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17mb/google/brya/var/felwinter: Add MT53E1G32D2NP-046 WT:B SPDEric Lai
Add MT53E1G32D2NP-046 WT:B SPD. BUG=b:205669003 TEST=Boot up without issues. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If084a8af941b36a8f3f608271078e32b093d9108 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17mb/google/brya/var/taeko: Correct touchpad GPE settingsJoey Peng
Correct GPE settings so touchpad can wake up DUT. BUG=b:206526991 TEST=emerge-brya coreboot and builds without error Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I1978e9220ad7a275d351ad5eeff7036131926b24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17mb/google/brya/var/taeko: disabled autonomous GPIO power managementJoey Peng
Used H1 firmware where the last version number is 0.0.22, 0.3.22 or less to production that will need to disable autonomous GPIO power management and then can get H1 version by gsctool -a -f -M BUG=b:205315500 TEST=emerge-brya coreboot and test that DUT can boot to OS. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ib26797fa2d4d0b1a6eb28c5d79b9ac0a6054abd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17mb/google/brya/variants/primus: Correct SSD power sequenceCasper Chang
SSD sometimes can't be detected in in warm/cold boot stress. M.2 spec describes SSD_PERST# should be sequenced after power enable. BUG=b:199967106 TEST=SSD was always discovered in warm/cold boot stress. Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I74c21cd96cf1c4518c4ed7c0b3b39e915b6b1ff7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17mb/google/brya: Enable early EC syncBoris Mittelberg
Enable VBOOT_EARLY_EC_SYNC in corebot BUG=b:201356952 BRANCH=None TEST=Tested on Brya id 2 Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: I6e480d64a5d90d5bb9cf59ed60b7b53af9edf46a Reviewed-on: https://review.coreboot.org/c/coreboot/+/59274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17mb/google/brya: Move typeC AUX configuration to variantEric Lai
TypeC AUX configuration is variant specific. So move into variant level. BUG=b:205235144 TEST=No typeC port 0 AUX in felwinter. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I02bfea462cf4c6359fd8d5cca4368786ee03bc8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17mb/google/brya/variants/primus: enable ALC5682I-VSMalik_Hsu
In next phase build, the audio codec will change to ALC5682I-VS BUG=b:205883511 TEST=emerge-brya coreboot chromeos-bootimage and check audio function Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I5906ef9bb88da7fe450a986bf7dd1ee701227f95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-16mb/google/brya/var/redrix: Update dsm parameters for speeker/tweeterWisley Chen
For tuning, redrix needs differnet dsm paramters file for L/R speeker/tweeter. BUG=b:204841998 TEST=build Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I6f93603a6809f9a5aea9f2e554935de5d0457286 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-16mb/google/brya/var/vell: Generate LP5 RAM IDKevin Chiu
Add the support LP5 RAM parts for vell: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) BUG=b:204284866 TEST=emerge-brya coreboot Change-Id: I49745948ebdb25fd98e285defd75714f80271968 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2021-11-15mb/google/brya/var/redrix: Hook up two missing sensorsWisley Chen
Redrix has 4 thermal sensors, so add the missing sensors settings. BUG=b:200134784 TEST=build and verified by thermal team. Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Ia9c58129d439ade21e96896c5e593cd08a627603 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-11-15Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"Hsuan-ting Chen
This reverts commit adb393bdd6cd6734fa2672bd174aca4588a68016. This relands commit 6260bf712a836762b18d80082505e981e040f4bc. Reason for revert: The original CL did not handle some devices correctly. With the fixes: * commit 36721a4 (mb/google/brya: Add GPIO_IN_RW to all variants' early GPIO tables) * commit 3bfe46c (mb/google/guybrush: Add GPIO EC in RW to early GPIO tables) * commit 3a30cf9 (mb/google/guybrush: Build chromeos.c in verstage This CL also fix the following platforms: * Change to always trusted: cyan. * Add to early GPIO table: dedede, eve, fizz, glados, hatch, octopus, poppy, reef, volteer. * Add to both Makefile and early GPIO table: zork. For mb/intel: * adlrvp: Add support for get_ec_is_trusted(). * glkrvp: Add support for get_ec_is_trusted() with always trusted. * kblrvp: Add support for get_ec_is_trusted() with always trusted. * kunimitsu: Add support for get_ec_is_trusted() and initialize it as early GPIO. * shadowmountain: Add support for get_ec_is_trusted() and initialize it as early GPIO. * tglrvp: Add support for get_ec_is_trusted() with always trusted. For qemu-q35: Add support for get_ec_is_trusted() with always trusted. We could attempt another land. Change-Id: I66b8b99d6e6bf259b18573f9f6010f9254357bf9 Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15mb/google/brya/var/felwinter: Disable PCIE port 6Eric Lai
PCIE port 6 is empty as per schematics. BUG=b:206047996 TEST=PCIE port 6 is disabled. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I30fa897c9310c44545e3df670895639a5144e1de Reviewed-on: https://review.coreboot.org/c/coreboot/+/59243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-15mb/google/brya/var/felwinter: Remove USB2 port 0Eric Lai
USB2 port 0 is empty as per schematics. BUG=b:206047996 TEST=USB2 port 0 is disabled. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I45d467a80c23d82dc33dcbed176430a758eea403 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-15mb/google/brya/var/felwinter: Enable garage pen detectionEric Lai
Enable garage pen detection. BUG=b:197912223 TEST=Check evtest can trigger event when toggling the switch. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib5929c876d1a0da34dadd7997a61ab8e75acbbb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-15mb/google/brya/variants/primus: enable RTD3 for PCIe-eMMC bridgeMalik_Hsu
Enable RTD3 driver for PCIe-eMMC bridge, If the board version is less than 1, do not enable RTD3 driver. BUG=b:204469567 TEST=Boot into eMMC storage and perform suspend stress 100 cycle passed Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I5836d65cedfe3907af2c4c33de7a396c4bb8b727 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-15mb/google/brya/variants/gimble: Update PL1 min valueSumeet Pawnikar
Update PL1 minimum value from 3W to 12W as per the thermal design discussed in this bug 203371203 comment #10. BUG=b:203371203 BRANCH=None TEST=Build and boot the gimble system Change-Id: Id66cfb6f6dc0217bd4d83eae1d66ad867a1bdb46 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-15mb/google/brya/var/kano: Add thermal sensor settingsDavid Wu
Kano has 3 thermal sensors, so add the missing sensor settings. BUG=b:205648035 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I0da25f142149f94c83fdf7b2ba2cb8694cddb412 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-11-15mb/google/brya: Create vell variantShon Wang
Create the vell variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:205908918 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_VELL Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Change-Id: Ide8ba1c0dd9b5d9ad90556053abf2a597136a10c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-13Revert "mb/google/brask: Correct GPIO GPP_R6 and GPP_R7 setting"David Wu
This reverts commit ba6fdc892d62741e456ac5628fcd6f869c4cb9af. Reason for revert: Refer to intel doc #627075 (Intel_600_Series Chipset_Family_PCH_GPIO_Impl_Sumry_ Rev1p5p1), GPP_R6 ~ GPP_R7 should be NF3 for dmic. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I460fd99b4ad4b9c470f692032ff7ea2b51cad388 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-12mb/google/brya/var/primus: Disable autonomous GPIO power managementCasper Chang
Used H1 firmware where the last version number is 0.0.22, 0.3.22 or less to production that will need to disable autonomous GPIO power management and then can get H1 version by gsctool -a -f -M BUG=b:201054849 TEST=USE="project_primus emerge-brya coreboot" and verify it builds without error. Change-Id: If5a99a96e5d4b84be3f2c1165283ce249ca75d58 Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-11mb/google/brya/var/felwinter: Enable SaGvEric Lai
Enable SaGv. BUG=b:198235324 TEST=Boot into without issues. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I3cbff8d28bb5b5bfdad323f348b9f880245d049d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-11mb/google/brya/var/kano: Configure USB2 and USB3 portDavid Wu
Disable unused USB2 and USB3 port BUG=b:192370253 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ia2fa10fb21e0a42e51728bc3d78163ca213f8d91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-11mb/google/brya/var/kano: Add gpio-keys ACPI node for PENHDavid Wu
Use gpio_keys driver to add ACPI node for pen eject event. Also setting gpio wake pin for wake events. BUG=b:192415743 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ia36119678cfd5c65a62685d3312537d9aa21e83b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-11-11mb/google/brya/var/taeko: Enable CPU PCIE RP 1Joey Peng
Modify settings to enable CPU PCIE RP 1 according to schematics. BUG=b:205504257 TEST=emerge-brya coreboot and can successfully boot with ssd and emmc. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I0f817c860f2b295c6aa84fa1999d374d99f817f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-13 12:16:23 +0000