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2023-08-11mb/google/brya/var/anahera: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I7a775838358e7abe3f03d0ae65fb619c15dbad6f Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76875 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-11mb/google/nissa/var/joxer: Update eMMC DLL settingsChia-Ling Hou
Update eMMC DLL settings to solve eMMC boot error. BUG=b:294196963 TEST=Reboot test 1000 times pass Change-Id: I16f3aa6aab4c58369770acad92c7ee5518c719ab Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77082 Reviewed-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-09mb/google/brya/var/yavilla: Modify NVM size and width sizeSerin Yeh
NVM has 8KB to store camera module related settings and parameters. According to NVM hardware spec, the NVM size should be 0x400 and the width size should be 0x08. Re-set the right NVM format and ensure camera related configs can get the correct module information. BUG=b:294155898 TEST=none Change-Id: I58932bc0f3dd935aa0ea8e68b2a4b0ae4907b316 Signed-off-by: Serin Yeh <serin.yeh@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76893 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-09mb/google/brya: Use runtime detection for touchscreensMatt DeVillier
Now that power sequencing has been implemented, switch from using ACPI "probed" flag to "detect" flag for all i2c touchscreens. This removes non-present devices from the SSDT and relieves the OS of the burden of probing. TEST=build/boot Windows/linux on redrix?, verify touchscreen functional in OS, dump ACPI and verify only i2c devices actually present on the board have entries in the SSDT. Change-Id: I0273014b2d164f67f503da7b968a09256bffb43c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74929 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-09mb/google/brya: Implement touchscreen power sequencingMatt DeVillier
For brya variants with a touchscreen, drive the enable GPIO high starting in romstage while holding in reset, then disable the reset GPIO in ramstage (done in the baseboard). This will allow coreboot to detect the presence of i2c touchscreens during ACPI SSDT generation (implemented in a subsequent commit). BUG=b:121309055 TEST=tested with rest of patch train Change-Id: I8e56ac4834ce69de18bef2d34f5c361a7fda1aab Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-08mb/google/brask/var/kuldax: Set power limit values for RPL SKUsDavid Wu
Add the RPL CPU power limits and system power limits based on the suggestion of the thermal team for RPL SKUs. The PL4 value suggested by the thermal team which is different from the reference document 686872. BUG=b:292471206 BRANCH=firmware-brya-14505.B TEST=built and booted into OS. Change-Id: Ia030d13ca276c5e8340ae3b20d6e169bb162751d Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76769 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Bob Moragues <moragues@google.com>
2023-08-08mb/google/nissa/var/yavilla: Update eMMC DLL settingsTony Huang
Update eMMC DLL settings to prevent eMMC initialization error BUG=b:290567342 TEST=warm/cold reboot stress test 2500 times pass Change-Id: I418836ec3e2d2221c219eae35e2b22aeaacce4a5 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-08-06mb/google/brya: Add DRIVERS_GFX_GENERIC to BRYA by defaultWon Chung
All boards based on brya will have GFX devices to represent DRM connectors in the kernel's /sys/class/drm/. There should be no functional impact with or without this patch. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I11afa9e8a1c8bf9f57bf6d195f07531182bd36f1 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-06mainboard: Add SPDX license headers to MakefilesMartin Roth
To help identify the licenses of the various files contained in the coreboot source, we've added SPDX headers to the top of all of the .c and .h files. This extends that practice to Makefiles. Any file in the coreboot project without a specific license is bound to the license of the overall coreboot project, GPL Version 2. This patch adds the GPL V2 license identifier to the top of all makefiles in the mainboard directory that don't already have an SPDX license line at the top. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic451e68b1ad9ccdf34484dd98bd7fca7e177ef22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68982 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-08-06mb/google/brya: select ENABLE_TCSS_USB_DETECTIONMatt DeVillier
Select ENABLE_TCSS_USB_DETECTION for non-ChromeOS builds, to enable booting from TCSS USB-C ports. TEST=build/boot google/banshee, verify able to boot from all USB ports using edk2 payload. Change-Id: I998cc4a40950f43b4c511ead93ccc02c56c8367c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76945 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-05mb/google/nissa/var/craaskov: Add wifi sar tableJamie Chen
Add wifi sar table for craaskov BUG=b:290739538 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Ib21f674b6749e125bf76a196902c994bfac15e65 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76576 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-05mb/google/nissa/var/craaskov: Configure the external V1p05/Vnn/VnnSxRex Chou
This patch configures external V1p05/Vnn/VnnSx rails for Craaskov to follow best practices for power savings – untested though. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 , S0 states. * Set the supported voltage states. * Set the voltage for v1p05 and vnn. * Set the ICC max for v1p05 and vnn. BUG=b:290165011 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Ibaf6a285788e26688d3d42691ab40052ef6d6cdb Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76926 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-05mb/google/nissa/var/craaskov: Add DPTF parametersVan Chen
The DPTF parameters were verified by the thermal team. Based on thermal table in 290705146#comment11. Set "tcc_offset" = "8" BUG=b:290705146 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I2d9e1ad2e2fa98757d76578956101a482073885e Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76712 Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-03mb/google/nissa/var/pirrha: Generate SPD ID for supported memory partSeunghwan Kim
Add pirrha supported memory parts in mem_parts_used.txt, generate SPD IDs for them. 1. K3KL8L80CM-MGCT (Samsung) 2. K3KL6L60GM-MGCT (Samsung) BUG=b:292134655 BRANCH=nissa TEST=FW_NAME=pirrha emerge-nissa coreboot chromeos-bootimage Change-Id: Ib3f5a5e5c8296f976d92f0196026d7bb63845664 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76881 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03mb/google: Add more comment on GFX devices for the future referenceWon Chung
Add more details to instruct future boards/models implementers regarding how GFX devices should be added. If HDMI and DP connectors are enumerated by the kernel in /sys/class/drm/ then corresponding GFX device should be added to ACPI. It is possible that some connectors do not have dedicated ports, but still enumerated. The order of GFX devices is DDIA -> DDIB -> TCPX. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I59e82ee954a7d502e419046c1c2d7a20ea8a9224 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76776 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-08-03mb/google/nissa/var/craaskov: Add overridetreeRex Chou
Add override devicetree based on schematics(ver. 20230714). BUG=b:290248526 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Id002282d91dc94b00f5d133203b62ca39d6cae6d Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76662 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-02mb/google/nissa/var/craaskov: Configure GPIOs according to schematicsRex Chou
Configure GPIOs based on schematics and confirm with EE. BUG=b:290248526 BRANCH=None TEST=emerge-nissa coreboot Change-Id: I17fc9333a0ef592ea36b196b3fd417be47fb82bb Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2023-08-02mb/google/nissa/var/joxer: support DPTF oem_variablesMark Hsieh
1. Joxer uses dptf.dv to distinguish 6W/15W by setting OEM variable. 2. Update passive policy and critical policy. BUG=b:285477026, b:293540179 TEST=emerge-nissa coreboot and check the OEM variable. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I4e52ac624f7d7628cce3035a2bac67fc527bc167 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Ivan Chen <yulunchen@google.com>
2023-07-31mb/google/brya/var/vell: Disable PCH USB2 phy power gatingShon Wang
The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for vell board. Please refer Intel doc#723158 for more information. BUG=b:293535284 TEST=build and boot vell Change-Id: I8a4d633fbd362188aedef373e515c7bfe5c4327a Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-31mb/google/brya: Create pirrha variantRaymond Chung
Create the pirrha variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:292134655 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_PIRRHA Change-Id: Idc0a4dbb467cbdb91a5ed55c5e0a9e898e775b11 Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76768 Reviewed-by: SH Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-31mb/google/nissa/var/gothrax: Adjust touchscreen driverYunlong Jia
Vendor changes touchscreen firmware to use hid method instead of i2c. BUG=b:274707912 BRANCH=None TEST=emerge-nissa coreboot Change-Id: I8e9e0b757e337db6af3fbf3cd4fdbc0079646179 Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76680 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2023-07-28mb/google/nissa/var/gothrax: Tune SX9324 P-sensor configurationYunlong Jia
Update SX9324 register settings based on tuning value from SEMTECH. －　Enable GPP_B5/GPP_B6 －　Enable GPP_H19 open irq －　Adjust register reg_afe_ctrl0/reg_afe_ctrl3/reg_afe_ctrl4 BUG=b:292016304 BRANCH=None TEST=Check register settings and confirm P-sensor function can work. Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I6f15f7a7c428aee45d35830574ef84aefcae6401 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76711 Reviewed-by: Kyle Lin <kylelinck@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-07-28mb/google/brask/var/constitution: Add wifi sar tableMorris Hsu
Add wifi sar table for constitution BUG=b:291859402 BRANCH=firmware-brya-14505.B TEST=emerge-constitution coreboot chromeos-bootimage Change-Id: I8f99c5cf486cb3e1f2825bbe3a8084f2fe57a41a Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76674 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-07-27mb/google/nissa/var/uldren: Modify GPIOs for non-touchscreenDtrain Hsu
Set GPP_C6(TCHSCR_REPORT_EN) and GPP_C7(TCHSCR_INT_ODL) to NC for non-touchscreen sku. BUG=b:283199751 BRANCH=firmware-nissa-15217.B TEST=build and boot to ChromeOS Change-Id: Ie062eef24f640c3d6c4a0b4c77792e57ac3a722c Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-27mb/google/nissa/var/uldren: Add FW_CONFIG probe for fivrDtrain Hsu
Uldren will support internal fivr in next phase and using fw_config to decide the board with internal or external fivr. BUG=b:287379760 BRANCH=firmware-nissa-15217.B TEST=boot to ChromeOS, cold reboot/suspend/recovery mode/install OS work normally. Change-Id: I8a1ac60f599f2895654946d9fa1c4e1f2657fd10 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2023-07-27mb/google/nissa/var/craaskov: Add memory parts supportRex Chou
Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: 1) LP5 Memory - 2GB Micron MT62F512M32D2DR-031 WT:B 2) LP5 Memory - 2GB Hynix H9JCNNNBK3MLYR-N6E 3) LP5 Memory - 4GB Samsung K3LKBKB0BM-MGCP 4) LP5 Memory - 4GB Hynix H9JCNNNCP3MLYR-N6E DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H9JCNNNBK3MLYR-N6E 0 (0000) K3LKBKB0BM-MGCP 1 (0001) H9JCNNNCP3MLYR-N6E 2 (0010) BUG=b:292461498 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I02e49d60e43c4fed8356556ec194d726c30cd609 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-07-26mb/google/brya/var/anahera: Disable PCH USB2 phy power gatingWisley Chen
The patch disables PCH USB2 Phy power gating to fix display flicker BUG=b:292403156 TEST=Verified on the defeat board Change-Id: If0c0e655c5d32f39b90635bb3c1d13d8b6993b59 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-07-26mb/google/brya: fix MRC cache failure for hynix partsNick Vaccaro
Set the cs_pi_start_high_in_ect if the DUT is using one of the two following Hynix parts: H54G56CYRBX247 and H54G46CYRBX267. Failure to set cs_pi_start_high_in_ect when using these parts will result in an MRC cache failure and DUT will fail to boot. BUG=b:292153199 TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot brya variant to kernel. Change-Id: I36040139b959c85c3ac220a34574caa12ca6c5fe Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-26mb/google/brya/var/redrix: Disable PCH USB2 phy power gatingWisley Chen
The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for redrix board. Please refer Intel doc#723158 for more information. BUG=b:292435264 TEST=build and boot redrix Change-Id: I34d10c763f4710d2c5678704320fd1cc8d8b6287 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76670 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-26mb/google/nissa/var/yavilla: avoid mipi camera LED blinking during launchRobert Chen
Camera LED will blink several times as sensor is being probed during kernel boot. Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips initial probe during kernel boot and prevent privacy LED blink. BUG=b:292173903 TEST=Build and boot on Yavilly EVT unit. Verify & observe Camera LED blinking behavior. Change-Id: Ic3e3439dc9313325189761b277e1a3bd1c1d9418 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76671 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-25mb/google/nissa/var/pujjo: Generate SPD ID for new supported memory partLeo Chou
Add pujjo new supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. Hynix H58G56BK7BX068 2. Samsung K3KL6L60GM-MGCT, K3KL8L80CM-MGCT 3. Micron MT62F1G32D2DS-026 WT:B BUG=b:292452868 TEST=Use part_id_gen to generate related settings Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Ia123a1cfd93a5e08ab0ba65f1d9be240d60ff356 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76672 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-20mb/google/nissa/var/uldren: Decrease GT7996F stop_delay_ms to 200msDtrain Hsu
In order to reduce S0ix resume time, decrease stop_delay_ms from 300ms to 200ms for Goodix GT7996F. The value source is from https://partnerissuetracker.corp.google.com/issues/285999032#comment16. BUG=b:285999032 BRANCH=firmware-nissa-15217.B TEST=boot uldren to ChromeOS and touchscreen is workable. Change-Id: I2f0adadbd3d0774da03338cc0abd1639104876d9 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76577 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-18mb/google/brya/var/osiris: Enable CsPiStartHighinEct for Hynix memoryDavid Wu
According to Intel doc#763797 to overcome early command training hang issue, the CsPiStartHighinEct needs to be enabled for hynix memory. BUG=b:284192689 BRANCH=firmware-brya-14505.B TEST=Built and booted into OS. Change-Id: Ic177c5ffcb6a3d3f76292a0d99ab0e806d43fc11 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76549 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-07-18mb/google/brya/var/taeko: Enable CsPiStartHighinEctJoey Peng
Enable CsPiStartHighinEct to fix MRC Cache fail issue BUG=b:279835630 BRANCH=none TEST=Pass MRC Cache test with toolkit 1000 times Change-Id: I25cd856785bab9c661e30e2987b43f0dc2ba9564 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-18mb/google/brya/var/kano: Enable CsPiStartHighinEct for Hynix memoryDavid Wu
According to Intel doc#763797 to overcome early command training hang issue, the CsPiStartHighinEct needs to be enabled for hynix memory. BUG=b:281643325 BRANCH=firmware-brya-14505.B TEST=Built and booted into OS. Change-Id: I95702e675fa3b73c7e8ee0c8625c7828d8129ea8 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76355 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18pujjoteen5: modify fw_config to separate pujjoteen5 wifi sar tableLeo Chou
Use fw_config to separate pujjoteen5 intel wifi sar table. BUG=b:279984381 Test=emerge-nissa coreboot Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I2e744bf0801bd7b18817a00fcbe3d0c62b8fc3d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76453 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-07-18mb/google/nissa/var/gothrax: Initialise overridetreeYunlong Jia
Add an initial overridetree for gothrax based on the schematic. BUG=b:274707912 BRANCH=None TEST=emerge-nissa coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: Idfd9788a75f9c342f85d6e1a3d54327d64797dd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76013 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18mb/google/nissa/var/gothrax: Set up driver as per schematicsYunlong Jia
Drivers for Pen Garage/SDCard Reader/LTE/SAR/WWAN and I2C for TPM. BUG=b:274707912 BRANCH=None Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I1203ca13bd55b8ab96ce5d323a36ffde06860fa9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76104 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyle Lin <kylelinck@google.com>
2023-07-17mb/google/nissa: Create craaskov variantRex Chou
Create the craaskov variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:290248526 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_CRAASKOV Change-Id: I1d12f7c3d0ef7067f4530c1c69c560f9a83561f6 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2023-07-13mb/google/nissa/var/pujjo: Add WWAN EM060 power on sequenceLeo Chou
Pujjo support WWAN EM060 device, use FW_CONFIG to handle the power on sequence. BUG=b:290709711 TEST=Build and check WWAN EM060 power on sequence. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I66800c75274e8e1e55d4314c82b7fcdf2a4477bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/76403 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-13mb/google/nissa/var/uldren: Modify reset_delay_ms for EKTH7D18Dtrain Hsu
Modify reset_delay_ms from 300ms to 6ms for ELAN EKTH7D18. BUG=b:285999032 BRANCH=firmware-nissa-15217.B TEST=boot uldren to ChromeOS and touchscreen is workable. Change-Id: Iffcddbe7735b7a837887dec68e1270c2af5f4556 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76417 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-11mb/google/nissa/var/gothrax: Update eMMC DLL tuning valuesSimon Yang
Update eMMC DLL tuning values for improved initialization reliability BUG=b:289763421 TEST=cold reboot stress test over 5000 cycles on Foresee and Kingston eMMC Change-Id: I63077b8717feecf3d50507abb188b7fadb5d6c79 Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76221 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-10mb/google/brya/var/redrix: Use just single GFX entryWon Chung
Since multiple GFX entry causes an ACPI error when trying to write _DOD method multiple times, combine the GFX entry into one so that _DOD method is written just once. BUG=b:289854155 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I22ad70d50f1aecf8da70e8dd04a36a0a7c1c7609 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76329 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-10mb/google/brya/var/brya: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Ia756f842943b8e1f1877db7433641e6bbd05f45b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74407 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-10mb/google/brya/var/skolas: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I889db739d6e006c1753eb8c0d208cf471d09f18d Reviewed-on: https://review.coreboot.org/c/coreboot/+/74368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-10mb/google/brya: put Bluetooth VPGIOs overridableMac Chiang
The BT VGPIOs pad config in variant of gpio.c won't be overwritten on board eventually because no matched gpios existed here. Put BT VGPIOs in gpio_table, ensure that these were able to be overwritten. The fix included crota and omnigul BT offload work successfully. BUG=b:264834572 TEST=test Bluetooth offload playback/capture in SCO profile. Change-Id: I62cecf26abd0411f7cbb0a56b8b8f0a25d370c69 Signed-off-by: Mac Chiang <mac.chiang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-07-10mb/google/brya/var/kuldax: Add fw_config and configurate AUX pinDavid Wu
Add fw_config and configurate AUX pin for MB USB Type-C. MB USB3 doesn't have re-timer, thus have to configurate the AUX pin. BUG=b:275335023 TEST=build pass Change-Id: I1334dcbaec6de1707c6892efbebaf8d460ba8648 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76348 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2023-07-07mb/google/brya/var/constitution: Update overridetreeMorris Hsu
constitution only has one TBT port, remove tcss_dma1. BUG=None TEST=emerge-constitution coreboot Change-Id: Ia4eb4371eb20e75a0f464e2b087fd2fe59569537 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Pablo Ceballos <pceballos@google.com>
2023-07-06mb/google/brya/var/mithrax: Generate SPD ID for supported partsJohn Su
Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: 1. K4U6E3S4AB-MGCL (Samsung) 2. K4UBE3D4AB-MGCL (Samsung) BUG=b:289873670 BRANCH=brya TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I7a262ac62c24cfb43c0283c9730c177a242342e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76240 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-04mb/google/nissa/var/uldren: Update DPTF parameters and tcc_offsetDtrain Hsu
Follow the Project_Uldren_Thermal_paramters_list_2023_0626.xlsx to modify DPTF parameters and tcc_offset. - Set tcc_offset to 3. - Update Critical Policy trip point. - Update Power Limits PL1 minimum step size to control limits (in mW). BUG=b:282598257 BRANCH=firmware-nissa-15217.B TEST=boot uldren to ChromeOS and pass thermal test. Change-Id: Ic5bbb3aa3b036a1eae8a95f63b570db2dc6da978 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76105 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-07-04mb/google/nissa/var/joxer: Disable external fivrMark Hsieh
In next phase, joxer will remove external fivr. BUG=b:285477026 TEST=emerge-nissa coreboot and boot to OS, suspend/resume work normally. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I7fd7ad90e1544966170df402243604379f5790db Reviewed-on: https://review.coreboot.org/c/coreboot/+/76187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-07-03mb/google/nissa/var/pujjo: Tune SX9324 register for pujjoteen5Leo Chou
Update SX9324 register settings based on tuning value from SEMTECH. BUG=b:279510275 TEST=Check i2c register settings on Pujjoteen5 and confirm P sensor function can work. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Idc9a2dc817e027551e209c0a26eeebad398f710c Reviewed-on: https://review.coreboot.org/c/coreboot/+/75900 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-03mb/google/nissa/var/joxer: support for different WiFi SAR tablesMark Hsieh
Set the WIFI_SAR_ID field in FW_CONFIG to selcet the correct SAR table. BUG=b:285477026 TEST=emerge-nissa coreboot and check the SAR value Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ibea62c77ecad9b2c475452b706779e4cfc6b06d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76144 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-03mb/google/nissa/yaviks: Tune eMMC DLL value for boot issueChia-Ling Hou
Resolve boot issue by tuning RX HS50 and HS200. BUG=b:265611305 TEST=Reboot test 2500 times pass Change-Id: I8a2727dc0ce9dc86c6bfb6d85567afee1734db62 Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75812 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
2023-06-29mb/google/nissa/var/gothrax: Add GPIO table for gothraxYunlong Jia
Configure GPIOs according to schematics. BUG=b:287563817 BRANCH=None TEST=emerge-nissa coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: If852c7a30edb9fb778872414cb15dc3446aebc55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75872 Reviewed-by: Henry Sun <henrysun@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-06-28mb/google/hades: Update SD controller from GL9750 to GL9755Eric Lai
Hades uses GL9755 not GL9750. Select the right driver for ASPM. BUG=b:283721798 TEST=check the coreboot log. GL9755: configure ASPM and LTR Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ia5b3b17d76f02d5114af24535f9a1eecc14358a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76118 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-27mb/google/hades: select DUMP_SMBIOS_TYPE17Eric Lai
Hades uses DDR5 which can't read SPD from coreboot yet. Use smbios dump to print memory information. TEST=check the coreboot log. memory Channel-0-DIMM-0 type is DDR5 memory part number is MTC8C1084S1SC56BG1 memory max speed is 5600 MT/s memory speed is 5200 MT/s memory size is 16384 MiB Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ica44081228a3a1edc36e2110e84686582fbe8f33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-06-26mb/google/brya/var/vell: update FW_config to sync config.starShon Wang
We have found inconsistencies in turn of FW_CONFIG settings/definitions, so sync setting to vell config.star BUG=b:282189358 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: I676b719ecc711a6f59e76465a3566bf63924d90f Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75913 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-22mb/google/brya/acpi: Set polling timing for DL23 and LD23 to 2msTarun Tuli
Reducing the polling time from 16ms to 2ms. Experimentally we have determined that the link state normally takes approximately 3.5ms to update and therefore we were waiting longer than necessary. TEST=build and confirm we are not waiting the extended period. Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I8fabb5ac46cae5c92d5b6f1dc0641a4d121c61dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/76052 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-22mb/google/brya/acpi: Set power down delay to 2ms after PEXVDDTarun Tuli
Reduce the delay between PEXVDD and NVVDD from 3ms to 2ms during power down sequences. The hardware discharge is aggressive enough that we can safely optimize this. BUG=b:288267305 TEST=build and measured delay is acceptable Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I7c65301414044487e50bbbca618c4e602e571cfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/76051 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-22mb/google/brya/acpi: Don't wait for PG in GPU off sequencesTarun Tuli
When powering rails down, there is no value in waiting for the PG signal to de-assert. Instead, shut the rails off as quickly as possible while maintaining a controlled ordering. BUG=b:288266850 TEST=build and measured delays are gone Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: If31691a7d62b72661fcbacb34e90f3a6adec8134 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76050 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-22mb/google/nissa/var/joxer: Disable GPIOs for SD card readerTerry Chen
the board won’t have a SD card reader, so disable it. BUG=b:285477026 TEST=USE="project_joxer emerge-nissa coreboot" Change-Id: I6a55058b453771d264700a1364ef538f831148e4 Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-06-20mb/google/hades: Update typeC usb PLDEric Lai
get_usb_port_references refer the PLD group. If the port assign cross ports like mux[0] use USB3 and mux[1] use USB1, then we need set USB3 to group 1. Update the PLD panel to back as well. BUG=b:286328285 TEST=check ACPI can have right USB port in EC CON. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I97517ecd4f8615af749fb6d007ded8e171796f7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/75912 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-19mb/google/nissa/var/joxer: enable ELAN and G2touch touchscreenMark Hsieh
Update overridetree to support ELAN and G2_G7500 touchscreen. BUG=b:285477026 TEST=emerge-nissa coreboot and check touchscreen function Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I236a2815f956929c6cd84c981cb15e9ab0f657b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75762 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-17mb/google/nissa/var/gothrax: Generate RAM IDs for new memory partsYunlong Jia
Add the support RAM parts for gothrax. Here is the ram part number list: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H58G56AK6BX069 1 (0001) K3LKBKB0BM-MGCP 2 (0010) BUG=b:284388714 BRANCH=None TEST=emerge-nissa coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: Ib16846f7b2061ee254db674ac7bac66c9b9f4e70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75834 Reviewed-by: Henry Sun <henrysun@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-16mb/google/nissa/var/joxer: Disable storage devices based on fw_configMark Hsieh
- Disable devices in variant.c instead of adding probe statements to devicetree because storage devices need to be enabled when fw_config is unprovisioned, and devicetree does not currently support this. (it disables all probed devices when fw_config is unprovisioned.). - Removed `bootblock-y += variant.c` from Makefile.inc based on CL:3841120.(The infrastructure for selecting an appropriate firmware image to use the right descriptor is now ready so runtime descriptor updates are no longer necessary.). BUG=b:285477026 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I6920d88dfec86676ff6733146f748e06d4085c49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75743 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-15mb/google/brya/var/volmar: Add Micron MT53E2G32D4NQ-046 WT:C SPDRen Kuo
Add support for Micron MT53E2G32D4NQ-046 WT:C LP4x DRAM. BUG=b:216393391 TEST=build pass Change-Id: I3797de01629fdb5ace4c610943d88db525da112b Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75826 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-06-15mb/google/nissa/var/pujjo: Set GPIO of WWAN_SAR_DETECT to NCLeo Chou
Pujjo does not support GPIO based D-SAR, so set GPP_D15 and GPP_H23 to NC. BUG=b:275264095 TEST=boot on pujjo and no impact WWAN dynamic SAR function Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I4fe40b32a572a8d914e01e5cd7927766ccf17c02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75403 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-15{driver, mb, soc}: Rename Intel CSE FPT config to ISH FW version configSubrata Banik
This patch renames `SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION` config to `SOC_INTEL_STORE_ISH_FW_VERSION` to ensure the usage of this config is clear. Any platform would like to fetch the currently running ISH firmware version should select this configuration. TEST=Able to build and boot google/marasov. Change-Id: Ie503d6a5bf5bd0d3d561355b592e75b22c910bf5 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75767 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-14mb/google/nissa/var/joxer: Add DmaProperty for ISHMark Hsieh
On nissa, the ISH is running closed source firmware, so the ChromeOS security requirements specify it must be behind an IOMMU. Add DmaProperty to the ISH _DSD on joxer. BUG=b:285477026 TEST=Kernel marks ISH (PCI device 12.0) as untrusted, and changes the IOMMU group type to "DMA". Also, device still goes to S0i3. Before: $ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted 0 $ ls /sys/kernel/iommu_groups/5/devices 0000:00:12.0 0000:00:12.7 $ cat /sys/kernel/iommu_groups/5/type DMA-FQ After: $ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted 1 $ ls /sys/kernel/iommu_groups/5/devices 0000:00:12.0 0000:00:12.7 $ cat /sys/kernel/iommu_groups/5/type DMA Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I69b00f0281f4493db157783840d9cdcbb138017f Reviewed-on: https://review.coreboot.org/c/coreboot/+/75758 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-14mb/google/nissa/var/joxer: Remove fw_config probe for storage devicesMark Hsieh
When fw_config is unprovisioned, devicetree will disable all probed devices. However, boot-critical devices such as storage devices need to be enabled. As a temporary workaround while adding devicetree support for this, remove the fw_config probe for storage devices so that all storage devices are always enabled. On eMMC SKUs, UFS and ISH will be disabled by the PCI scan anyway. On UFS SKUs, eMMC is not disabled by the PCI scan, but keeping it enabled should have no functional impact, only a possible power impact. BUG=b:285477026 TEST=On joxer eMMC and UFS SKUs, boot to OS and `suspend_stress_test -c 10` Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I834bd81ce636a6f32d50434cbf07b1d572620492 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75757 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-13mb/google/brya/variants/hades: Set WP signal to GPP_E12Tarun Tuli
Move the WP signal to GPP_E12 from the current GPP_E15 to match the design. BUG=b:285084125 TEST=WP signal reports as we expect Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I8772173fcdcabf78b0c7d605cd495ebe04b63242 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-13mb/google/brya/var/osiris: Add Micron MT53E2G32D4NQ-046 WT:C SPDDavid Wu
Add support for Micron MT53E2G32D4NQ-046 WT:C LP4x DRAM. BUG=b:216393391 TEST=build pass Change-Id: I8c66a18fd94d9a013710fbc6dc7f1533d808392e Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-06-12mb/google/brya/var/hades: Abort power on if any rails fail to come upTarun Tuli
Currently if a rails PG fails to assert, the power on sequence continue after the 20ms timeout. Instead, we should abort and enter a power down. BUG=b:285980464 TEST=sequence now aborts and powers down on failure Change-Id: Id0865e6bdb5db1815ad5509306637308e98c15d7 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-12mb/google/nissa/var/joxer: Configure the external V1p05/Vnn/VnnSx railsMark Hsieh
This patch configures external V1p05/Vnn/VnnSx rails for Joxer to achieve the better power savings. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 , S0 states. * Set the supported voltage states. * Set the voltage for v1p05 and vnn. * Set the ICC max for v1p05 and vnn. Kit: 646929 - ADL N Platform Design Guide BUG=b:285477026 TEST=Verified all the UPD values are updated with these configs. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I78d2a885d577f6c1a89ab74c0da7b6544322c0d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2023-06-09mb/google/brya/acpi: Turn NV12 enable signal off on GCOFF entryTarun Tuli
Properly shutdown NV12 rail in the off sequence (current implementation leaves it asserted). BUG=b:286287940 TEST=NV12 now shuts down on GCOFF entry Change-Id: I7d338fc4a96f119617aff558413a5a9ac44c27d7 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75533 Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-06-09mb/google/nissa/var/uldren: Modify WWAN power sequenceDtrain Hsu
Follow spec[1] to modify WWAN power sequence. The WWAN power sequence of warm reset is fail. The correct sequence is WWAN_EN should keep high when doing warm reset. Set GPP_D6 to PWROK which is not to do PAD reset when warm reset. [1]: [JDB10] FC ADL-N_WWAN sequence_FM101-GL SDX12 Power Timing Review_V1.6_20230602.xlsx BUG=b:285065375 BRANCH=firmware-nissa-15217.B TEST=1. emerge-nissa coreboot chromeos-bootimage 2. power sequence meets spec. Change-Id: If59630dbd10e971c91e01f33a657c01d857bc0b9 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75690 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-09mb/google/nissa/var/yavilla: Enable wifi SARShon Wang
Enable wifi sar function for yavilla/yavilly/yavijo. Use the fw_config to separate SAR setting for different wifi card. BUG=b:286141046 BRANCH=firmware-nissa-15217.B TEST=build, enabled iwlwifi debug, and check dmesg Change-Id: I1bd111a734a250df49535a07ef056d5b68fccb33 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-06-09mb/google/brya/var/vell: Generate SPD ID for supported memory partShon Wang
Add new memory parts DRAM Part Name ID to assign Hynix H58G66AK6BX070 3 (0011) Hynix H9JCNNNFA5MLYR-N6E 4 (0100) Micron MT62F2G32D8DR-031 WT:B 4 (0100) BUG=b:279325772 BRANCH=firmware-brya-14505.B TEST=run part_id_gen to generate SPD id Change-Id: I2e6a916de08e7c05e95909d2b69bc839d13192d9 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74713 Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-06-08mb/google/brya/var/kano: Add Micron MT53E2G32D4NQ-046 WT:C SPDDavid Wu
Add support for Micron MT53E2G32D4NQ-046 WT:C LP4x DRAM. BUG=b:216393391 TEST=build pass Change-Id: I0abf1f1105f9a6f16af23b0ed3eb4faeb669eee6 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75716 Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-06-08mb/google/brya: Enable GPU ACPI for HadesTarun Tuli
Include the GPU ACPI methods for all of Hades baseboard. BUG=b:285981616 TEST=built for Hades and verify shutdown works Change-Id: Iec3c4b59a9e7a9d4a902db51d40b60e114521774 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-07mb/google/brya/var/redrix: Add new GFX device with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot BRANCH=firmware-brya-14505.B Change-Id: Ia083617c58d6b7ebc108e07e29a1c8061580eae5 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-07mb/google/nissa/var/joxer: disable PCIE RP7Mark Hsieh
joxer removed SD card from all SKUs, thus disable pcie_rp7. BUG=b:285477026 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I3486d665ddb1de521ab4e656addb2209055174c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75658 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07mb/google/nissa/var/joxer: Remove VBOOT_GSC_BOARD_ID configReka Norman
Board IDs are now filled in as part of the signing process, so we don't need to set them in coreboot. BUG=b:240620735 TEST=Build and check VBOOT_GSC_BOARD_ID is set to ZZCR. Change-Id: I7dda8ad59046a1dd9a28595e037eda86e91c98df Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75641 Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-06mb/google/nissa/var/uldren: Modify GPP_D7 and PCIE RP7Dtrain Hsu
Uldren does not have PCIE device and should disable PCIE RP7 and GPP_D7 for preventing PCIe controller not power gate in S0ix. BUG=b:283735051 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage 1. PCIE RP7: cbmem -c | grep 'PCI: 00:1c.6' [SPEW ] PCI: 00:1c.6: enabled 0 [SPEW ] PCI: 00:1c.6: enabled 0 2. GPP_D7: iotools mmio_read32 0xfd6d0ab0 0x44000300 Change-Id: Ia8a2c0f5530c7a056e8d706c651cac1d49b2091c Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75644 Reviewed-by: Harsha B R <harsha.b.r@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-06-06mb/google/nissa/var/joxer: add lp5x SPDs for JoxerMark Hsieh
Add Makefile.inc to include four LPDDR5x SPDs for the following parts for Joxer: DRAM Part Name ID to assign K3KL6L60GM-MGCT 3 (0011) H58G56BK7BX068 4 (0100) MT62F1G32D2DS-026 WT:B 4 (0100) K3KL8L80CM-MGCT 4 (0100) BUG=b:236576115 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ibdc89c882581cfe4e5978faf4c6f70d653e0813d Reviewed-on: https://review.coreboot.org/c/coreboot/+/75610 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-04mb/google/brya/var/taeko: Fix PLD group orderWon Chung
Ensure USB-C ports' _PLD group numbers appear in order. get_usb_port_references in src/ec/google/chromeec/ec_acpi.c uses group token to match with the Type-C port number. BUG=b:216490477 TEST=build coreboot and system boot into OS. BRANCH=firmware-brya-14505.B Change-Id: I5c0395d33ee47ab1c7d45f33d6afb063b8263836 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75572 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-04mb/google/brya/var/marasov: Fix PLD group orderWon Chung
Ensure USB-C ports' _PLD group numbers appear in order. get_usb_port_references in src/ec/google/chromeec/ec_acpi.c uses group token to match with the Type-C port number. BUG=b:216490477 TEST=build coreboot and system boot into OS. BRANCH=firmware-brya-14505.B Change-Id: I51ff0991565d60807c100b33fb66ab10cc48b8e1 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-04mb/google/brya/var/constitution: Fix PLD group orderWon Chung
Ensure USB-C ports' _PLD group numbers appear in order. get_usb_port_references in src/ec/google/chromeec/ec_acpi.c uses group token to match with the Type-C port number. BUG=b:216490477 TEST=build coreboot and system boot into OS. BRANCH=firmware-brya-14505.B Change-Id: Ib564ffe272e73f46ec6608420dc431c8b017fb65 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-04mb/google/brya/var/kuldax: use RPL FSP headersDavid Wu
Select SOC_INTEL_RAPTORLAKE for kuldax so that it will use the RPL FSP headers for kuldax. BUG=b:285406822 BRANCH=firmware-brya-14505.B TEST="FW_NAME=kuldax emerge-brask coreboot-private-files-baseboard-brya coreboot chromeos-bootimage" Cq-Depend: chromium:4583807, chrome-internal:6003096 Change-Id: Icbf8b26bc2bfee2559cce236bde80a99f8bff859 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75599 Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-06-04mb/google/brya/var/kuldax: Enable Fast VMode for kuldaxDavid Wu
Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP threshold. BUG=b:285406822 BRANCH=firmware-brya-14505.B TEST=Verify that the feature is enabled by reading from fsp log Change-Id: I9ae58d704cba8124c6cb9865431aff84c9d154f7 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75600 Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-06-03mb/google/brya/var/anahera: Generate RAM ID for K4UCE3Q4AB-MGCLWisley Chen
Generate RAM ID for Samsung K4UCE3Q4AB-MGCL DRAM Part Name ID to assign K4UCE3Q4AB-MGCL 3 (0011) BUG=b:281950933 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: I75818b8a34d010fc0efe90c7625162e40e3b0dca Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-03mb/google/brya/var/redrix: Generate RAM ID for K4UCE3Q4AB-MGCLWisley Chen
Generate RAM ID for Samsung K4UCE3Q4AB-MGCL DRAM Part Name ID to assign K4UCE3Q4AB-MGCL 3 (0011) BUG=b:281943392 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: I79b29b1195468272c7f64a0eeb15d032eff8c1d3 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-01mb/google/nissa/var/uldren: Add DPTF parametersDtrain Hsu
The DPTF parameters were verified by the thermal team. BUG=b:282598257 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I1f38ef52d3906960f8b692595fcc3b39bc000243 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2023-05-31mb/google/brya/acpi: FBVDD_PWR_EN should be inverted on AgahTarun Tuli
The FBVDD_PWR_EN signal should be inverted in its control level on Agah v.s. Hades. The original change covered the Hades implementation, but needs to be updated to invert for Agah. This change can be removed once we drop support for Agah. BUG=b:280467267 TEST=built for Hades and Agah Change-Id: I7f90c03b8d9b859004e5c124bf0a1f7b59921c3d Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75530 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-31mb/google/nissa/var/uldren: Fine tune eMMC DLL settingsDtrain Hsu
Fine tune eMMC DLL settings based on Uldren board. BUG=b:280120229 TEST=executed 2500 cycles of cold boot successfully on all eMMC sku. Change-Id: I82a55a1fe17aa910eb02464df463603dcbbbef05 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75459 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Jamie Chen <jamie.chen@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-31mb/google/nissa/var/uldren: Add ACPI DmaProperty for WLAN deviceDtrain Hsu
Add ACPI DmaProperty for WLAN device. `is_untrusted` is eventually ended up by adding DMA property _DSD which is similar to what `add_acpi_dma_property` does for WWAN drivers, hence it makes sense to have a unified name across different device drivers. BUG=b:279676191 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I6d898a939aa0be31a671d2436a81c34f7a1ec030 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75460 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-26mb/google/nissa/var/uldren: Add fw_config probe for lteDtrain Hsu
Use fw_config to probe lte. BUG=b:283199751 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I5596f3536b0a21453f89e67615acabbbf6a8409b Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75337 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-26mb/google/nissa/var/uldren: Add fw_config probe for touchpadDtrain Hsu
Use fw_config to probe touchpad. BUG=b:283199751 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Ib20abac74683c670c174821b821ede461dbb0163 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-24mb/google/hades: Enable smbus in device treeEric Lai
Hades uses the SODIMM, enable the smbus to see the SPD address for the memory. BUG=b:283138024 TEST=i2cdetect -l can see the smubs adapter. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I3912a025afaf8388d04a4b08852a84d4a2a6bf06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75399 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-05 02:37:59 +0000