diff options
| author | Won Chung <wonchung@google.com> | 2023-06-01 00:18:05 +0000 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2023-06-04 19:16:09 +0000 |
| commit | 96edcc1c98eb34bf6acfc78d1f87180497bb60e8 (patch) | |
| tree | 15dd93fc32187dd38389b20552ce5bdf66dda2c1 /src/mainboard/google/brya | |
| parent | 6ce0d1a756133506f20db017cac84fba2171e4fe (diff) | |
mb/google/brya/var/constitution: Fix PLD group order
Ensure USB-C ports' _PLD group numbers appear in order.
get_usb_port_references in src/ec/google/chromeec/ec_acpi.c uses group
token to match with the Type-C port number.
BUG=b:216490477
TEST=build coreboot and system boot into OS.
BRANCH=firmware-brya-14505.B
Change-Id: Ib564ffe272e73f46ec6608420dc431c8b017fb65
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Diffstat (limited to 'src/mainboard/google/brya')
| -rw-r--r-- | src/mainboard/google/brya/variants/constitution/overridetree.cb | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/brya/variants/constitution/overridetree.cb b/src/mainboard/google/brya/variants/constitution/overridetree.cb index 4b894b02f8..17965fd4d8 100644 --- a/src/mainboard/google/brya/variants/constitution/overridetree.cb +++ b/src/mainboard/google/brya/variants/constitution/overridetree.cb @@ -244,14 +244,14 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-C Port C1 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 2))" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port2 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, LEFT, ACPI_PLD_GROUP(1, 3))" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, LEFT, ACPI_PLD_GROUP(3, 1))" device ref tcss_usb3_port3 on end end end @@ -271,14 +271,14 @@ chip soc/intel/alderlake register "desc" = ""USB2 Type-C Port C1 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 2))" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port2 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, LEFT, ACPI_PLD_GROUP(1, 3))" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, LEFT, ACPI_PLD_GROUP(3, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi |