summaryrefslogtreecommitdiff
path: root/src/mainboard/google/brya/variants
AgeCommit message (Collapse)Author
2021-09-17mb/google/brya: Add WWAN poweroff sequenceEric Lai
Follow FIBOCOM_L850-GL Hardware User Manual_V1.0.8. BUG=b:180166408,b:187691798 TEST=measure WWAN power off by scope is meeting the spec. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I6b2725cd61d5b54bc7fd70a9daffd29e7b43690b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-16mb/google/brya/variants/gimble: Add fw_config probe for ALC5682-VD/ALC5682-VSMark Hsieh
ALC5682-VD/ALC5682-VS use different kernel driver by different hid name. Update hid name depending on the AUDIO field of fw_config. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:200009010 TEST=ALC5682-VD/ALC5682-VS audio codec can work Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I09c7830fff6b318cf1a1f4a44ee0a819691f7c58 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57673 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-16mb/google/brya/variants/kano: Add MIPI camera supportDavid Wu
Add MIPI camera support for OVTI2740 BUG=b:196937374 b:194926283 TEST=Build and boot on Kano Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I248c64b9460c898f9faa5f7ac8cf339a9c814013 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-16mb/google/brya/var/redrix: Add fw_config probe for eKT3764/eKT3644Wisley Chen
Report different ACPI device depending on TP_SOURCE field of fw config (SSFC-bit8~bit9) for elan touchpad. BUG=b:199503876 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I15781c2d942d81e11c296ea2f2586ba82f67e4a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-16mb/google/brya/var/redrix: Select camera module based on SSFC valueArec Kao
This patch has changes to support multiple camera modules, base on the value set in the SSFC_CONFIG. BUG=b:198235323 TEST=tested the changes with redrix 5MP(ov5675/hi556) camera. Change-Id: I71c8355617171ec7d08862759b87d4bf12ce2924 Signed-off-by: Arec Kao <arec.kao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57272 Reviewed-by: Andy Yeh <andy.yeh@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-16mb/google/brya: Fix brya0 WWAN poweron sequencingTim Wawrzynczak
The PCIe WWAN module used on brya0 requires control over 4 signals to successfully power it on. It is desirable to do this before passing control to the payload, because the modem requires a ~10 seconds initialization phase before it can be used. The corrected sequence looks like: 1) Drive device into full reset and enable power in bootblock 2) Deassert FCPO in romstage, after power rails stabilize 3) Deassert WLAN_RST#, then WLAN_PERST# in ramstage BUG=b:187691798 Change-Id: I10f15a4dcfd86216c334fb24b4693ea250d35ee4 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-09-16mb/google/brya: Update state of BB_RT_FORCE_PWR gpiosTim Wawrzynczak
This GPIO is used to force the USB retimers on Type-C ports to stay in a powered state and can be used e.g., during a firmware update to the retimer to force power on even when no device may be connected to the port. However, its power rail is controlled elsewhere and coreboot is not applying a FW update, so this GPIO should be driven low instead. BUG=b:193402306 TEST=compile Change-Id: I976a0b8252b31aacef476d5ee4bcf6b1ef2e79de Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-09-16mb/google/brya/var/redrix: Add privacy screenWisley Chen
Add privacy screen support. BUG=b:198188272 TEST=build and check SSDT Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Ied9d9138f68ba45c4d746aed1cd3f828d4ab7fae Reviewed-on: https://review.coreboot.org/c/coreboot/+/57289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-15mb/google/brya/variants/gimble: update fw_config for next build phaseMark Hsieh
Update audio FW config based on the schematic carbine_adl-p_evt_20210901.pdf BUG=b:199180746 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I4f8ee1a97dd92c7aa0131cd0a77b05f851a26b05 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57529 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-15mb/google/brya/var/felwinter: Add R4/R5 for dmicEric Lai
Based on latest schematic (0903) update the GPIO table. BUG=b:197308586 BRANCH=None TEST=emerge-brya coreboot Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie79ba14859f7fa4ea66a0f0d58287f4515d01baf Reviewed-on: https://review.coreboot.org/c/coreboot/+/57636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-09-15mb/google/brya: Add support for romstage GPIO tableTim Wawrzynczak
Some variants may require more complex power sequencing than can be accomodated with just 2 GPIO tables, therefore introduce one in romstage as well. BUG=b:187691798 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7a63a2ee2cd036b9ae5822be9c87d8a026a54922 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-09-15brya/gimble: add `get_wifi_sar_cbfs_filename()` in variant.cMark Hsieh
gimble only uses one WiFi SAR table, contained in a file named wifi_sar_0.hex BUG=b:189068477 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ied030b79183cc6f962674260e7a82a7261b317ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/57616 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-11mb/google/brya: Replace white space with tabSubrata Banik
This patch unifies line indentation. Change-Id: Ieeb580057d8abb20afe3a5d73f5f835e6d31c899 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-09mb/google/brya/variants/kano: Update GPIOs config for kanoDavid Wu
Update the GPIO configuration to match the latest schematic. BUG=b:192370253 BRANCH=None TEST=FW_NAME=kano emerge-brya coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I96be95a127f42b005d97a3c02650af13419524a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-09mb/google/brya/variants/primus: update for next build phaseMalik_Hsu
According to the schematic diagram of version C14_MB_20210902A_SB, modify the settings of GPIO and fw_config. BUG=b:197700276 BRANCH=none TEST=emerge-brya coreboot Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I14907faeb631193715b1e0e451e427fb79a68279 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-09mb/google/brya/variants/taeko: Add initial fw config for taekoJoey Peng
According to config.star fw mask definition, add initial FW_CONFIG id. BUG=b:194649740 TEST=FW_NAME=taeko emerge-brya coreboot chromeos-bootimage Cq-Depend: chrome-internal:4072654 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ifef750338d777b76e9710d6bca9a166120db6a0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-08mb/google/brya/var/redrix: Enable SaGv supportWisley Chen
Enable SaGv support for redrix BUG=b:198536984 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I54402dfde5db4106a4e0d891c19592fda39a1099 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-07mb/google/brya/variants/gimble: update fw_config.c for next build phaseMark Hsieh
Update fw_config.c based on the schematic carbine_adl-p_evt_20210901.pdf BUG=b:190688567 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I240c0cd777d215e46a0a661aaac63a187311019d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-07mb/google/brya/variants/gimble: add GPP_B4 and GPP_D11 to early_gpio_tableMark Hsieh
NVMe needs extra time to run boot process, enable power and deassert reset for NVMe earlier in the boot flow that gimble can successfully boot into OS with non-serial coreboot. BUG=b:198405404 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ib76965db2a6cd0c19be4043fec73af297a619c7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57359 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-07mb/google/brya/variants/gimble: Enable SaGv supportMark Hsieh
This patch enables SaGv support for gimble. BUG=b:198531517 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I29887418827614afb10558c6958c9c5e9667079e Reviewed-on: https://review.coreboot.org/c/coreboot/+/57357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Marx Wang <marx.wang@intel.com>
2021-09-03mb/google/brya/variants: fix override values for power limitsSumeet Pawnikar
There are two different types of 682 SKU available with TDP of 28W and 45W. This patch fix override values for power limits for these 682 SKU. This patch also sets power limit values dynamically based on machine ID and CPU TDP of SKU. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I796e56321ae9c8312530a4b8986cd73a2245f5fa Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57290 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-02mb/google/brya: Fix Idle S0ix issue due to dynamic GPIO PM disabledMeera Ravindranath
GPIO PM was disabled for brya to evaluate if longer interrupt pulses are required for ADL. Since ADL requires 4us long pulses (EDS:626817), GPIO PM can be enabled. All devices currently tested on brya support 4us long pulses. This change drops the GPIO PM override and re-enables dynamic GPIO PM. TEST=Boot brya to OS, ensure no TPM errors. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I0c7b66b5514d8b80775ab7578ce7b12181af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56926 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-02mb/google/brya/variants/brask: Enable PCIE port 7 for EthernetDavid Wu
Enable PCIE port 7 using clk 6 for RTL8125 Ethernet BUG=b:193750191 BRANCH=None TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ic60a66dbd6ad87cf9c0de85ca7df4d854c371bf5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-01mb/google/brya/var/redrix: adjust uid for Maxim ampWisley Chen
DEV0 - 0x3a i2c-MX98390:00: Right Speaker DEV1 - 0x3b i2c-MX98390:01: Left Speaker DEV2 - 0x38 i2c-MX98390:02: Right Tweeter DEV2 - 0x39 i2c-MX98390:03: Left Tweeter This is to consist with other 2 speakers configs, and m/c driver design. uid0/1 = regular speakers. uid2/3 = tweeter BUG=191931762 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I0a3183b1e1ecbb109258d6e076551158e0b40ce1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-31mb/google/brya/var/gimble: Include SPD for K4UBE3D4AA-MGCRMark Hsieh
Add SPD support to gimble for LPDDR4 memory part K4UBE3D4AA-MGCR. BUG=b:191574298 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ida21fd50129412af59a341dea45232fd0f9931ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/57253 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-30mb/google/brya/var/felwinter: Update gpio tableEric Lai
Based on latest schematic to update the gpio table. BUG=b:197308586 BRANCH=None TEST=emerge-brya coreboot Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I0d91199ffd2128a136ea0a33dfe7affa77ae61d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-30mb/google/brya/var/felwinter: Update device treeEric Lai
Based on latest shcematic to update the device tree. BUG=b:197308586 BRANCH=None TEST=emerge-brya coreboot Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I59601571c5e4c2d19738cb333605fb22e1ea0d2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/57167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-28soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by defaultFelix Singer
Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the default by changing its enum value to 0 and remove its configuration from all related devicetrees. If `common_soc_config.chipset_lockdown` is not configured with something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT` is used. Also, add a release note for the upcoming 4.15 release. Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-28mb/google/brya/variants/primus: update USB 2.0 controller Lane ParameterCasper Chang
Modify USB 2.0 port5 parameter to improve SI diagram measurement. BUG=b:187992881 TEST= Pass USB 2.0 SI Eye diagram measurement. Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I1eff05a7ad6563898744c24f9657e28625319873 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-28mb/google/brya/var/anahera: Generate SPD ID for supported partsWisley Chen
Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. MT53E1G32D2NP-046 WT:A H9HCNNNBKMMLXR-NEE K4U6E3S4AA-MGCR MT53E512M32D2NP-046 WT:E H9HCNNNCPMMLXR-NEE K4UBE3D4AA-MGCR H9HCNNNFAMMLXR-NEE MT53E2G32D4NQ-046 WT:A MT53E512M32D1NP-046 WT:B MT53E1G32D2NP-046 WT:B BUG=b:197850509 TEST=build pass Change-Id: Ib7bdab1396138d728ae053c30656a9c80dddaff8 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-28mb/google/brya: Add two sensors for DPTF functionalitySumeet Pawnikar
Add two thermal sensors for fan and wwan for DPTF based thermal control. BRANCH=None BUG=b:181271666 TEST=None Change-Id: Idc9bd6040c9bb316ec7e314f5e9c937c75cfc95a Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Boris Mittelberg <bmbm@google.com>
2021-08-28mb/google/brya: Create anahera variantWisley Chen
Create the anahera variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:197850509 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_ANAHERA Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Id7649d56a8d6f85d12208f7ddaf2f71a7fe98e8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/57187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-27mb/google/brya/variants/primus: Enable SaGv supportAriel Fang
This patch enables SaGv support for primus. BUG=b:196286180 Signed-off-by: Ariel Fang <ariel_fang@wistron.corp-partner.google.com> Change-Id: I00074e348dd6347602c18dcfd231a890153b4685 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-26mb/google/var/redrix: Correct the WWAN_PERST_L settingWisley Chen
WWAN_PERST_L (GPP_E0) is wrongly configured to NC in ramstage. So, remove it. BUG=b:192052098 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: If8e96045a0d78a942f77d8d8e371ab75dff0c202 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-26mb/google/brya/variant/redrix: Correct MAX98390 AMP settingWisley Chen
4 MAX98390 Speaker Amps are connected to i2c0 and device addresses are 0x38/0x39/0x3a/0x3b BUG=b:191931762 TEST=FW_NAME=redrix emerge-brya coreboot chromeos-bootimage Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Ie8f01e6a7e09e18f6d34f3ceb1db8e2e238197bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/57114 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-25mb/google/brya/variants/gimble: Correct I2C slave address and update gpio.cMark Hsieh
1. According to the Maxim's comment and schematic diagram of proto, Modify I2C slave address to 0x38, 0x3c. 2. According to the schematic diagram of proto, Change GPD11 to NC. BUG=b:191811888, b:1191213263 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ibf8adf2ed8dda9ae6da06e7e995bef9395cdee35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57059 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-25mb/google/brya/primus: modify HID to MX98357A to enable audio functionCasper Chang
Primus has MX98360A, which Linux kernel 5.10 currently does not support and, therefore, audio does not work. As the device is compatible with the MX98357A, use that until Linux’ SoF driver supports the new version (https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3070268). BUG=b:194749863 BRANCH=none TEST=build coreboot and audio function works Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I893d9a31dc2c7726599c150be01b9585fb6c8a47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-25mb/google/brya: Fix PL4 limitsTim Wawrzynczak
Commit e7f3e6a0558 added PL4 limits for brya0, but the units were mW, whereas the `tdp_pl4` field is expected to be in whole Watts, therefore divide all of the settings by 1000. BUG=b:197468828 TEST=boot brya0 to OS Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6da6bae4eb8c83188d813828cdc4f7c1e20f1b5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-08-24mb/google/brya/variants/kano: Init devicetree for kanoDavid Wu
Init basic override devicetree based on schematics BUG=b:192370253 TEST=FW_NAME=kano emerge-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I283517427612e24eabe2ce736d677253065c7859 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24mb/google/brya: Enable SaGv supportV Sowmya
This patch enabled the SaGv support for brya0 baseboard. BUG=b:187446498 Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I2a71e159fa49f677660af8279f2b582a3916eee2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24mb/google/brya/var/felwinter: Generate RAM ID and SPD fileEric Lai
Add the support RAM parts for felwinter. Here is the ram part number list: DRAM Part Name ID to assign K4U6E3S4AA-MGCR 0 (0000) K4UBE3D4AA-MGCR 1 (0001) H9HCNNNBKMMLXR-NEE 0 (0000) MT53E1G32D2NP-046 WT:A 2 (0010) BUG=b:197308861 BRANCH=None TEST=emerge-brya coreboot Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I76febefc251b02a047819242e23c02dc50891c2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-22mb/google/brya/var/brya0: Align comments in overridetreePaul Menzel
Change-Id: Id3eb18cae2dd9a7b148bc9f3dcaf387f35dbd2fb Fixes: 312fb716 ("mb/google/brya: Add ALC1019_NAU88L25B support") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-08-20mb/google/brya: Add ALC1019_NAU88L25B supportEric Lai
Add ALC1019_NAU88L25B DB support. BUG=b:195891240 TEST=audio is functional when playing youtube. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I9209c4cab00fc03b2a6107b5c32804786cd2e242 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-19mb/google/brya: set tcc_offset value to 10Sumeet Pawnikar
Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature. This value is suggested by Thermal team. BUGb=b:195706434 BRANCH=None TEST=Built for brya platform and verified the MSR value Change-Id: I22573e8ca935d99a16b0876768df169db4e61c4d Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57000 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-19mb/google/brya/variants/primus: Fix GL9755S power sequenceMalik_Hsu
- Enable EN_PP3300_SD - Configure SD_PE_RST_L correctly BUG=b:195625340 TEST=Able to boot with SD card Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I33c17e88cabdc9b13634fc8f341aa6a09b7bfde5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-16mb/google/brya/var/redrix: Generate SPD ID for supported partsWisley Chen
Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. MT53E512M32D1NP-046 WT:B MT53E1G32D2NP-046 WT:B BUG=b:192052098 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I61377e6cdd3af9d6d80b9e1e68191b39f43358ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/56969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-16mb/google/brya: Add I2C parameterEric Lai
Add I2C parameters to make sure each bus speed is around 390kHz. BUG=b:188793264 TEST=Measure by scope. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib47228b8684c44f6acfec9e9e4b6e7b18ba6f6c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-16mb/google/brya/variants/kano: Configure GPIOs according to schematicsDavid Wu
Update initial gpio configuration for kano BUG=b:192370253 TEST=FW_NAME=kano emerge-brya coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I4d6099fa8d17bebf798ddf236a68886087e2a95e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-16mb/google/brya: Configure EN_FCAM_PWR to highVarshit B Pandya
Recent change "7a8c68a: mb/google/brya: Configure H21 as GPO and A17 as low" turned EN_FCAM_PWR low since EN_FCAM_PWR is turned ON and OFF by IPU driver while MIPI UFC probing. However USB UFC also requires 3.3V which is enabled by A17. This caused USB UFC enumeration to fail BUG=b:196014678 Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I88c204ec07b1f7511f0d88074e336cfc9116a7d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56882 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16mb/google/brya/primus: Fix G2 touchscreen reset GPIO polarityCasper Chang
modify reset_gpio as active low to meet touchscreen spec BUG=b:195490284 BRANCH=none TEST=build coreboot and touchscreen works Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I7ce1b3025db8abebf5693b34da846a7e969246fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/56923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-16mb/google/brya: allow MKBP devices and disable TBMC deviceBoris Mittelberg
Enable MKBP (Matrix Keyboard Protocol) interface for all Brya family to use for buttons and switches. Disable TBMC (Tablet Mode Switch device), as it is not needed anymore. BUG=b:170966461 TEST=manual test on Brya P1: Volume Up/Down buttons Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: Ic9c707f57871f388c363e01c9ab78a3b358ce728 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-15mb/google/brya: set PL4 value dynamically for thermalSumeet Pawnikar
Set PL4 value dynamically for brya board based on CPU SKUs which is detectable at runtime. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 with below messages, On brya (282): Overriding DPTF power limits PL1 (3000, 15000) PL2 (39000, 39000) PL4 (100000) On brya (482): Overriding DPTF power limits PL1 (4000, 28000) PL2 (43000, 43000) PL4 (105000) Change-Id: I20b98ccd8493ed238de647cda8ceb25f62029133 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-15mb/google/brya/{redrix,taeko}: Deduplicate lockdown configFelix Singer
Lockdown configuration is done in their baseboards. Thus, remove the setting from the variants overridetree. Change-Id: Iadb1201718466503987e4f6bd72bf711a2d3128e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-13mb/google/brya/variants/brya0: add PL4 values for different SKUsSumeet Pawnikar
Add PL4 values for brya0 board for different CPU SKUs. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 with below messages, On brya (282): Overriding DPTF power limits PL1 (3000, 15000) PL2 (39000, 39000) PL4 (100000) On brya (482): Overriding DPTF power limits PL1 (4000, 28000) PL2 (43000, 43000) PL4 (105000) Change-Id: I095e9eda6665fd1927f35ee57d52922eddd8227a Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-12mb/google/brya/variants/redrix: enable LTE PCIe portWisley Chen
Enable LTE PCIe port according to fw config. BUG=b:192052098 TEST=emerge-brya coreboot chromeos-bootimage Change-Id: Ic9472d2249c622858a75c63bc82e8e4e8166a3d7 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56894 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12mb/google/brya/variants/redrix: add mipi camera supportWisley Chen
Add mipi camera support by selecting the Kconfig symbols and adding it to the devicetree with ACPI UID 0x50000 and name IPU0. BUG=b:192052098 TEST=checked mipi camera works Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I69281f36ddbc1abf9905c8db9287500f9aa995c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56893 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12mb/google/brya/variants/gimble: Update GPIO for PP1800 DMIC enableMark Hsieh
add GPP_D16 in gimle gpio.c and set value to 1 for PP1800 DMIC init sequence BUG=b:195968649 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ia0639162e2c3f02f622470fa16c21fe8a067cf7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56889 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-11mb/google/brya/variant/taeko: Update devicetree settingsJoey Peng
Based on schematic and gpio table of taeko, generate overridetree.cb settings for taeko. BUG=b:195494281 TEST=FW_NAME=taeko emerge-brya coreboot chromeos-bootimage Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I96aaf48284a226edc39115f870bf0f3dd83ab8b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-10mb/google/brya/variants/primus: Remove DPTF fan controlScott Chao
BUG=b:195901486, b:195387997 BRANCH=none TEST=Check fan is able to control by EC Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: If758d75ff24c88c9eaf0de90ac0ef08d172a2edd Reviewed-on: https://review.coreboot.org/c/coreboot/+/56879 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-10mb/*/{brya,adlrvp}: move cpu_cluster static configuration to chipset.cbMAULIK V VAGHELA
For mainboard devicetree, it always have definition for enabling cpu_cluster 0 which is required for all the variants. Since it is SoC related settings, it's better to keep in chipset.cb as a common setting for all the mainboards using the same SoC. BUG=None BRANCH=None TEST=Change has no functional impact on the brya board. Change-Id: I8f7c3184b62f8d84ca4605fb9f2a1cc569f1f964 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56853 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-10mb/*/brya/adlrvp: Remove hardcoding of BSP APIC IDMAULIK V VAGHELA
coreboot always assumes that BSP APIC ID will be 0 and core enumeration logic will look for lapic id from the mainboard. As per Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 3: 8.4.1 BSP and AP Processors, this assumption might not hold true and we may have any other core as BSP. To handle this, we need to remove hardcoding of APIC ID 0 from mainboard. BUG=None BRANCH=None TEST=Check if there is no functional impact on the board. Change-Id: Ibc60494b0032a3139c1e6c79251fb2da750c8de8 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-08-10mb/google/brya/variant/taeko: Update memory settingsJoey Peng
Based on the Taeko's schematic, generate memory settings. BUG=b:161089195 TEST=FW_NAME=taeko emerge-brya coreboot chromeos-bootimage Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I4e23c28aaf20d9e52b43033b4e41c751e26872bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/56766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-09mb/google/brya/variants/taeko: Configure GPIOs according to schematicsJoey Peng
Update initial gpio configuration for taeko BUG=b:195252436 TEST=FW_NAME=taeko emerge-brya coreboot Change-Id: Ida1edbf874c93f6efac45c276920ead9311ac6f2 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-09mb/google/brya/variants/brya0: set power limits for thermalSumeet Pawnikar
Set power limits for brya0 variant board based on CPU SKUs which is detectable at runtime. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 variant board with below messages, On brya (282): Overriding DPTF power limits PL1 (3000, 15000) PL2 (39000, 39000) On brya (482): Overriding DPTF power limits PL1 (4000, 28000) PL2 (43000, 43000) Change-Id: I4c07319af756b10e5d22f320e97ff956fb4a14c6 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56622 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-09gimble: enable elan touchscreenScott Chao
Enable Elan touchscreen and remove Goodix touchscreen. We also get confirmation by Elan that address is 0x15. BUG=b:195494292 BRANCH=none TEST=build coreboot and dmesg | grep hid, it showed i2c-ELAN9050:00. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I20a7fd0b370803c14990b77bab302727af197ccb Reviewed-on: https://review.coreboot.org/c/coreboot/+/56801 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-09mb/google/brya: create dynamic power limits mechanism for thermalSumeet Pawnikar
Add dynamic power limits selection mechanism for brya board based on CPU SKUs which is detectable at runtime. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya with below messages, On brya (282): Overriding DPTF power limits PL1 (3000, 15000) PL2 (39000, 39000) On brya (482): Overriding DPTF power limits PL1 (4000, 28000) PL2 (43000, 43000) Change-Id: I86619516adeec13642f02ba7faf9fc4945ad774e Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-05mb/google/brya/variants/gimble: add TcssAuxOriScott Chao
Gimble don't have retimer on port0, the port need to be configured for the SOC to handle Aux orientation flipping. Also add "typec_aux_bias_pads" lets the SoC IOM firmware control the Aux DC bias voltages. BUG=b:195087071 BRANCH=none TEST=check both orientation can output display on type-c monitor. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I057048c14110bb81bf5b5fd0e3151deb031ca5d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-05mb/google/brya/variants/primus: enable PS2 interfaceCasper Chang
BUG=b:187969783 Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I1e063524cfa4121c38cfed23e95557953511d884 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-04mb/google/brya/variants/gimble: Remove DPTF fan controlScott Chao
BUG=b:195378817 BRANCH=none TEST=Check fan is able to control by EC Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I84c020e470194072bb796f75f8a1304832504469 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56768 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-04mb/google/brya/variants/gimble: Update overridetree for gimbleMark Hsieh
According to the schematic diagram of proto, added drivers/i2c/max98390 to device ref i2c0 and deleted device ref hda. BUG=b:191811888 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I0f0a8c84db3fbc963797d11246c5d31b395bb744 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-03mb/google/brya: Add RTD3 for WWANThejaswani Putta
Enable the PCIe RTD3 driver for WWAN device attached to PCIe Root Port 6 and provide the reset GPIO / src clk pins. BUG=None BRANCH=None TEST=Build and boot the coreboot image, check if device is enumerated in the lspci list after warm/cold reboot cycles, run suspend cycles and check if WWAN is entering L2 LPM. Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com> Change-Id: Ie9d1ce55cc1297ea0e1069979bbecfaac8f8de05 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2021-08-03mb/google/brya/variants/primus: configure correct type-c portScott Chao
BUG=b:195274799 TEST=USE="project_primus" emerge-brya coreboot and verify it builds without error. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I4abf7b2d98b188735ef79f8ffbee4c02099ec021 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56583 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-03mb/google/brya: Introduce new baseboard braskZhuohao Lee
This patch initiates the brask setting which includes the gpio and device tree setting. BUG=b:191472401 BRANCH=None TEST=build pass Change-Id: I1bb42c7bb2492402de0810bc4ab2e8d8c0e2392b Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-03mb/google/brya: Create felwinter variantIan Feng
Create the felwinter variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:194431541 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_FELWINTER Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: Iff2b9daec40995a013f9fe0dd76ad667d1807d1b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56765 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02mb/google/brya/variants/redrix: Init devicetree for redrixWisley Chen
Init basic override devicetree based on schematics BUG=b:192052098 TEST=FW_NAME=redrix emerge-brya coreboot chromeos-bootimage Change-Id: I9fb752fe8280893b84c172d8a519578fa4220184 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-08-02mb/google/brya/variants/gimble: configure correct type-c portScott Chao
Change TypeC port1 usb3 port="3". BUG=b:194472269 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: Iaba27aad2adfb0a9e83058ac756ca46a762107bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/56545 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02mb/google/brya: Update entries for UFC to support IMX208Varshit B Pandya
1. Replace OV5675 ACPI entries with IMX208 2. Replace FW_CONFIG name 3. Add support for NVM inside UFC BUG=b:190674542 TEST=Build and boot to OS on Brya, raw capture on UFC Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I6a3bf13ec844fb46e11ce58382057fcc7187c135 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-08-02mb/google/brya: Configure H21 as GPO and A17 as lowVarshit B Pandya
As per the schematics, UFC has on card oscillator so we donot need H21 in NF1 that is IMGCLKOUT H21 is used to enable this oscialltor so configuring it as 1 A17 is configured as high while _ON method is called by driver and it is configured as low when _OFF method is called by driver. Hence coreboot should configure it as low on boot. BUG=b:190674542 Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I745169a5ab6a9c20b6e1bda792a43193d04ac48d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56655 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-30mb/google/brya/variants/primus: Disable PCIe6Malik_Hsu
WWAN (fibocom L850-GL) works in USB mode, so turn off PCIe 6. BUG=b:194861116 Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: Ie04a5bb2af9ce11f57339f460a7f880bfc14b688 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-29mb/google/brya: add BASEBOARD_DIR to support different baseboardZhuohao Lee
In order to support different baseboard configuration, we add the BASEBOARD_DIR to switch the directory. The expected structure looks like: mb ..|_ google .........|_ brya .............. |_ variants .....................|_ baseboard ..............................|_ brya ....................................|_ gpio.c ....................................|_ memory.c ....................................|_ devicetree ..............................|_ brask ....................................|_ gpio.c ....................................|_ memory.c ....................................|_ devicetree ......................|_ brya_variant1 ......................|_ brya_variant2 ......................|_ ... ......................|_ brask_variant1 ......................|_ brask_variant2 ......................|_ ... ...............|_ <all mb common code> BUG=b:191472401 BRANCH=None TEST=build pass Change-Id: Ic99e42dbbd27fa3e1f6cb3a1b5daee1c8c7b1083 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-07-28mb/google/brya/var/kano: Generate SPD ID for supported partsDavid Wu
Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. MT53E512M32D1NP-046 WT:B MT53E1G32D2NP-046 WT:B H54G46CYRBX267 H54G56CYRBX247 K4U6E3S4AB-MGCL K4UBE3D4AB-MGCL BUG=b:194766276 b:194686484 b:194765811 TEST=build Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Iba019c50224be8322865eee7baf81e3a574ff9a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-07-28mb/google/brya/variants/primus: Update NVMe clkMalik_Hsu
According to the schematic diagram of proto, modify the clock of nvme from the baseboard default to src0. BUG=b:194487277 Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I41be517b434513bca2332ec37e54f56910302bb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-26mb/google/brya: Deduplicate chipset lockdown configFelix Singer
Due to an issue in sconfig, move `chipset_lockdown` out of `common_soc_config` and configure it separately in the baseboard's devicetree since it might get overwritten if a variant configures `common_soc_config`. Also, deduplicate the configuration of `chipset_lockdown`. Change-Id: Id969346df06aa82ab2ad2b1aa4884a9bcd876d75 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56408 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/google/brya: Enable BT offload conditionallySugnan Prabhu S
Currently, BT offload is disabled/enabled unconditionally based on the devicetree settings. BT offload uses I2S lines and cannot be enabled when a I2S based audio daughter card is active. So we need to enable BT offload only while using soundwire based audio daugther card. BUG=b:175701262 TEST=Verified BT offload on brya with soundwire audio daughter card BT offload enabled Change-Id: I6a9ad463e13e2cfcfc3b7de5a61a25cdef0641f7 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-22mb/google/brya/variants/redrix: Configure GPIOs according to schematicsWisley Chen
Update initial gpio configuration for redrix BUG=b:192052098 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I2294fb3bdba832677038cfe24b5014014c7f03e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56428 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21mb/google/brya/variants/primus: Update two GPIOsariel fang
1. Move M2_SSD_PLN_L to GPP_D3 for power loss notify function. 2. Set GPP_E21 as NC to remove LCLW_DET function BUG=b:190643562 Signed-off-by: Ariel Fang <ariel_fang@wistron.corp-partner.google.com> Change-Id: Id3c60adeb5d35c79a1c700937f93a80ad3587c5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56420 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21mb/google/brya: Program Unused Cnvi BT related GPIOs to NCMaulik V Vaghela
Program unused Cnvi BT UART GPIOs as NC since we are using Bluetooth over USB mode for Brya. Change-Id: I33a37ceb8a91603d2a193de5bdd1b6885eb3c319 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55317 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21mb/google/brya: Create taeko variantKevin Chang
Create the taeko variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:193685558 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_TAEKO Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: If738849bc3103c52a4c4d8a8aaef3f90a62ad5c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56385 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21mb/google/brya/var/gimble: Include SPD for MT53E1G32D2NP-046 WT:A and ↵Mark Hsieh
K4U6E3S4AA-MGCR Add SPD support to gimble for LPDDR4 memory part MT53E1G32D2NP-046 WT:A and K4U6E3S4AA-MGCR. BUG=b:191574298 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I4bfc18fd42c6ff2675e6f836c2ecc9617fac3aff Reviewed-on: https://review.coreboot.org/c/coreboot/+/56329 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21mb/google/brya: Add variant specific soc chip config updateSugnan Prabhu S
This patch adds support for variant specific soc chip config update function. Change-Id: Ic3a3ae0b409433e6dfa102c5e7a6322d4f78f730 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-21mb/google/brya/variants/primus: add dram part idMalik_Hsu
This change adds mem_parts_uesd.txt that contains the new memory parts used by primus and Makefile.inc generated by gen_part_id.go using mem_parts_used.txt. BUG=b:193813079 Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I6aa37114f3a164a4f3c35dfc9b43e1106b825bff Reviewed-on: https://review.coreboot.org/c/coreboot/+/56366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-21Revert "mb/google/brya: Enable south XHCI ports 1 and 2"Tim Wawrzynczak
This reverts commit f7f715dff38c4a629139b2493ed6e0d7cc2eb36f. Reason for revert: FSP 2207.01 uses the UsbTcPortEn UPD for TCSS XHCI enable BUG=b:184324979 TEST=boot brya, all 3 USB Type-C ports still enumerate devices Change-Id: I82bae21d185247bc0f3580fd6f92abb8eece6732 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56132 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.corp-partner.google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12mb/google/brya: Update generic device number for mipi_camera deviceVarshit B Pandya
If two generic devices use the same number, device coming later overrides the earlier device, as a result of this the static.c has only one device. In the case where we have UFC set to UFC_USB, this will result in no IPU device scope in SSDT, since its entry will be set to disbled after UFC probe. TEST=Build, Boot and Check UFC camera preview with UFC=UFC_USB Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I034cb7da787313d1cb53484922149589ac0f1c5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12mb/google/brya,primus,voxel: Update controller field for tbt_dma entriesMaulik V Vaghela
We need to reference correct USB port number for driver to identify type-C port number correctly. BUG=b:189476816 BRANCH=None TEST=Check the transactions are happening on correct port. Also checked retimer firmware update on both the ports. Change-Id: I20c088ee81610155067abad086eba8d72f73ad60 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12mb/google/brya/variants/primus: Update GPIO for PS8811 initCasper Chang
Route GPP_D14 to USB_A1_RT_RST_ODL for PS8811 init sequence BUG=b:193099675 Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: Ia950da61a50f30f7c4aaef572c5ed162ee76dd0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12mb/google/brya: Create kano variantDavid Wu
Create the kano variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:193052432 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_KANO Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ib0670e346c113291054cb92fb57aae52f844e8c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56155 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-08mb/google/brya/var/redrix: Generate SPD ID for supported partsWisley Chen
Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. MT53E1G32D2NP-046 WT:A H9HCNNNBKMMLXR-NEE K4U6E3S4AA-MGCR MT53E512M32D2NP-046 WT:E H9HCNNNCPMMLXR-NEE K4UBE3D4AA-MGCR H9HCNNNFAMMLXR-NEE MT53E2G32D4NQ-046 WT:A BUG=b:190818098, b:190874372, b:192052098 TEST=build Change-Id: I62ee401e43bef22b4b09f41ea59bbdbc479f293c Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55885 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-08mb/google/brya: Create redrix variantWisley Chen
Create the redrix variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:192052098 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_REDRIX Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I4cfa0bd84e1ba9f8140f95d18a6da960da8124ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/55883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-07-08mb/google/brya0: Update the FIVR configurationsV Sowmya
This patch sets the disable the external voltage rails since brya board doesn't have V1p05 and Vnn bypass rails implemented. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I1c4fdb38c5c56798935b2c6627a75c3f1ac9fbef Reviewed-on: https://review.coreboot.org/c/coreboot/+/55704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-05mb/google/brya: Add HANG_DETECT host event to EC S0ix wake maskTim Wawrzynczak
The brya EC supports S0ix hang detection, but it was not enabled in coreboot as well, masking that event out of S0ix, therefore add it in to the EC S0ix wake mask. TEST=After EC prints "Warning: Detected sleep hang! Waking host up!", the host actually wakes up Change-Id: I2c699114abcd9a045a41858c731e4b6fe99d3000 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-08 05:09:38 +0000