diff options
| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | 2021-07-23 15:50:17 +0530 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-08-09 15:02:56 +0000 |
| commit | 582829d9acaa899d8381f2b44a82f54da42b87a1 (patch) | |
| tree | 60a48466d488fb7890dd0f47c75b17143958f2d7 /src/mainboard/google/brya/variants | |
| parent | 09cc8f6677ad99eee99a18bfcd8ce1350b3efc52 (diff) | |
mb/google/brya: create dynamic power limits mechanism for thermal
Add dynamic power limits selection mechanism for brya board based on
CPU SKUs which is detectable at runtime.
BUG=b:194745919
BRANCH=None
TEST=Build FW and test on brya with below messages,
On brya (282):
Overriding DPTF power limits PL1 (3000, 15000) PL2 (39000, 39000)
On brya (482):
Overriding DPTF power limits PL1 (4000, 28000) PL2 (43000, 43000)
Change-Id: I86619516adeec13642f02ba7faf9fc4945ad774e
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/variants')
3 files changed, 60 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/Makefile.inc b/src/mainboard/google/brya/variants/baseboard/brya/Makefile.inc index 1d38b77ea0..9665436d28 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/Makefile.inc +++ b/src/mainboard/google/brya/variants/baseboard/brya/Makefile.inc @@ -3,3 +3,4 @@ bootblock-y += gpio.c romstage-y += memory.c ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c b/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c new file mode 100644 index 0000000000..35cb48835e --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi_device.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <device/pci_ops.h> +#include <soc/pci_devs.h> + +#include <drivers/intel/dptf/chip.h> + +void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries) +{ + if (!num_entries) + return; + + const struct device_path policy_path[] = { + { .type = DEVICE_PATH_PCI, .pci.devfn = SA_DEVFN_DPTF}, + { .type = DEVICE_PATH_GENERIC, .generic.id = 0} + }; + + const struct device *policy_dev = find_dev_nested_path(pci_root_bus(), + policy_path, ARRAY_SIZE(policy_path)); + if (!policy_dev) + return; + + struct drivers_intel_dptf_config *config = policy_dev->chip_info; + + uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); + + for (size_t i = 0; i < num_entries; i++) { + if (mchid == limits[i].mchid) { + struct dptf_power_limits *settings = &config->controls.power_limits; + settings->pl1.min_power = limits[i].pl1_min_power; + settings->pl1.max_power = limits[i].pl1_max_power; + settings->pl2.min_power = limits[i].pl2_min_power; + settings->pl2.max_power = limits[i].pl2_max_power; + printk(BIOS_INFO, "Overriding DPTF power limits PL1 (%u, %u) PL2 (%u, %u)\n", + limits[i].pl1_min_power, + limits[i].pl1_max_power, + limits[i].pl2_min_power, + limits[i].pl2_max_power); + } + } +} diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h index c938de820d..b992129a55 100644 --- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h @@ -22,4 +22,19 @@ int variant_memory_sku(void); bool variant_is_half_populated(void); void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config); +/* Modify devictree settings during ramstage */ +void variant_devtree_update(void); + +struct cpu_power_limits { + uint16_t mchid; + unsigned int pl1_min_power; + unsigned int pl1_max_power; + unsigned int pl2_min_power; + unsigned int pl2_max_power; +}; + +/* Modify Power Limit devictree settings during ramstage */ +void variant_update_power_limits(const struct cpu_power_limits *limits, + size_t num_entries); + #endif /*__BASEBOARD_VARIANTS_H__ */ |