diff options
| author | Casper Chang <casper_chang@wistron.corp-partner.google.com> | 2021-08-27 16:34:03 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-08-28 17:44:51 +0000 |
| commit | 621ae7c701033029352603f2978b7580295f59e3 (patch) | |
| tree | bcd1463edfae24dd0530c2fd43f93c881e5691fb /src/mainboard/google/brya/variants | |
| parent | 0d753e510808e66ffd5dc6ee71ff4e1db4c09ffa (diff) | |
mb/google/brya/variants/primus: update USB 2.0 controller Lane Parameter
Modify USB 2.0 port5 parameter to improve SI diagram measurement.
BUG=b:187992881
TEST= Pass USB 2.0 SI Eye diagram measurement.
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I1eff05a7ad6563898744c24f9657e28625319873
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/variants')
| -rw-r--r-- | src/mainboard/google/brya/variants/primus/overridetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index 86cdfeae0e..ec9283ee14 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -60,6 +60,7 @@ chip soc/intel/alderlake register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port register "usb3_ports[2]" = "USB3_PORT_EMPTY" + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" device domain 0 on device ref dtt on |