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path: root/src/mainboard/google/brya/variants
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2024-03-11mb/google/brya: Create nova variantDavid Wu
Create the nova variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:328711879 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_NOVA Change-Id: Ie1cee43f0e2545288130bcc5152075603695c395 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
2024-03-09mb/google/brya/var/xol: Disable unused controllersSeunghwan Kim
Disable unused controllers in overridetree.cb by referring to xol proto2 schematics. Enabling unused controllers blocks entering s0ix. - I2C3 - SATA - PCIE RP8 - PCIE RP9 - GSPI1 BUG=b:328318578 BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: I1be7caf8234c32406aa2cff8fc7fe9fa39b16d89 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81105 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-09mb/google/brya/var/xol: Update psys_pmax value to 122WSeunghwan Kim
Update psys_pmax value to 122 from 145. This value is from internal power team. BUG=None BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: I8bc58343d5736e2457db006972dc229e16d3fe59 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81104 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-09mb/google/brya/var/xol: Configure Acoustic noise mitigationSeunghwan Kim
Enable Acoustic noise mitigation for xol. The setting values are from internal power team. - Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to SLEW_FAST_4 - Set FastPkgCRampDisable VCCIA and VCCGT to 1 BUG=None TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: I6165ae6ca73d1467a1d2cc7bd545298bd4c2f54f Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81103 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-03-06mb/google/nissa/var/glassway: Tune eMMC DLL valuesDaniel Peng
Update eMMC DLL values to improve initialization reliability. BUG=b:327123701 TEST=Improve reboot on MB with eMMC smoothly. Change-Id: Ice9ee217acf7dc6e3e704bc82529e0b9a8faf184 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80779 Reviewed-by: Shawn Ku <shawnku@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Yang <simon1.yang@intel.com>
2024-03-05mb/google/brya/var/xol: Add VGPIO configurations for PEG60Seunghwan Kim
Add VGPIO configurations for NVMe on PEG60. BUG=b:326481458, b:372086400 BRANCH=firmware-brya-14505.B TEST=Verified DUT could detect NVMe. Install ChromeOS into NVMe and boot from it. Change-Id: I5520dc2a4bf6e788701a774674d223b7e8ad5b44 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-05mb/google/nissa/var/gothrax: Add probe and GPIO config for touchpanelYunlong Jia
Add FW_CONFIG probe to separate touch panel settings. TOUCH_PANEL_ENABLE/TOUCH_PANEL_DISABLE Use different gpio tables based on the value of TOUCH_PANEL. BUG=b:325987249 TEST=emerge-nissa coreboot and run in DUT Change-Id: I23c62406a932815ff1cfafe05b70468b1f9cca54 Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kyle Lin <kylelinck@google.com>
2024-03-05mb/google/brya/var/dochi: Add wifi sar tableMorris Hsu
Add wifi sar table for dochi BUG=b:326137130 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Change-Id: Iaf90756eb318bef1ffcda9368a976c0ca209a100 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-04mb/google/brya/var/xol: Update NVMe clock source index to 0Seunghwan Kim
Change ClkSrc index for NVME to 0 from 1 by referring to proto2 schematics. BUG=b:326481458 BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: I7ea1cd7d8e16d4cee953e931d2f1829eae7d1978 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80768 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-01mb/google/nissa/var/glassway: Add GPIO tableDaniel Peng
Refer to the reference board of nivviks, and update GPIO settings via glassway schematic of ca24a_r10_240108_v3_mb_gsen_gmr.pdf. BUG=b:319071869 BRANCH=firmware-nissa-15217.B TEST=Local build successfully and boot to OOBE normally. Change-Id: I0de743746160c6eb081cb9a061ac1703b01ba5b4 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-02-28mb/google/brya/var/xol: Add storage option in FW_CONFIGSeunghwan Kim
Add STORAGE config in FW_CONFIG to support NVME sku. - STORAGE_UFS : 0 - STORAGE_NVME: 1 BUG=b:326481458 BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: Id8316f643ba9a55319b67431a24a507e92419aa7 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80767 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-02-27mb/google/nissa/var/glassway: Add initial override devicetreeDaniel Peng
Refer to the reference board of nivviks, and update devicetree settings via glassway schematic of ca24a_r10_240108_v3_mb_gsen_gmr.pdf. BUG=b:319071869 BRANCH=firmware-nissa-15217.B TEST=Local build successfully and boot to OOBE normally. Change-Id: Ibbb10a373bd5fa52a0833b81133517d2a088536b Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80742 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-22mb/google/nissa/var/glassway: Generate SPD ID for supported memory partsDaniel Peng
Add supported memory parts in mem_parts_used list, and generate SPD ID for these parts. DRAM Part Name ID to assign K3KL8L80CM-MGCT 0 (0000) K3KL6L60GM-MGCT 1 (0001) H58G56AK6BX069 2 (0010) H9JCNNNBK3MLYR-N6E 3 (0011) BUG=b:319071869 BRANCH=firmware-nissa-15217.B TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\ part_id_gen.go ADL lp5 \ src/mainboard/google/brya/variants/glassway/memory/ \ src/mainboard/google/brya/variants/glassway/memory/\ mem_parts_used.txt" Change-Id: I00ae3efe8e554f44cee5a27ac88c5d65eb95f7fb Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
2024-02-21mb/google/brya/var/xol: Add support memory partsSeunghwan Kim
Add support memory parts for Xol. - Samsung K3KL6L60GM-MGCT - Samsung K3KL8L80CM-MGCT BUG=b:319506033 BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Proto board can boot to ChromeOS. Change-Id: Ic6a36e40f0f93109f296c5cc67a368ace81bd217 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80637 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-02-21mb/google/brya/var/xol: Update memory configurationSeunghwan Kim
Update memory configuration following proto schematics. BUG=b:319506033 BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Proto board can boot to ChromeOS. Change-Id: I59aabe0870317092f59701bdf88b53bf9731377a Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-02-21mb/google/brya/var/xol: Update thermal policySeunghwan Kim
Update initial DTT policy and TCC setting for Xol. The setting values are from internal power team. - Critical CPU temparature: 105 -> 99 - TCC offset: 90 -> 94 BUG=b:323989520 BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: I546b313a1e6af16029309174a5bed2d1e4aa4d11 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80410 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-02-21mb/google/nissa/var/anraggar: Change tdp_pl1_override from 6 W to 15 WWeimin Wu
Set tdp_pl1_override to 15 for performance required by the thermal team. Fix policies.critical index from 2 to 0. BUG=b:313833488 TEST=emerge-nissa coreboot Change-Id: I5341bd3d4842f9298a2f5d9e589918bb1b06ba69 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-02-21mb/google/brya: Create glassway variantDaniel Peng
Create the glassway variant of the nivviks reference board by copying the template files to a new directory named for the variant. BUG=b:319071869 BRANCH=firmware-nissa-15217.B TEST=None Change-Id: I597666a5be6f71b82c7baddbe343da3d5117dd1c Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-02-13mb/google/*: Replace use of gfx/generic addr field with display typeMatt DeVillier
Eliminates the use of a magic number, and the resulting DID entry in the _DOD method is the same. TEST=build/boot google/drallion, dump SSDT and verify DID entry is unchanged. Change-Id: Ic929cf7ec6849ba398653226bbe46d27b4e3fa81 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-13mb/google/brya/var/*: Use name 'LCD0' for internal panel outputMatt DeVillier
The GMA driver generates the brightness controls expecting the name LCD0, so we need to use it here as well so that the DSDT and SSDT parts match. TEST=build/boot Win11 on google/brya (redrix), verify brightness controls are functional. Change-Id: I389553b2ddc5b09d165229e2d8066cacf852b82c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80174 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Won Chung <wonchung@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-02-09mb/google/nissa: Skip GPP_F15 GPIO locking to avoid IRQ stormWeimin Wu
There is an existing issue for nissa where wake up from RTC wake is not working during suspend_stress_test. The phenomenon of the issue is that after pulling out the stylus, can see an interrupt storm occurs, checking through: "cat /proc/interrupts | grep acpi". When the counter of interrupt is greater than a certain value, "Disabling IRQ #9" will occur, so RTC wake is not working. Reference: https://review.coreboot.org/c/coreboot/+/65086 This patch skips the locking for GPP_F15 to allow kernel to configure it later. The interrupt storm of acpi disappears. BUG=b:321348117 TEST=1. cat /proc/interrupts | grep acpi there isn't interrupt storm of acpi when pulling out stylus. 2. The stylus tools panel will pop up when pulling out it. 3. Inserts stylus can wakeup DUT after powerd_dbus_suspend. 4. Passed: suspend_stress_test -c 2500 --suspend_min=15 --suspend_max=20 Change-Id: Ie143c43e0555d17d8a290f17637b537fba806144 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80316 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-09mb/google/nissa/var/anraggar: Config DP AUX BIAS according to fw_configWeimin Wu
EVT mini-build changes redriver IC from PS8745 to ANX7493, the ANX7493 not support DP AUX BIAS, so connects DP AUX BIAS of DB to SOC directly. Add DB_AUX_BIAS bit field to fw_config for compatibility. BUG=b:320235566 TEST=DP function of MB and DB workable Change-Id: I53974ec7444912a63d0fe0a9303c9e5d6941f68d Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80259 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-07mb/google/brya/var/xol: Update GPIO configurationsSeunghwan Kim
Upload initial GPIO configuration for xol based on proto schematics. BUG=b:319506033 BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage xol proto board can boot to ChromeOS Change-Id: I224e58628e44571c07ce034136d690587e62be08 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80325 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-07mb/google/brya/var/xol: Update Kconfig and devicetreeSeunghwan Kim
Upload the initial devicetree and update Kconfig for xol following proto schematics. BUG=b:319506033 BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot Change-Id: I411932eb4872d77993394a290e8afdd1a0038faf Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80324 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-27mb/google/nissa/var/anraggar: Enable BT audio offloadJianeng Ceng
This patch enables Cnvi BT Audio Offload feature and also configures the virtual GPIO for CNVi Bluetooth I2S pads. BUG=b:303157827 TEST=Build and boot to anraggar. Verify the config from serial logs. w/o this CL - ``` [SPEW ] -- CNVi Config -- [SPEW ] CNVi Mode= 1 [SPEW ] Wi-Fi Core= 1 [SPEW ] BT Core= 1 [SPEW ] BT Audio Offload= 0 [SPEW ] Pin Muxing ``` w/ this CL - ``` [SPEW ] -- CNVi Config -- [SPEW ] CNVi Mode= 1 [SPEW ] Wi-Fi Core= 1 [SPEW ] BT Core= 1 [SPEW ] BT Audio Offload= 1 [SPEW ] Pin Muxing ``` Change-Id: I9e6731c8ceaad6ee58b525d4246fa769bfe1b0c7 Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80001 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-27mb/google/brya/var/omniknight: Add WIFI SAR tablejamie_chen
Add WIFI SAR table for omniknight. BUG=b:320172979 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I70e79577612b3d5c4dc0f92211f87cbea0532d5d Signed-off-by: jamie_chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80152 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2024-01-25mb/google/brya/var/*: Ensure LCD device has a valid addressMatt DeVillier
Some variants added the generic gfx driver with an LCD device without specifying the address, which is required for the backlight controls to be functional under Windows. Add the address value where missing. Address value used (0x80010400) is same as on other Brya variants which did properly set it, and is taken from the ACPI 6.5 spec section B.4.2, _DOD (display output device enumeration), table B-2: - bit 31 = use the ACPI-defined (vs vendor-defined) bit scheme for bits 15-0 - bit 16 = platform firmware can detect the device - bit 10 = display type is internal/integrated flat panel (aka LCD) TEST=build/boot Win11 on google/brya (osiris), verify ACPI backlight controls functional. Change-Id: Id24e330cfb7c993d12665a704e1ca78e2e38874f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-24mb/google/brya/var/pujjo: Add i2c device for Parade touch screenleo.chou
Add new i2c address 0x24 of touch IC for Parade touch panel. BUG=b:320731709 Test=emerge-nissa coreboot Change-Id: I51bd89beffd912fc147da11d19f38cb44cbe570a Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-01-24*/mem_parts_used.txt: Change Makefile.inc to Makefile.mkMartin Roth
Now that the files are renamed, make sure all references to Makefile.inc are updated as well. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I09e235eecf0c32c80a41bfcbbd3580cce6555e10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-24mb/google/asurada to cyan: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5855f49984db59d786decad6142e3525b146a573 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80105 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-01-22mb/google/brya: Create xol variantYH Lin
Create the xol variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:319506033 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_XOL Change-Id: Id60c50b70c9ab53d62ad48cfc15462f2410f9f02 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80145 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-18mb/google/brya: Drop primus4es boardJakub Czapiga
Primus4es board is no longer supported thus drop it from the tree. TEST=Build all Brya boards in CrOS-SDK - Primus4ES not built. No negative impact observed. Change-Id: I0502b2eed6f80d648b422c8d1622d504a6c93822 Signed-off-by: Jakub Czapiga <czapiga@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-18mb/google/nissa/var/craaskov: Add fan performance controlRex Chou
Add 6w and 15w fan performance control. BUG=b:318454915 TEST=emerge-nissa coreboot chromeos-bootimage Thermal team test pass. Change-Id: If21baa2f6f9bcd527cec2bced27c5fb2cd607830 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79988 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-18mb/google/nissa/var/craaskov: Modify 6W and 15W DPTF parametersRex Chou
1. Modify 6w/15w DPTF parameters based on b:290705146#comment41. 2. 6W MSR power limit_1 power (Watts) increase to 20. 3. 15W MSR power limit_1 power (Watts) increase to 20. BUG=b:290705146 TEST=emerge-nissa coreboot chromeos-bootimage Thermal team test pass. Change-Id: I15fa4b8f7c7088ff56da6493659ae45572913b5a Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-01-17mb/google/nissa/var/craaskov: Modify ELAN touchscreen enable delay from 1ms ↵Rex Chou
to 6ms Modify touchscreen enable_delay to 6ms to meet with spec. eKTH3915N_Product Spec_V1.3_20221028_IPM.pdf BUG=b:318443640 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Id57ab04e61d9e95c962f2c564d3a7e2e7ed6b992 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79978 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2024-01-17mb/google/nissa/var/gothrax: Tune eMMC DLL valuesSimon Yang
Gothrax cannot boot into OS with a kernel loading failure. Update eMMC DLL values to improve initialization reliability How to get these values: - Sending different speed TX/RX command/data signal to eMMC and check the response is successful or not. - Collecting above results from each eMMC model that project used. - Analysing logs to provide a fine tuned DLL values. BUG=b:310701323 TEST=Cold reboot stress test over 2500 cycles Change-Id: Ie36cc9948e3d5dee46385e584baad141a249be79 Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-01-16mb/google/nissa/var/craaskov: Add Micron MT62F1G32D4DR-031 to mem_partsIan Feng
Add new memory Micron MT62F1G32D4DR-031 WT:B. DRAM Part Name ID to assign MT62F1G32D4DR-031 WT:B 2 (0010) BUG=b:319778218 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I9e54958490228beb7039d531c709d56ec244b9e7 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79914 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-12mb/google/nissa/var/anraggar: add FW config to apply the wifi sarJianeng Ceng
1.In contrast to the MediaTek Wi-Fi module, the Intel Wi-Fi module needs to load a SAR table. 2.Describe the FW_CONFIG probe for the settings. - WIFI_6 for MTK Wi-Fi module MT7921L - WIFI_6E for Intel Wi-Fi module AX211NGW BUG=b:315418153 TEST=emerge-nissa coreboot Change-Id: I37e8adc3de02707b2df541cc5e6f88083554eeb4 Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
2024-01-12mb/google/nissa/var/quandiso: Tune P-sensors for Linux 5.15 sx9324Robert Chen
driver Since DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER value on dedede cannot meet DRIVERS_I2C_SX9324 on nissa, need to update the tuning value. Update proximity sensor fine tune value with quandiso EVT machine. BUG=b:314550601 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot and verify p-sensor watch 'cat /sys/bus/iio/devices/iio:device*/*raw' Change-Id: I5fc3bc5876594f2df79d628bd986113d37087c3d Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-11mb/google/nissa/var/craaskov: Enable PIXA touchpadIan Feng
Add PIXA touchpad for variants of craaskov. BUG=b:289962540 TEST=build craaskov firmware and test with PIXA touchpad Change-Id: Iccf19b275548f44aec00be8631590b8a7ad1aa23 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79872 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2024-01-10mb/google/nissa/var/anraggar: Add FW_CONFIG probe for mipi cameraWeimin Wu
Due to some without mipi camera SKUs can't entering S0i3. BUG=b:317670018 TEST=suspend_stress_test -c 1 Change-Id: Ifa8649a603c59946b530abd315113b405ceaf35a Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-10mb/google/byra/var/*: Set WLAN device type back to pciDavid Ruth
This partially reverts commit f493857c9bc1 ("mb/google/brya/var/*: Set dGPU/LAN/WLAN device type to generic"). Setting the WLAN device type to generic broke ACPI SSDT table definition, so set it back to pci. BUG=b:318576073 TEST=build/boot google/nissa (pujjo), verify WLAN ACPI SSDT tables contain the appropriate device entry. Change-Id: If5dad9deb040c8cb0c507e11726f0ba44ccb2909 Signed-off-by: David Ruth <druth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-01-08mb/google/nissa/var/craaskov: Implement touchscreen power sequencingrex_chou
For brya variants with a touchscreen, drive the enable GPIO high starting in romstage while holding in reset, then disable the reset GPIO in ramstage (done in the baseboard). BUG=b:317746281 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I3ca2e2d12a86eaae9e37870a2541c0287e354690 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79764 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-31mb/google/nissa/var/craask: Add ILTK touchscreenRen Kuo
Add touchscreen ILTK for craaskwell. Refer to ILI2901A-A200 Data Sheet_V1.1_20231026. BUG=b:308873706 TEST=build and check touchscreen function on craask Change-Id: I6a68855b1659ff0c9cd33a0ec9acbd289f525a3d Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79735 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
2023-12-28mb/google/nissa/var/anraggar: add hook for WiFi SAR tablecengjianeng
As a preparation for WiFi SAR table addition, adding hook for it. BRANCH=nissa BUG=b:315418153 TEST=emerge-nissa coreboot Cq-Depend: chrome-internal:6790137 Change-Id: Idb200699bb8c8581b9512ec8ec9442f65f8822b3 Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-22mb/google/nissa/var/gothrax: Add probe for Type-C Port C1 (DB)Yunlong Jia
Add probe DB_C_A_LTE/DB_C_A for Type-C Port C1 (daughter board). DB_A is only used for skus without Type-C Port C1. BUG=b:316048649 TEST=emerge-nissa coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: Ifb702c497740953144b43c56653da16fade1053f Reviewed-on: https://review.coreboot.org/c/coreboot/+/79629 Reviewed-by: Kyle Lin <kylelinck@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-21mb/google/{brya,brox,rex}: Update ec_sync wake capabilityMark Hasemeyer
Some of the boards use the EC_SYNC pin to wake the AP but do not advertise the pin as wake capable in the CREC _CRS resource. Relevant boards were determined through empirical testing and inspection of gpio configuration. Update the ACPI tables for rex, brya, and brox based boards to advertise their EC_SYNC pin as wake capable. BUG=b:243700486 TEST=-Dump ACPI and verify ExclusiveAndWake share type is set when EC_SYNC_IRQ_WAKE_CAPABLE is defined -Wake Aviko via keypress and verify chromeos-ec as wake source -Wake Screebo via lid open and verify chromeos-ec as wake source Change-Id: I5828be7c9420cab6ae838272c8301c302a3e078c Signed-off-by: Mark Hasemeyer <markhas@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79374 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-19mb/google/nissa/var/anraggar: Use GPP_D15 to control AVDD and AFVDDWeimin Wu
For EVT SCH: 1. Use GPP_D15 to control AVDD and AFVDD simultaneously for MIPI Camera. 2. Delay reset for 5ms when device power on. BUG=b:312663347 TEST=1. Google Camera app working 2. Passed EA verified Change-Id: I880fb309fcef006090e2849fa6c3a0d472851851 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-17mb/google/nissa/var/anraggar: Disable SDCard controllerWeimin Wu
1. Anraggar doesn't support SDCard, so disable SDCard contorller. 2. Not disabling it will cause can't enter S0ix on first suspend. BUG=b:313585586 TEST=1. check lspci 2. can enter S0ix on first suspend Change-Id: Ie4747d9c5d6ae93d29ef78b629855e0dd320c4db Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-16mb/google/nissa/var/uldren: Reduce boot time for non-touchscreen skuDtrain Hsu
Non-touchscreen sku will set related GPIOs to NC. If touchscreen enabled in overridetree for non-touchscreen sku, the boot time will be 6-7s. Set touchscreen probed to TOUCHSCREEN_UNKNOWN for reduce boot time from 6-7s to under 1s. BUG=b:316434359 BRANCH=firmware-nissa-15217.B TEST=Boot time (cbmem -t) from 6,460,972 to 922,844 Change-Id: I016ce762f726b7624bd060284f74f0992cb129b6 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-12-15mb/google/brya: Enable FSP UPD LpDdrDqDqsReTrainingBora Guvendik
FSP default value for LpDdrDqDqsReTraining is 1. For boards that didn't set LpDdrDqDqsReTraining to any value, 0 was being assigned and it caused black screen issue. BUG=b:302465393 TEST=Boot to OS with debug FSP, check LpDdrDqDqsReTraining = 1 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I301a6e43f2944ffbc63431393378ab8b23450032 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-12-15mb/google: Reduce DA7219 mic detect threshold to 200ohmTerry Cheong
The original DA7219 is designed to use a 500ohm mic detection threshold. Some headset mics (e.g. Logitech H111) have a lower DC impedance that is lower than the threshold and thus cannot be detected. Lower the threshold to 200ohm to match the new default value provided by Renasas as in https://patchwork.kernel.org/project/alsa-devel/patch/20231201042933.26392-1-David.Rau.opensource@dm.renesas.com/ to support such headsets. BUG=b:314062160,b:308207450 Change-Id: I6415e84a4622e0c61bc74b94536fe734048a043f Signed-off-by: Terry Cheong <htcheong@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-15mb/google/brya/var/dochi: Enable LpDdrDqDqsReTrainingMorris Hsu
FSP default value for LpDdrDqDqsReTraining is 1. For boards that didn't set LpDdrDqDqsReTraining to any value, 0 was being assigned and it caused black screen issue. BUG=b:302465393,b:315739133 TEST=Boot to OS with debug FSP, check LpDdrDqDqsReTraining = 1 Change-Id: I5d61301fddac6630bb1c48e992dd76e5cf02a272 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79533 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-12-14mb/google/nissa/var/anraggar: Update DTT settings for thermal controlWeimin Wu
Update DTT settings based on the suggestion of the thermal. BUG=b:313833488 TEST=emerge-nissa coreboot Change-Id: I2296990062cadc05202e3d1ab90af04234bda885 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-14mb/google/nissa/var/anraggar: Enable USB3 Port3 for WWAN (LTE)Weimin Wu
1. Ref to SCH, LTE use USB3 Port3, enable it. 2. Explicitly define the use of USB3 Port1 & USB3 Port2. BUG=b:315061146 TEST=can pass PCIe Hardware Compliance Test Change-Id: I03d6925020012fa740bbd0168a2f5b02ea6763b4 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-14mb/google/nissa/var/anraggar: Change code style for register usb2_portsWeimin Wu
Change code style to be compatible with Nissa's format: register "option" = "{ [0] = value /* comment */ ... }" to register "option[0]" = "value" /* comment */ BUG=none TEST=abuild -v -a -x -c max -p none -t google/brya -b anraggar Change-Id: I60659bd44813173f9b984216473a0919c5f331b8 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-11mb/google/nissa/var/quandiso: Tune P-sensorRobert Chen
Update proximity sensor tuning value from dedede/kracko tuning. Remove GPIO override to use the configuration from nissa baseboard: - GPP_B5 ==> SOC_I2C_SUB_SDA - GPP_B6 ==> SOC_I2C_SUB_SCL BUG=b:310050220 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I7c687677a797415d80be4c420484d3346a8455f6 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79247 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-08mb/google/nissa/var/anraggar: Fix unrecogniz Type-C USB disk on depthchargeWeimin Wu
Due to TCPC0 & TCPC1 exchanged compare to Neried design, but related USB2 Ports not exchanged, keep mainboard C port to conn0. BUG=b:312998945 TEST=can boot from external Type-c USB disk Change-Id: Ib8df4a256bd9cd1b2ca229b09d68f97babc8092e Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-01mb/google/nissa/var/anraggar: Trim GPIO commentsWeimin Wu
Trim all GPIO comments like "origin ==> current". BUG=b:304920262 TEST=pass building Change-Id: I05daa4df16b6da3d3f971b75c7c467032e3f854d Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79321 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-01mb/google/nissa/var/anraggar: Fix the GPP_D6 for LTE power.Weimin Wu
Fix GPP_D6 configuration for LTE power enable. BUG=b:304920262 TEST=mmcli -m any Change-Id: I2996fd35c2897269997bc0290e0ce93bbbaa1bf8 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79166 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
2023-12-01mb/google/nissa/var/anraggar: Fix Type-C & DP functionsWeimin Wu
Due to TCPC0 & TCPC1 exchanged compare to Neried design, but related USB2 Ports not exchanged. BUG=b:304920262 TEST=Tpye-C & DP functions workable Change-Id: I9dacf06b1e672575a684856acdb10b6c88360b18 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79165 Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-01mb/google/nissa/var/anraggar: Enable ILITEK touchscreenWeimin Wu
For proto PCB: GPP_C0 for enable power supply which also for sensor subsystem. GPP_C0 must allways turn power on, so GPP_C6 is not only used for enable function but also for stop report. BUG=b:304920262 TEST=1. touchscreen function workable 2. INT pin no active during suspend Change-Id: I7dabf205dba616f57ef9717f950eba96282d8e3d Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
2023-12-01mb/google/brya/var/dochi: Update overridetree for type c1Morris Hsu
Update overridetree to correct AUX pin to USB-C port 3 BUG=b:299570339 TEST=emerge-brya coreboot chromeos-bootimage Change-Id: I3a5a89c6008fbf28c927f83060e6e508d60845ba Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79343 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-30mb/google/nissa/var/quandiso: Add LTE only daughterboard supportRobert Chen
Quandiso does not use DB_1C, replace the fw_config with LTE only daughterboard. BUG=b:312094048 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Id7129e52d3733f62405f9d766f08563f05016c69 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79297 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Shawn Ku <shawnku@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-30mb/google/nissa/var/anraggar: Add OV13B10 MIPI camera deviceWeimin Wu
Enable MIPI camera for anraggar project. Sensor: OV13B10-GA5A Driver: DW9714V EEPROM: GT24P64E Ref to SCH, use MIPI 4-lane serial output interface. BUG=b:309518095 TEST=Google Camera app working Checking log with: coreboot log: \_SB.PCI0.I2C2.CAM0: Intel MIPI Camera Device I2C address 036h \_SB.PCI0.I2C2.VCM0: Intel MIPI Camera Device I2C address 0ch \_SB.PCI0.I2C2.NVM0: Intel MIPI Camera Device I2C address 050h kernel log: kernel: [ 6.140429] intel-ipu6-isys intel-ipu6-isys0: bind ov13b10 11-0036 nlanes is 4 port is 1 cros_camera_service[4755]: Read camera eeprom from /sys/bus/i2c/devices/i2c-PRP0001:02/eeprom cros_camera_service[4755]: Probing media device '/dev/media0' cros_camera_service[4755]: Probing sensor 'ov13b10 11-0036' (v4l-subdev17) cros_camera_service[4755]: Found V4L2 sensor subdev on /sys/devices/pci0000:00/0000:00:15.2/i2c_designware.2/i2c-11/i2c-OVTIDB10:00/video4linux/v4l-subdev17 Change-Id: I6a82557c94203f24449588a6005abc53cc29ca76 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79163 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arec Kao <arec.kao@intel.corp-partner.google.com>
2023-11-30mb/google/nissa/var/anraggar: Enable CNVi BluetoothWeimin Wu
Intel CNVi WLAN's BT uses USB2 Port 10 inside the SOC, and the relevant configuration needs to be modified in overridtre.cb. BUG=b:304920262 TEST=lsusb ID 8087:0033 Intel Corp. rfkill list hci0:Bluetooth Change-Id: Ibcae800836c17307bc133de5a91658f6dda5985c Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79055 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-30mb/google/nissa/var/anraggar: Tune eMMC DLL valuesSimon Yang
Anraggar cannot boot into OS and kernel loading failure. Update eMMC DLL values to improve initialization reliability - Sending different speed TX/RX command/data signal to eMMC and check the response is success or not. - Collecting every eMMC that use for the project - Based on above result to provide a fine tune DLL values BUG=b:308366637 TEST=Cold reboot stress test over 2500 cycles Change-Id: I9ec3cc23000301aa72aed96e74b63114623c4fc2 Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78851 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-30mb/google/brya/var/marasov: Update MSR Package Power Limit-1 valuesDaniel Peng
As customer demand, it is necessary to set MSR Package Power Limit-1 to 17W for the DTT setting to optimize performance. The PL1 value (17W) suggested by the thermal team which is different from the reference code(PL1=15W). BUG=b:312321601 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Built and booted into OS, and confirm MSR PL1=17W correctly. Change-Id: If7874d26038118c5605cf0721c30e681b45123fe Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79335 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-27mb/google/brya/var/taeko: Generate SPD IDs for 2 new memory partsLeo Chou
Add taeko new supported memory parts in mem_parts_used.txt, generate spd-3.hex for these parts. 1. Samsung K4UBE3D4AB-MGCL 2. Micron MT53E1G32D2NP-046 WT:B BUG=b:312363368 TEST=Use part_id_gen to generate related settings Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I221ad3f490f24b43fe1ccd211014787eab5d1038 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: YH Lin <yueherngl@google.com>
2023-11-27mb/google/nissa/var/craask: Enable PIXA touchpadTyler Wang
Add PIXA touchpad for variants of craask. BUG=b:310489697 TEST=build craask firmware and test with PIXA touchpad Change-Id: I7e68a44eb3d639eaadb5b7b9cb5a6955fd059eeb Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-24mb/google/nissa: make GPP_F17 edge triggered to avoid spamming ECScott Chao
In nissa platform, we configured GPP_F17 as SCI+APIC to wake the system and also generate IRQ to the IOAPIC. Currently, we set GPP_F17 to level triggered and it causes AP (Application Processor) to keep sending GET_NEXT_EVENT to EC during resume from suspend by connecting AC. So we change GPP_F17 to edge triggered to avoid this condition. BUG=b:308716748 TEST=Original failure rate was 7 out of 10 times and it reduced to 0 out of 60 times on six joxer systems. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I3ceb1dfce46376a6a9a8c6cb6d691d818a0a42ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/79244 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-23mb/google/nissa/var/quandiso: Disable un-used C1 port by daughterboardRobert Chen
Probe usb ports by FW_CONFIG setting to disable C1 port on quandiso new daughterboard without C1 port. BUG=b:312094048 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I6f702f60c772176e80b3452bf957d10625564102 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79173 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-22mb/google/nissa/var/craaskov: Add 6W and 15W DPTF parametersVan Chen
The DPTF parameters were defined by the thermal team. Based on thermal table in 290705146#comment17. BUG=b:290705146 BRUNCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I02b4187000eec9990bf10a57875b23007f7bdd12 Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79183 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-21mb/google/nissa/var/joxer: Add speaker ldo configTerry Chen
Follow thermal validation, add ldo output select for speaker. BUG=b:297298847 TEST=emerge-nissa and deploy to DUT to verify audio functionality. Change-Id: Ie68f2b35f024b4dd066d831ae8fd5a662d407753 Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-21mb/google/byra/var/*: Set LAN device type back to pciMatt DeVillier
This partially reverts commit f493857c9bc1 ("mb/google/brya/var/*: Set dGPU/LAN/WLAN device type to generic"). Setting the LAN device type to generic broke programming the LAN MAC address, so set it back to pci. TEST=build/boot google/brya (osiris), verify LAN MAC address programmed correctly. Change-Id: I4fb43b7212e67b5c38724baad572860bc45b558e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79150 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-20mb/goog/brya/var/brya0/skolas: Disable HPS GPIOs if HPS_ABSENTNick Vaccaro
Check FW_CONFIG and disable gpios for HPS if HPS_ABSENT for skolas and brya0 variants. BUG=b:311740746 BRANCH=firmware-brya-14505.B TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas to kernel and verify via "cbmem -c | grep HPS". Change-Id: I8cbe4f40c41f1d06e8f511c3e88c05984566d441 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-20mb/goog/brya/var/brya0/skolas: Disable LTE GPIOs if LTE_ABSENTNick Vaccaro
Check FW_CONFIG and disable gpios for LTE if LTE_ABSENT for skolas and brya0 variants. BUG=b:311459627 BRANCH=firmware-brya-14505.B TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas to kernel and verify LTE gpios are disabled via "cbmem -c | grep LTE". Change-Id: I3f3bc2b536babf71cc484cce02f96f47707f729c Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79122 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-20mb/goog/brya/var/skolas: sync slolas overridetree with brya0Nick Vaccaro
Skolas uses brya0 schematic, so override tree should be almost the same for brya0 and skolas. This change sync's the skolas overridetree.cb with brya0's overridetree.cb. BUG=b:311722825 BRANCH=firmware-brya-14505.B TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas to kernel. Change-Id: I14a2ed803a8ffb8614018af587c66034fb724b38 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-16mb/google/brya/var/osiris: Update power limit values for RPL CPUDavid Wu
Update power limit values based on the suggestion of the thermal team for RPL CPU. The PL1 value (28W) suggested by the thermal team which is different from the reference document 686872 (PL1=15W). BUG=b:310834985 TEST=built and booted into OS. Change-Id: Ia2540ecd1fc453701b9160c97d82ba50b88ee848 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79059 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-13mb/google/nissa/var/gothrax: Add GPIO configurationYunlong Jia
Add variant of LTE and WFC support on gothrax board. We base decisions on the values within the firmware configuration CBI field. In fw_config settings, if the board move LTE and WFC modules, the hardware GPP_A8/GPP_E13/GPP_F12/GPP_H19/GPP_H23/GPP_R6/GPP_R7 pins need to be deasserted. BUG=b:303526071 TEST=emerge-nissa coreboot & \ Check against schematic. Whether it works as expected under different SKUs. Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: Ia8041bdc599509911bde95d6294314036e75b227 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78916 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-09mb/google/nissa/var/gothrax: Add FW_CONFIG probe about DB/WFCYunlong Jia
Add FW_CONFIG probe to separate WFC settings. WFC_PRESENT/WFC_ABSENT Add FW_CONFIG probe for new DB_USB sku. DB_C_A_LTE/DB_A BUG=b:303526071 TEST=emerge-nissa coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I93e0bce4b8be37e259efe0d7b0185035b3e88785 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78963 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-08mb/google/brya/var/anraggar: Initialise overridetreewuweimin
Initialise overridetree based on the schematics revision 20231020A. Added data.vbt just only for running abuild completed. Real vbt define by CONFIG_INTEL_GMA_VBT_FILE in chromium:4936896. BUG=b:304920262 TEST=abuild -v -a -x -c max -p none -t google/brya -b anraggar Change-Id: I232bde990747be80e1ab62c3f0d010d5fc854cb5 Signed-off-by: wuweimin <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78456 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-08mb/google/brya/var/anraggar: Add initial GPIOs configwuweimin
Configure GPIOs according to schematics revision 20231025G. BUG=b:304920262 TEST=abuild -v -a -x -c max -p none -t google/brya -b anraggar Change-Id: I7be6829fc27ee20e014c372d704333ebfd4967b8 Signed-off-by: wuweimin <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-04mb/google/brya/var/marasov: Enable Wi-Fi sar table for Intel moduleDaniel Peng
1.In contrast to the MediaTek Wi-Fi module, the Intel Wi-Fi module needs to load a SAR table. 2.Describe the FW_CONFIG probe for the settings on marasov. - WIFI_SAR_ID_0 for MTK Wi-Fi module MT7921L - WIFI_SAR_ID_1 for Intel Wi-Fi module AX211NGW BUG=b:300045956 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Change-Id: I5b5c6bea6c2c916fb682044218ec7b3a5d2659f6 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77789 Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-03mb/google/nissa/var/craaskov: Disable storage devices based on fw_configRex Chou
Disable devices in variant.c instead of adding probe statements to devicetree because storage devices need to be enabled when fw_config is unprovisioned, and devicetree does not currently support this (it disables all probed devices when fw_config is unprovisioned). BUG=b:305887856 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I5993049ac63520c4dfd057c38b566fc69502d825 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-03mb/google/brya/var/*: Set dGPU/LAN/WLAN device type to genericMatt DeVillier
Change the dGPU/LAN/WiFi device types from PCI to generic, so that the bogus PCI device and function values don't end up in coreboot's internal device tree. The presence of these bogus PCI devices cause the LPI constraint generator to create does a reference for an ACPI device which does not exist (SB.PCI0.RP{xx}.MCHC). The invalid reference(s) cause a Windows BSOD (INTERNAL_POWER_ERROR). TEST=untested Change-Id: Ic997b5ad893853b99ae53a2e5c7acf58467ea4f1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78873 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-02mb/google/brya/var/omnigul: Add fingerprint SPIJamie Chen
Add fingerprint SPI, and power off FPMCU during romstage. BUG=b:305860604, b:306320063 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot, measure evtest can detect and check device probed in kernel log Change-Id: Ic7b9e29ca3cb9352fe098156924fde2719399a79 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-11-01mb/google/brya/var/quandiso: Add VBT data fileRobert Chen
Add data.vbt file for quandiso recovery image. Select INTEL_GMA_HAVE_VBT for quandiso as it has a VBT file now. The VBT file is copied from chromeos internal source and based on yaviks VBT. BUG=b:296506936 TEST=emerge-nissa coreboot Change-Id: Ia9f84b4f56171737a9e7a513b63549b3013775c4 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77588 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Shawn Ku <shawnku@google.com>
2023-11-01mb/google/nissa: Add AUDIO_CONFIG in fw_configRen Kuo
The codec alc5650 has different setting from other amp codec in depthcharge. Since nissa has a single shared depthcharge target, add the fw_config field to allow different audio_configs. (refer to chromium:4983866) BUG=b:307410704 TEST=With depthcharge change, set fw_config and gbb flags on craaskana and check beep sound on firmware screen is workable. Change-Id: I7446fce57557204d91151f1a31755381c1813c6f Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78791 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-31mb/google/brya/var/*: Mark fingerprint reader as hiddenMatt DeVillier
Windows doesn't have / will likely never have a signed driver for the FPR, so set the device status as hidden so it will not appear as an unknown device in Windows Device Manager. Linux does not check/care about the ACPI device status. TEST=build/boot Win11 on google/brya (kano), verify FPR does not show up as unknown device under Device Manager. Change-Id: Ie73fd9d448ecca9e9112abc0d92b4ab46ce3618d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-29mb/google/brya/variants/craask: Enable DDR RFIM Policy for CraaskSumeet Pawnikar
DDR interfaces emit electromagnetic radiation which can couple to the antennas of various radios that are integrated in the system, and cause radio frequency interference (RFI). The DDR Radio Frequency Interference Mitigation (DDR RFIM) feature is primarily aimed at resolving narrowband RFI from DDR4/5 and LPDDR4/5 technologies for the Wi-Fi high and ultra-high bands (~5-7 GHz). This patch sets CnviDdrRfim UPD and enables CNVI DDR RFIM feature for Craask variant. Refer to Intel doc:640438 and doc:690608 for more details. BUG=None BRANCH=None TEST=Build and boot Craask. - Verified that Wifi DDR RFIM Feature is enabled and DDR RFI table can be modified. Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Change-Id: I5560bbedb26e88edd9d35f16b639fe63ef42c30e Reviewed-on: https://review.coreboot.org/c/coreboot/+/78453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-28mb/google/brya/var/dochi: Update overridetree for touchscreenMorris Hsu
Update overridetree for ILI2901 and eKTH7B18U touchscreen. BUG=b:299284564, b:298328847, b:299570339 TEST=emerge-brya coreboot Change-Id: Ib45f3c7c92ea525ca13a6137dd87eeb318f30384 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Bob Moragues <moragues@google.com>
2023-10-27mb/google/nissa/var/joxer: Override tdp pl1 value for DTT tuningMark Hsieh
Follow thermal validation, override tdp pl1 in 6w ADL_N platform to 10w and override tdp pl1 in 15w ADL_N platform to 20w. BUG=b:307365403 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I8dd743e65b9e5fbd6aa2fd9c1b87c7bd487c8174 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78650 Reviewed-by: ChiaLing <chia-ling.hou@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Ivan Chen <yulunchen@google.com>
2023-10-25devicetrees: Remove trailing backslash from multiline valuesFelix Singer
It's not needed to put a backslash at the end of a line for quoted multiline values. Thus, remove it. Change-Id: I1b83d53598ba2adeed853a96d6c2c1a21f01a9f7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78576 Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-10-24mb/google/brya: Set WWAN_PCIE_WAKE_ODL as interrupt on RedrixPaweł Anikiel
This signal gets deasserted by the WWAN modem to reactivate the PCIe link when in low power mode. In order to handle this efficiently, the kernel needs to set up an interrupt. BUG=b:301150499 TEST=Compiled and tested on google/redrix Signed-off-by: Paweł Anikiel <panikiel@google.com> Change-Id: I37f6836aefe4a374eaff3e4bc11358be274cf563 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78416 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-10-23mb/google/brya/variants/anraggar: Generate 13 RAM IDswuweimin
Vendor DRAM Part Name Type MICRON MT62F512M32D2DR-031 WT:B LPD5 HYNIX H9JCNNNBK3MLYR-N6E LPD5 HYNIX H9JCNNNCP3MLYR-N6E LPD5 MICRON MT62F1G32D4DR-031 WT:B LPD5 HYNIX H9JCNNNFA5MLYR-N6E LPD5 MICRON MT62F2G32D8DR-031 WT:B LPD5 SAMSUNG K3KL6L60GM-MGCT LPD5x MICRON MT62F1G32D2DS-026 WT:B LPD5x SAMSUNG K3KL8L80CM-MGCT LPD5x HYNIX H58G56BK7BX068 LPD5x MICRON MT62F2G32D4DS-026 WT:B LPD5x SAMSUNG K3KL9L90CM-MGCT LPD5x HYNIX H58G66BK7BX067 LPD5x BUG=b:304920262 TEST=Run part_id_gen tool without any errors Change-Id: I2968c2f0b9cdd55235f9833a3d3cdb3c83b8601b Signed-off-by: wuweimin <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-23mb/google/brya/var/dochi: Update overridetree for FingerPrintMorris Hsu
Update overridetree to correct FP_MCU fw_config settings. BUG=b:299284564, b:298328847, b:299570339 TEST=emerge-brya coreboot Change-Id: If76dd8fa3567ed01b11a6d2ba796e8c39807816c Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78454 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-23mb/google/brya/var/dochi: Update overridetree for TouchPadMorris Hsu
Update overridetree for TouchPad. BUG=b:299284564, b:298328847, b:299570339 TEST=emerge-brya coreboot Change-Id: I4f88fa8a34b65aaeb64746e7f02e82d9913ce21b Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78455 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-23mb/google/nissa/var/gothrax: Supplement register settings for SX9324 P-sensorYunlong Jia
Set the following register value to make SX9324 work normally "ph0_pin" = "{1, 3, 3}" "ph1_pin" = "{3, 2, 1}" "ph2_pin" = "{3, 3, 1}" "ph3_pin" = "{1, 3, 3}" "ph01_resolution" = "512" "ph23_resolution" = "1024" "startup_sensor" = "1" "ph01_proxraw_strength" = "2" "ph23_proxraw_strength" = "2" "avg_pos_strength" = "256" "cs_idle_sleep" = ""gnd"" "int_comp_resistor" = ""lowest"" "input_precharge_resistor_ohms" = "4000" "input_analog_gain" = "3" BUG=b:295109511 BRANCH=None TEST=emerge-nissa coreboot chromeos-bootimage & Check sar sensor data Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: Ib15f12d754fec8b379afd702b27d0701fac78072 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-10-20mb/google/brya/var/dochi: Enable EC keyboard backlightMorris Hsu
Enable EC keyboard backlight for dochi. BUG=b:299284564 TEST=FW_NAME=dochi emerge-brya coreboot chromeos-bootimage Change-Id: I1b640c576fcdd368110b88cba6f969f10dfc15f1 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 20:46:26 +0000