diff options
| author | Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> | 2023-10-25 18:11:58 +0800 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2023-10-27 17:21:20 +0000 |
| commit | 926be7736115125ec1706befed6e4cde16e98aef (patch) | |
| tree | 23438346cc73593a6d17f94fdd72fc10ba4019c5 /src/mainboard/google/brya/variants | |
| parent | face29cd50890e8f6647a2a7ec3e879989b86952 (diff) | |
mb/google/nissa/var/joxer: Override tdp pl1 value for DTT tuning
Follow thermal validation, override tdp pl1 in 6w ADL_N platform to
10w and override tdp pl1 in 15w ADL_N platform to 20w.
BUG=b:307365403
TEST=USE="project_joxer emerge-nissa coreboot"
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I8dd743e65b9e5fbd6aa2fd9c1b87c7bd487c8174
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78650
Reviewed-by: ChiaLing <chia-ling.hou@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Diffstat (limited to 'src/mainboard/google/brya/variants')
| -rw-r--r-- | src/mainboard/google/brya/variants/joxer/overridetree.cb | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/joxer/overridetree.cb b/src/mainboard/google/brya/variants/joxer/overridetree.cb index 135041d0a7..187afe5d64 100644 --- a/src/mainboard/google/brya/variants/joxer/overridetree.cb +++ b/src/mainboard/google/brya/variants/joxer/overridetree.cb @@ -136,6 +136,25 @@ chip soc/intel/alderlake }, }" + # Power limit config + + register "power_limits_config[ADL_N_081_15W_CORE]" = "{ + .tdp_pl1_override = 20, + .tdp_pl2_override = 35, + .tdp_pl4 = 83, + }" + register "power_limits_config[ADL_N_041_6W_CORE]" = "{ + .tdp_pl1_override = 10, + .tdp_pl2_override = 25, + .tdp_pl4 = 78, + }" + + register "power_limits_config[ADL_N_021_6W_CORE]" = "{ + .tdp_pl1_override = 10, + .tdp_pl2_override = 25, + .tdp_pl4 = 78, + }" + device domain 0 on device ref dtt on chip drivers/intel/dptf |