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path: root/src/mainboard/google/beltino/devicetree.cb
AgeCommit message (Expand)Author
2024-08-26nb/intel/haswell: Move SPD addresses to devicetreeKeith Hui
2024-04-13mb/google/beltino: Set initial fan PWM to 30%Matt DeVillier
2024-04-13superio/ite: Unify it8772f with common codeJoel Linn
2022-12-05superio/ite/it8772f/chip.h: Use 'bool' when appropriateElyes Haouas
2022-11-25cpu/intel/haswell: Move chip_ops to cpu clusterArthur Heymans
2022-11-09nb/intel/haswell: Hook up PCI domain and CPU cluster ops to devicetreeArthur Heymans
2022-01-04sb/intel: Use `bool` for PCIe coalescing optionAngel Pons
2021-01-15cpu/intel/haswell: Factor out ACPI C-state valuesAngel Pons
2020-11-10sb/intel/lynxpoint/sata: Always use AHCI modeAngel Pons
2020-07-28lynxpoint: Factor out PIRQ routing from devicetreeAngel Pons
2020-07-26mb/*/*/devicetree.cb: Normalize disabled PIRQ valuesAngel Pons
2020-07-12haswell: Move some MRC settings to devicetreeAngel Pons
2020-01-07mb/google/{beltino,jecht}: Drop SIO configuration linesNico Huber
2018-08-01mb/google,samsung/*: Add LPC TPM chip driver to devicetreeMatt DeVillier
2016-11-24Add Haswell Chromeboxes/Chromebase using variant board schemeMatt DeVillier
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-17 06:24:24 +0000