diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-11-07 08:04:59 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-11-09 14:30:12 +0000 |
| commit | 600fa266bdc8740126420e63579a5b9d103ca960 (patch) | |
| tree | b824384794084eae2d4ebd7ff774cbc4bfb41999 /src/mainboard/google/beltino/devicetree.cb | |
| parent | 58955be0aab666dc40f7c0f9e31966cc605e2c12 (diff) | |
nb/intel/haswell: Hook up PCI domain and CPU cluster ops to devicetree
Change-Id: I955274bc6bda587201f130762c0735c36f5501d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69289
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/beltino/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/beltino/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index 8eada25326..9704cc34d3 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -14,6 +14,7 @@ chip northbridge/intel/haswell register "usb_xhci_on_resume" = "true" device cpu_cluster 0 on + ops haswell_cpu_bus_ops chip cpu/intel/haswell device lapic 0 on end # Magic APIC ID to locate this chip @@ -22,6 +23,7 @@ chip northbridge/intel/haswell end device domain 0 on + ops haswell_pci_domain_ops subsystemid 0x1ae0 0xc000 inherit device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller |