| Age | Commit message (Expand) | Author |
|---|---|---|
| 2022-11-09 | nb/intel/haswell: Hook up PCI domain and CPU cluster ops to devicetree | Arthur Heymans |
| 2022-01-04 | sb/intel: Use `bool` for PCIe coalescing option | Angel Pons |
| 2021-01-15 | cpu/intel/haswell: Factor out ACPI C-state values | Angel Pons |
| 2020-11-10 | sb/intel/lynxpoint/sata: Always use AHCI mode | Angel Pons |
| 2020-07-28 | lynxpoint: Factor out PIRQ routing from devicetree | Angel Pons |
| 2020-07-26 | mb/*/*/devicetree.cb: Normalize disabled PIRQ values | Angel Pons |
| 2020-07-12 | haswell: Move some MRC settings to devicetree | Angel Pons |
| 2020-01-07 | mb/google/{beltino,jecht}: Drop SIO configuration lines | Nico Huber |
| 2018-08-01 | mb/google,samsung/*: Add LPC TPM chip driver to devicetree | Matt DeVillier |
| 2016-11-24 | Add Haswell Chromeboxes/Chromebase using variant board scheme | Matt DeVillier |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |