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Change-Id: I335494b3339f2e5da7b1b0483b557a6eb211dfc1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18710
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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These definitions do not require AGESA.h include,
and we will eventually remove agesawrapper.h files.
Change-Id: I1b5b78409828aaf2616e177bb54a054960c3869f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18588
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Vendorcode always does PCI MMCONF access once it is
enabled via MSR.
In coreboot proper, we don't give opportunity to make
pci_read/write calls before PCI MMCONF is enabled via MSR.
This happens early in romstage amd_initmmio() for all cores.
Change-Id: If31bc0a67b480bcc1d955632f413f5cdeec51a54
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17533
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I3feed296b6ff9908e783c1221a8f61d9c548fef4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17564
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Do this like fam15tn to reduce code duplication.
Change-Id: I064fd27b85be7fb0c9d6918a84fc6f9b17065534
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17563
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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To store memory configuration in SPI flash currently adds
some 150 ms delay in ramstage, visible in timestamps listing
at 75:cbmem post.
Change-Id: I1160259054b58e9a8df2a105c730e0f4140be1f5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/12215
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.
This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.
Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Instead of reaching into src/include and re-writing code
allow for cleaner code sharing within coreboot and its
utilities. The additional thing needed at this point is
for the utilities to provide a printk() declaration within
a <console/console.h> file. That way code which uses printk()
can than be mapped properly to verbosity of utility parameters.
Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11592
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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As per discussion with lawyers[tm], it's not a good idea to
shorten the license header too much - not for legal reasons
but because there are tools that look for them, and giving
them a standard pattern simplifies things.
However, we got confirmation that we don't have to update
every file ever added to coreboot whenever the FSF gets a
new lease, but can drop the address instead.
util/kconfig is excluded because that's imported code that
we may want to synchronize every now and then.
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} +
$ find * -type f
-a \! -name \*.patch \
-a \! -name \*_shipped \
-a \! -name LICENSE_GPL \
-a \! -name LGPL.txt \
-a \! -name COPYING \
-a \! -name DISCLAIMER \
-exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} +
Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9233
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
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Fix system include paths to be consistent. Chipset support is
part of the Coreboot 'system' and hence 'non-local' (i.e., in
the same directory or context). One possible product of this, is
to perhaps allow future work to do pre-compiled headers (PCH) on
the buildbot for faster build times. However, this currently just
makes mainboard's consistent.
Change-Id: I2f3fd8a3d7864926461c960ca619bff635d7dea5
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8085
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Not part of wrapper to AGESA, but workaround for enable_resources().
Also remove remains of comments in non-fam14 wrappers.
Change-Id: I2526821ca283feb6a506b602b86f817f8b03b341
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7816
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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These are not wrappers for AGESA as they do not enter vendorcode at all.
We expect most of the added fixme.c file to be written without use of AMDLIB.h
and parts relocated as northbridge enable_resources().
Change-Id: Iba6d59e2a7672349208e9a65fcd2cb1094ab7d50
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7815
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Enabling MMCONF PCI-e configuration access should be done before
console_init(). This will likely move further to bootblock one day.
Change-Id: I20c93fe6e79ef7e7981b2f1cd3c6b446feea0f4e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7163
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Change-Id: I5601ed92ca808603b0a9edad118ca54aa168aceb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7604
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
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Change-Id: I5189d0c55635aeb29553fd04a67490cfee3d88d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7153
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
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Change-Id: If6cb99469f56fff8f88b294b625f0a5205ec540b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7238
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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On the ASRock E350M1 a Nuvoton NCT5572D is used as SuperIO-chip. The coreboot
port to this board however used the driver of the Winbond W83627HF SuperIO,
which is compatible enough to get most stuff working, but which clears bit 6 in
register 0x2B. This switches the function of pin 38 of the NCT5572D from
RSTOUT1# output to GP36. The PERST# pin of the ethernet chip and the
unpopulated miniPCIe slot are connected to this pin, so they didn't get reset
during a reboot.
Using the newly added driver for the Nuvoton NCT5572D fixes this problem.
There is also a trace from the pin 37 of the SuperIO, which can be configured
as RSTOUT2#, to pin 82 of the USB3-chip with unknown function.
As with the wrong driver, PS/2 keyboard and mouse do work in SeaBIOS and GRUB
but not in Linux.
Change-Id: I4bc78406afd3b0e10a1b04b561147e0ed94cc494
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/6266
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I14a9dc99acb5d5365a3d7e99a3964120bb611b05
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: http://review.coreboot.org/6308
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Implement logging just once to have uniform output.
Change-Id: I8db694a3bf6b1af459bdf98f7acb99edf4dd07f7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6180
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Push back any board specific values back into romstage.c #defines and
drop any remaining fragments of CONFIG_SIO_PORT in-tree.
Change-Id: Ieb63fb0c2ab1a82b53bafd86686de7b21ac226c3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6045
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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We should configure i8254/i8259 down in to the southbridge rather than
romstage of every AGESA/CIMx board much like Intel boards do.
Change-Id: Id7c4f0baa0819d52aef9b0ee03c20d0fa16b9352
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5669
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Use generic winbond romstage serial init symbols instead of model
specific implementation. We do this on a case by case basis as some
boards are ROMCC and so need to #include .c files. This is a step to
migrate non-romcc boards to a more generic superio framework.
Change-Id: I56f6d9ec77cd21a612cbbdb48634543f34a2e72c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5591
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I24b2cbd671ac3a463562d284f06258140a019a37
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4683
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This change allows Kconfig options ROM_SIZE and CBFS_SIZE to be
set with values that are not power of 2. The region programmed
as WB cacheable will include all of ROM_SIZE.
Side-effects to consider:
Memory region below flash may be tagged WRPROT cacheable. As an
example, with ROM_SIZE of 12 MB, CACHE_ROM_SIZE would be 16 MB.
Since this can overlap CAR, we add an explicit test and fail
on compile should this happen. To work around this problem, one
needs to use CACHE_ROM_SIZE_OVERRIDE in the mainboard Kconfig and
define a smaller region for WB cache.
With this change flash regions outside CBFS are also tagged WRPROT
cacheable. This covers IFD and ME and sections ChromeOS may use.
Change-Id: I5e577900ff7e91606bef6d80033caaed721ce4bf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4625
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
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ROMCC boards were left unmodified.
Change-Id: I3d842196b3f5b6999b6891b914036e9ffcc3cef0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3853
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Since this parameter is not used anymore, drop it from
all calls to copy_and_run()
Change-Id: Ifba25aff4b448c1511e26313fe35007335aa7f7a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3213
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Due to
$ more src/southbridge/amd/cimx/sb800/Makefile.inc
[…]
romstage-y += cfg.c
romstage-y += early.c
romstage-y += smbus.c
ramstage-y += cfg.c
ramstage-y += late.c
[…]
`src/southbridge/amd/cimx/sb800/` is passed with the switch `-I` to
the compiler, where it is also going to find the header file
`sb_cimx.h`. Therefore use `#include <sb_cimx>` everywhere, which is
what some AMD SB800 based boards already do.
The only effect is, that the compiler will not needlessly look into
directories which do not contain the header file [1].
The following command was used for the replacement.
$ git grep -l sb_cimx.h src/mainboard/ | xargs sed -i 's/#include "sb_cimx.h"/#include <sb_cimx.h>/'
[1] http://gcc.gnu.org/onlinedocs/cpp/Search-Path.html
Change-Id: I96ab34bac1524e6c38c85dfe9d99cb6ef55e6d7c
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3118
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Here's the great news: From now on you don't have to worry about
hitting the right io.h include anymore. Just forget about romcc_io.h
and use io.h instead. This cleanup has a number of advantages, like
you don't have to guard device/ includes for SMM and pre RAM
anymore. This allows to get rid of a number of ifdefs and will
generally make the code more readable and understandable.
Potentially in the future some of the code in the io.h __PRE_RAM__
path should move to device.h or other device/ includes instead,
but that's another incremental change.
Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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In the file `COPYING` in the coreboot repository and upstream [1]
just one space is used.
The following command was used to convert all files.
$ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/'
[1] http://www.gnu.org/licenses/gpl-2.0.txt
Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2490
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
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[…]
CC romstage.inc
src/mainboard/asrock/e350m1/romstage.c: In function 'cache_as_ram_main':
src/mainboard/asrock/e350m1/romstage.c:48:5: warning: unused variable 'reg8' [-Wunused-variable]
This change was already done for AMD Persimmon in the following
commit.
commit d7a696d0f229abccc95ff411f28d91b9b796ab74
Author: efdesign98 <efdesign98@gmail.com>
Date: Thu Sep 15 15:24:26 2011 -0600
Persimmon updates for AMD F14 rev C0
Change-Id: I8f1ae1a609b87b197583934f0556f66b64e6994d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2230
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
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There is no reason for this to be a top level directory.
Some stuff from lib/ should also be moved to drivers/
Change-Id: I3c2d2e127f7215eadead029cfc7442c22b26814a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/939
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This cleans up the strings in romstage.c, removing the ugly "got past".
Also, cleaned up comments and some spacing.
Change-Id: I0124df76eb442f8a0009a31a8632e4fd67ed7782
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/539
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This change adds the southbridge related code to support
the update of the AMD Family14 cpus to the rec C0 level.
Some of the changes reside in mainboard folders but they
reference changed files in the southbridge folder so they
are included herein.
Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/135
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Move the AMD SB800 early clock setup code that is needed for early
serial port operation from mainboard/romstage.c to sb800/bootblock.c.
This prevents code duplication and simplifies porting.
Change-Id: I615cfec96c9f202d9c154dc6674ec7cbcf4090c3
Signed-off-by: Scott Duplichan <scott@notabs.org>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/96
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
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Committing Scott's e350m1 changes (svn r6585):
Move SB800 clock init earlier,
Fixes problem where initial serial port output is garbled.
Change-Id: If05aa37726b962e8994ee69bf1882fcfae56aa19
Signed-off-by: Scott Duplichan <scott@notabs.org>
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Reviewed-on: http://review.coreboot.org/32
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
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So we don't waste time on the first cbfs scan.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
[adapt persimmon with the same change, and work around romcc bug
in bootblock code: it doesn't like MEMACCESS[idx] |= value;]
Change-Id: Ic4d0e53d3102be0de0bd18b1b8b29c500bd6d997
Reviewed-on: http://review.coreboot.org/9
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marcj303@gmail.com>
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Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: If840164fa0e2b6349ba920edf06386ba1fe08aab
Reviewed-on: http://review.coreboot.org/8
Tested-by: build bot (Jenkins)
Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
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Enable rom cache early to reduce boot time.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6633 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Enable SPI cacheline prefetch early to reduce boot time.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6627 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Switch processor cores to pstate 0 early to reduce boot time.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Enable 33 MHz fast mode SPI read early to reduce boot time.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6625 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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initialization functions.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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A video option rom must be added for UMA graphics support. It can
be extracted from the supplied UEFI BIOS.
ASRock E350M1 support is based on the AMD persimmon project. The
major differences are SIO model and DIMM SDP addressing. With this
coreboot and seabios, the board can boot DOS from a SATA drive and
can boot WinPE from a USB flash drive. I was unable to get
Windows setup to run.
The board has a socketed SPI flash BIOS chip and a serial port
header. The SIO is Nuvoton NCT5572D. Using coreboot's existing
Winbond w83627hf is a good enough match to get the serial port
and keyboard working.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6382 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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