diff options
| author | Marshall Buschman <mbuschman@lucidmachines.com> | 2011-06-04 15:47:05 +0000 |
|---|---|---|
| committer | Peter Stuge <peter@stuge.se> | 2011-06-04 15:47:05 +0000 |
| commit | 314f4a2077b78fbbab3bfe60308e82b875ddcc07 (patch) | |
| tree | 9e9047fbd6068d7cdcd9b6db0b3f0dc182368683 /src/mainboard/asrock/e350m1/romstage.c | |
| parent | 1a7699f42a1f485d912dcf99b5b5ef1d1c39393e (diff) | |
Port persimmon r6591 to e350m1: ROM cache early
Enable rom cache early to reduce boot time.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6633 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/asrock/e350m1/romstage.c')
| -rw-r--r-- | src/mainboard/asrock/e350m1/romstage.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 41f9a6b86a..4b45caf6e9 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -47,6 +47,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; u8 reg8; + // all cores: allow caching of flash chip code and data + // (there are no cache-as-ram reliability concerns with family 14h) + __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); + __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); + // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time __writemsr (0xc0010062, 0); |