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2022-12-06mb/amd/mayan/gpio: Configure mayan GPIOsFred Reitberger
Configure mayan GPIOs per schematic 105-D59700-00A Rev 1.00 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I283afc716487fd8fa6d455194c382d87a3e6860b Reviewed-on: https://review.coreboot.org/c/coreboot/+/70207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-05mb/amd/mayan: Improve naming of EC FWFred Reitberger
Change the EC FW CBFS filename prefix to a more accurate "ec/" Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ic789df11160e3ffe7b7294b11e1fa80e3c3961ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/70206 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-01mb/amd/chausie: change AMD_FWM_POSITION_INDEX for non-chromeos caseFelix Held
Commit 2c102232e8f7 ("mb/amd/chausie,google/skyrim: increase RW_MRC_CACHE size to 120 kByte") increased the MRC cache size, but with the change the default AMD_FWM_POSITION_INDEX which is 5 for the 16MByte flash size, the amdfw part won't be placed on the expected position, since the cbfs header is in that exact location and cbfstool places the amdfw part right after that. Change the AMD_FWM_POSITION_INDEX to 4 for the non-chromeos builds to work around this. TEST=Non-chromeos chausie build now boots and doesn't fail any more before releasing the x86 cores from reset Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I89fe1d0672139e04070f05c6c8fa8955edcfc7ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/70133 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-30mb/amd/birman/gpio: Configure birman GPIOsFred Reitberger
Configure birman GPIOs per schematic 105-D67000-00B v0.7 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I5459efb38431e568e25405c440b5b9cf1354f02f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-27mb/amd/mayan: Add framework for morgana crb mayanRitul Guru
mayan is the reference board for the morgana SoC. It needs to be updated to match the actual board design as well. amd/mayan is started as a copy of amd/birman. Change-Id: Id6801e6c6e706ae3878ce9e2c3d6452964235148 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70010 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-15soc/amd: commonize generation of the PIC/APIC mapping tablesFelix Held
Now that we have a common init_tables in all mainboards using AMD SoCs, both the population of the fch_pic_routing and fch_apic_routing arrays and the definition of those arrays can be moved to the common AMD SoC code to not have the code duplicated in all mainboards. BUG=b:182782749 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: I8c65eca258272f0ef7dec3ece6236f5d00954c66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68853 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-15mb/amd/gardenia,pademelon: rewrite IRQ mapping handlingFelix Held
Gardenia and Pademelon had the same mainboard_picr_data and mainboard_intr_data data arrays. Compared to Kahlee there were 4 differences for PIRQ_F, PIRQ_SCI, PIRQ_SD and PIRQ_SATA in the IRQ data arrays. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia460b467990be7c3e6261440505988a9770ea084 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68852 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10mb/amd/chausie/ec.c: Enable WLANFred Reitberger
Enable WLAN power and deassert the various radio disables. TEST=boot chausie Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I2d21905001fa776c0d5c864d83dcd697e3febe0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/69319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-11-10mb/amd/chausie: Correct naming of EC FWFred Reitberger
Change the EC FW CBFS filename prefix to a more accurate "ec/" TEST=build and boot chausie Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ib9ee24ca06b29c74cc0a91f9e4789df00ba1ba53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-11-09soc/amd/picasso/acpi: include pci_int_defs.asl from soc.aslFelix Held
Instead of including pci_int_defs.asl in each board's DSDT, include it in the common soc.asl. This moves the PRQM OperationRegion and the PRQI IndexField defined in pci_int_defs.asl into the \_SB scope, but those are defined inside the \_SB scope both in the Picasso reference code and for the AMD SoCs from Cezanne on. TEST=Both Linux and Windows still boot and don't show ACPI errors on Mandolin after moving this inside the \_SB scope Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib4e7bfb15de184cc43cd17c8249be0f59405793f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2022-11-09soc/amd/picasso/acpi: rename pcie.asl to pci_int_defs.aslFelix Held
This aligns Picasso more with the newer AMD SoCs and also makes it a bit clearer what this file does. Also remove the unneeded tabs at the beginning of each line. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie6e5ee815e4346004bc864a6111a255dc689eae8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2022-11-07mb/*/*: Remove AMD agesa family16 boardsArthur Heymans
These boards use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: I43c7075fb6418a86c57c863edccbcb750f8ed402 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07mb/*/*: Remove AMD family14 boardsArthur Heymans
These boards use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: I3495d140a244bbbf63e846fcd963d69907e09719 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07mb/*/*: Remove AMD FAMILY15TN boardsArthur Heymans
These boards use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: I9efb5cb1149cc4cf6337c47af8a2f4c4b55f4368 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-29mainboard/amd/chausie: Don't use APCB_FT6_UpdatableNikolai Vyssotski
This APCB binary is not used for coreboot builds. Coreboot does not support RW APCB. Change-Id: I4d317ae31cf226b5481619f1539abb6237033f7c Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-10-29mb/amd/birman: Update Birman to work with Morgana or GlindaMartin Roth
Birman should work with either Morgana or Glinda SoCs, so configure the mainboard to allow building with either. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I56206cd9ad5db99c00b734430b250e04ea9e0609 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-10-26mb/amd/bilby,birman,chausie,majolica: rework FCH IRQ mapping generationFelix Held
This ports the changes to the way the fch_pic_routing and fch_apic_routing arrays get populated from Mandolin to Bilby, Birman, Chausie and Majolica. This is a preparation to move the init_tables implementation to the common AMD SoC code in a later patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia957056b60dafbc52a9809a4563a348ad7443376 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26mb/amd/mandolin: handle invalid intr_index values in init_tablesFelix Held
Make sure that the intr_index is valid to avoid out-of-bounds writes to the fch_pic_routing and fch_apic_routing arrays. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I45ab115f3814b212243c4f6cf706daf77b6ff3b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26mb/amd/mandolin: introduce mb_get_fch_irq_mappingFelix Held
Introduce mb_get_fch_irq_mapping to access the FCH IRQ routing mapping information and use it in init_tables to get the mapping instead of directly accessing the array's contents. This is a preparation to move the init_tables implementation to the common AMD SoC code in a later patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9c39ea9de5ebbf70d2c5a87bfdfe270796548c5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26mb/amd,google: unify fch_irq_routing struct instance nameFelix Held
Use the same fch_irq_map name in all mainboards using the Picasso, Cezanne, Mendocino and Morgana instead of using a mainboard-specific name. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I035cffb9c6c8afd6bd115831e8eed4a395e2a7fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/68846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26mb/amd/bilby,mandolin: add missing string.h includeFelix Held
string.h defines the memset function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I242a0382e7020681b6c3a25f75a2a91cbccbe815 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26soc/amd/mendocino: Enable GPP clk req disabling for disabled devicesRobert Zieba
Enable GPP clk req disabling for disabled PCIe devices. If a clk req line is enabled for a PCIe device that is not actually present and enabled then the L1SS could get confused and cause issues with suspending the SoC. BUG=b:250009974 TEST=Ran on skyrim proto device, verified that clk reqs are set appropriately Change-Id: I6c840f2fa3f9358f58c0386134d23511ff880248 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68139 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-26soc/amd/common/include: introduce and use FCH_IRQ_ROUTING_ENTRIESFelix Held
Instead of using magic constants for the fch_pic_routing and fch_apic_routing array sizes, define FCH_IRQ_ROUTING_ENTRIES in the common code headers and use this definition. This also allows to drop the static assert for the array sizes. In the Stoneyridge mainboard code the equivalent arrays are named mainboard_picr_data and mainboard_intr_data; also use FCH_IRQ_ROUTING_ENTRIES as fixed array size there. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2d7ee46bd013ce413189398a144e46ceac0c2a10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68818 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26mb/amd,google: move fch_irq_routing struct definition to soc/amdFelix Held
Define the fch_irq_routing struct once in a common header file instead of in every mainboard's code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I11d9000b6ed7529e4afd7f6e8a7332c390da6dab Reviewed-on: https://review.coreboot.org/c/coreboot/+/68817 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21mb/google/skyrim/port_descriptors: update DDI for MDN and ChausieJason Nien
Add two new types for MDN DDI descriptor BUG=b:228284940 TEST=Normal boot and S0i3 cycles Signed-off-by: Jason Nien <finaljason@gmail.com> Change-Id: I02793f032f9855dac202a5aca8666c26426d6cb2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66847 Reviewed-by: Bao Zheng <fishbaozi@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-10-15mb/amd/padmelon: rename to pademelonFelix Held
This AMD reference board is called Pademelon and not Padmelon, so fix the name in coreboot. Also update the corresponding documentation. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id1c7331f5f3c34dc7ec4bc5a1f5fe3d12d503474 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-14mb/amd/padmelon/bootblock/OemCustomize: add TODO for Prairie FalconFelix Held
The PCIe port descriptor list seems to be specific to Merlin Falcon and Prairie Falcon has a different PCIe root port configuration. Since I neither have the board nor the different APUs, I just add a comment about this instead of trying to come up with a PCIe port descriptor list that may or may not work properly on Prairie Falcon APUs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8e1eb67a8f684297bbefc6e2593250d7bd45593f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-14mb/amd/padmelon/devicetree: use device aliasesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I509daac75c80bdca808706f783b04843209cc313 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68380 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14mb/amd/gardenia/devicetree: disable unused gpp_bridge_2Felix Held
The board's PCIe port descriptors have the PCIe engine disabled, so update the devicetree accordingly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic97a54c3cc762a36752d6b9f21467428912a9edd Reviewed-on: https://review.coreboot.org/c/coreboot/+/68379 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14mb/amd/gardenia/devicetree: use device aliasesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9a429c0fd23eb3b52a19a974b22079d675e3506a Reviewed-on: https://review.coreboot.org/c/coreboot/+/68318 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-13mb/amd,google/*/devicetree: drop CPU cluster device for StoneyridgeFelix Held
Since commit 60e9114c6210 ("include/device: ensure valid link/bus is passed to mp_cpu_bus_init"), no dummy LAPIC device is required under the CPU cluster device. Since the CPU cluster device is already present in the Stoneyridge chipset devicetree, drop the whole CPU cluster part from the mainboard's devicetrees. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8918c14be25ac9756926a9c6a2806a3dceced42a Reviewed-on: https://review.coreboot.org/c/coreboot/+/68317 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-13mb/amd/padmelon: enable PCI device 3.1 for MerlinfalconFelix Held
When using a Merlin Falcon APU, explicitly enable the PCIe root port at B0D3F1. B0D3F0 is only a dummy PCI device function, but needs to also be enabled in order for the actually used function to be usable. Prairie Falcon doesn't have and PCI device 3 on bus 0, so remove D3F0 from the common mainboard devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I01f9b9ac2a9ebd5899a093d97eb5b2d76d309f66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68315 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-13mb/amd/padmelon/devicetree: fix PCIe port device numbersFelix Held
Enable the correct PCIe root ports in the devicetree so that the configuration matches the PCIe port descriptors in src/mainboard/amd/padmelon/bootblock/OemCustomize.c. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idb00a65adcf2059d7432a8df08654bb0ba965e24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68314 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-13mb/amd/gardenia,padmelon/devicetree: explicitly enable IOMMU deviceFelix Held
PCI devices that aren't present in the devicetree will be treated as enabled. Since the chipset devicetree that will be added in a follow-up patch disables this device by default, explicitly enable the IOMMU device on the Stoneyridge mainboards that don't disable it to keep the same behavior. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4a2cdd00abe8309244829dc633dd8a9ca0038dfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/68313 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-13mb/amd/padmelon: use override devicetrees for the different APUsFelix Held
Since the devicetree files are passed to util/sconfig without being processed by the C preprocessor, using #if in the devicetree won't give the behavior that might be expected. Instead sconfig treats the #if as a comment, but still processes all other lines. To get the intended behavior, replace the C preprocessor usage in the devicetree by moving the APU-specific parts to override devicetrees that get selected according to the selected APU type. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iddd317b27a838849fa40c0fb77d942609104cf04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68312 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-10mb/amd/birman: Add framework for morgana crb birmanMartin Roth
birman is the reference board for the morgana SoC. It needs to be updated to match the actual board design as well. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I4b16854c954949217a76c3d4f04ddc4001f64337 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68196 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14mb/amd/gardenia: deselect HAVE_PIRQ_TABLE and drop incorrect irq_tablesFelix Held
This file isn't correct, since the Stoneyridge SoC doesn't have a legacy PCI bridge on bus 0 bridge 0x14 function 4. Google/Kahlee doesn't select HAVE_PIRQ_TABLE, so it's likely safe to also not select it for this board. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibaf470b9ff7823019772d43af98ebc47af395728 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-09-12mb/amd/*/irq_tables.c: Reformat codeElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: If6cdf02c56778da67b56afbb71f9f01107f23d2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/67519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-12mb/amd/*/irq_tables.cmb/*/*/irq_tables.c: Use ALIGN_UP macroElyes Haouas
Change-Id: I2bd5e09f51918fe4c7e954edf54ab4d9bc629fd1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-08mb/amd/chausie/ec.c: Clean up definesFred Reitberger
Use the BIT() macro instead of reinventing the wheel. TEST=timeless builds are identical Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I873013feebd30c86290dda692c7b137d5f3c4729 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-31mb/amd/chausie/Kconfig: Re-enable ESPI_RETAIN_PORT80Fred Reitberger
Chausie fails to boot without this option set. Enable in the mainboard rather than the SoC Kconfig to not impact Skyrim. TEST=boot to OS Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I9f2a1be9eddb9e17407d00ff50ceb70a2718ce3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/67175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-16mb/**/dsdt.asl: Drop superfluous commentsAngel Pons
These comments don't add much value, so remove them. Change-Id: I7e9692e3fe82345cb7ddcb11c32841c69768cd36 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66713 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2022-08-13src/mb: Update unlicensable files with the CC-PDDC SPDX IDMartin Roth
These files contain no creative content, and therefore have no copyright. This effectively means that they are in the public domain. This commit updates the unlicensable empty (and effectively empty) files with the CC-PDDX identifier for license compliance scanning. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I0b76921a32e482b6aed154dddaba368f29ac2207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66497 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-11treewide: Rename Sabrina to MendocinoJon Murphy
'Mendocino' was an embargoed name and could previously not be used in references to Skyrim. coreboot has references to sabrina both in directory structure and in files. This will make life difficult for people looking for Mendocino support in the long term. The code name should be replaced with "mendocino". BUG=b:239072117 TEST=Builds Cq-Depend: chromium:3764023 Cq-Depend: chromium:3763392 Cq-Depend: chrome-internal:4876777 Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I2d0f76fde07a209a79f7e1596cc8064e53f06ada Reviewed-on: https://review.coreboot.org/c/coreboot/+/65861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-08-07mb/amd/chausie: Add Kconfig prompts to EC stringsMarshall Dawson
Make the default Microchip EC firmware path/to/file values overridable by adding prompts to the strings. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I300f78a11960dbe193165fcb379b7190e3de4545 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-18treewide: Don't add bitsElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Id56310bd616cd19fee5dc934676006b2dc34b1ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/65929 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-18mb/amd/*/BiosCallOuts.c: Fix some white spaces issuesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I37ed13e1fa318ca0f8381f5b1b409bf80fa4da11 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17mb/amd/*/irq_tables.c: Fix some white spaces issuesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ifc915e2825724fdaac67d259e1af2079893492a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17mb/amd/persimmon/mainboard.c: Fix some white spaces issuesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I490a7f0c9cb32ca1ea246c14b72852814553214f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-04mb/amd/bilby: Add PSP NVRAM and RPMC NVRAM region to flash mapRitul Guru
Create PSP NVRAM and RPMC NVRAM region with size 128K & 64K respectively, which are supported region by the PSP. moved CBFS up due to build error, CBFS need not to be at the end the flash for amd Zen cpu. Change-Id: Ide778c61a755697c1bef1eaa87f2976d8ff12eb6 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-06-14mb/amd/chausie/Kconfig: enable PCIe power managementFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia24a502994d24f3341273c5e6f768687ad20baf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65113 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-14mb/amd/chausie/devicetree: add PCIe clock output configurationFelix Held
The general purpose PCIe clock outputs 0, 1 and 3 are used with their corresponding clock request pins, so set the gpp_clk_config to GPP_CLK_REQ for those and disable the unused output 2. This matches the DXIO descriptor in port_descriptors.c. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I38ab8d6d824617509fdd18f06d5593889ec50666 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65112 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-12mb/amd/chausie,google/skyrim: increase RW_MRC_CACHE size to 120 kByteFelix Held
The APOB data in DRAM is larger than the 96 kBytes of RW_MRC_CACHE, so it won't fit in the flash and makes soc_update_apob_cache return early before writing the APOB data from DRAM into the flash with this warning: [WARN ] RAM APOB data is too large 1db18 > 18000 Increasing the RW_MRC_CACHE size to 120 kByte fixes this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I763d20f504d4f5b7cea68f21f409de9a1035f440 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64555 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-10mb/chausie/ec: Set MS bit in SW02Fred Reitberger
Set the MS bit in EC SW02 register to enable s0i3 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I97b6adf48b49635251c70015f1d87fd8ca11d539 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-05-28vendorcode/amd/agesa/f15tn: Fix all improper use of .dataArthur Heymans
AGESA has a lot of code in the .data section which is for initialized data, that in fact should be .rodata. This adds the 'CONST' keyword everywhere it is needed. TEST: See in the .elf file (e.g. using readelf) that there is nothing in .data section. Change-Id: I9593c24f764319f66a64715d91175f64edf10608 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2022-05-24mb/amd/chausie,majolica: don't select HAVE_ACPI_RESUMEFelix Held
The Chausie and Majolica boards use S0ix which is mutually exclusive with S3, so don't select HAVE_ACPI_RESUME. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1d1bf33ad017dfbf908e0a195949998668c8e137 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64605 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16mb/amd/chausie/devicetree: add USB PHY configurationFelix Held
Specify the USB PHY settings in the devicetree instead of relying on the FSP defaults. The USB PHY configuration for Chausie are taken from the internal UEFI code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8cc38e6e26d53802773fe3c405415de15cca98a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-16mainboard/amd/padmelon: Use pci_or_config32()Elyes Haouas
Change-Id: I8d55fc93f6ec413d0cbcea2f8e0a90a76f1803cd Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-12soc/amd/*/Makefile.inc: Do some cosmeticsArthur Heymans
The first target for the add_intermediate targets is always $(obj)/coreboot.pre. Change-Id: Iea2322ca1abd43900f3631b7965f07fed4235ca0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-11mb/*/bootblock.c: Fix set but unused variable over inb loopArthur Heymans
Change-Id: Iba80c4a5960c6fb59f542b33e8e769576ccfed59 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2022-04-27mb/amd/chausie: Auto-detect DDI typeFred Reitberger
Read the EEPROM to detect the DDI type. BUG=b:225139014 TEST=Boot chausie and correctly detect display card type Change-Id: I3ddd8789e75d5da2ea1e6ce9a81e5ebb2cf3c007 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-27mb/amd/chausie: Add EC supportFred Reitberger
Add support for the chausie EC. Use EC to configure default board GPIO settings. Change-Id: I3e59e17644cddf1a508614f90c20561bde2691fb Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-27md/amd/chausie: call espi_switch_to_spi1_padsFred Reitberger
Chausie uses the spi1 pads for eSPI Change-Id: Iee9b92dd9b4e84764568ec3cc8d1fce731e0d1a7 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63866 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-07ChromeOS: Add DECLARE_x_CROS_GPIOS()Kyösti Mälkki
Change-Id: I88406fa1b54312616e6717af3d924436dc4ff1a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-06ChromeOS: Promote variant_cros_gpio()Kyösti Mälkki
The only purpose of mainboard_chromeos_acpi_generate() was to pass cros_gpio array for ACPI \\OIPG package generation. Promote variant_cros_gpio() from baseboards to ChromeOS declaration. Change-Id: I5c2ac1dcea35f1f00dea401528404bc6ca0ab53c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-01mb/amd/majolica/port_descriptors: clean up variable namesFred Reitberger
Removing unnecessary "czn" in variable name. Majolica is always a cezanne. TEST=Timeless build Change-Id: I490111ecea84c934585d0bbd623486fba76eb7f1 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63261 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-01mb/amd/chausie/port_descriptors: clean up variable namesFred Reitberger
Remove "czn" from the variable names since chausie does not use cezanne. TEST=Timeless build Change-Id: I8cc854f4c60707c7fec5cd7fef1c4550883cd45a Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-30mb/amd/chausie/port_descriptors: update DDI descriptorsFelix Held
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I31db6c138a21dc22e7aa473f2215ca2c7594326c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63163 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30mb/amd/chausie/devicetree: update PCI root portsFelix Held
Only enable the PCIe root ports that have corresponding DXIO descriptors and also update the comments to have them match the actual hardware configuration. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I378c620abb6e52de680669b6edd228874153e399 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63162 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30mb/amd/chausie/port_descriptors: update DXIO descriptorsFelix Held
Change the DXIO descriptors to match the default PCIe lane mapping on the chausie board. With this configuration and a board-level rework to bypass the EC control of the NVMe SSD power supply rail, this configuration results in the SSD being detected on the root port on bus 0 device 2 function 3 and usable as boot device. This was also validated against the schematics revision B. Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib74988b741f748d240ef09fa0dba8885bdc5e706 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63161 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-25mb/*/BiosCallOuts.c: Fix unused variableArthur Heymans
This fixes clang builds. Change-Id: Ie09fae149a9530ad45f0cd5945e73f46484ef385 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-03-23soc/amd/cezanne: Turn off gpp clock request for disabled devicesRobert Zieba
The current behavior does not actually check if a device is present before enabling the corresponding gpp_clkx_clock_request_mapping bits which may cause issues with L1SS. This change sets the corresponding gpp_clkx_clock_request_mapping to off if the corresponding device is disabled. BUG=b:202252869 TEST=Checked that value of GPP_CLK_CNTRL matched the expected value when devices are enabled/disabled, checked that physically removing a device that is marked as enabled also disables the corresponding clk req BRANCH=guybrush Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61259 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-21mb/amd/chausie: add APCB binaries if availableFelix Held
The APCB files that provide the firmware components running on the PSP some mainboard-specific information like the DRAM interface configuration. Those files aren't yet in the upstream 3rdparty/blobs repository, so only add those files if they are present and print that no APCB was added and the image won't boot if they aren't present. TEST=Both cases behave as expected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1e8621901741b8b0531fe134273b47e85911e19f Reviewed-on: https://review.coreboot.org/c/coreboot/+/62925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-03-21mb/amd/chausie/chromeos.fmd: increase A/B RW section size to 4MBNikolai Vyssotski
To have enough space in the A/B RW sections, increase those sizes to 4 MByte and decrease the RO section size to 6 MByte to free up the space needed for that. Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib107fd05cfb0ef7de95425abcce6c82b88a9835d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-03-19mb/amd/chausie/devicetree: set PSPP policy to DXIO_PSPP_DISABLEDFelix Held
Right now, the PSPP policy that controls if the PCIe lanes can be dynamically downgraded to a lower speed to save some power needs to be disabled in order for the link training to be successful. Once this feature is working, the PSPP policy will be switched to balanced again. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I85a06f322c4ddff25c3a858e2b79c84b36c48932 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-14mb/amd/chausie/devicetree: enable GFX HDA, ACP and XHCI2 devicesFelix Held
GFX HDA is the audio controller that provides audio output via the external display connection, ACP is the audio coporcessor for the on- board audio codec and XHCI2 is the third XHCI controller that provides one USB 2.0 port. All those devices are used, so enable them in the board's devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I186797a832470eb17752e06aa2fcc0b5c9db0398 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62571 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-03soc/amd/stoneyridge/acpi: rename cpu.asl to pnot.aslFelix Held
After the patch that moved the generation of the PPKG object to Stoneyridge's acpi.c, only the PNOT object remained in its cpu.asl, so rename it to pnot.asl. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0deb2d75cae98b8fcd31297d7fac5f27525efe65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-03soc/amd/picasso/acpi: rename cpu.asl to pnot.aslFelix Held
After the patch that moved the generation of the PPKG object to Picasso's acpi.c, only the PNOT object remained in its cpu.asl, so rename it to pnot.asl. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic77dacb146aa823fc99f779f465fff28b2aead68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-01mb/amd/chausie: Always enable developer modeRaul E Rangel
Chausie doesn't have recovery mode buttons so it's impossible to manually enter recovery mode to enable developer mode. This means we need to force developer mode. BUG=none TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id0b08ee8e009e8603f63e691b5a7a2ac04e1fc3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-28mb/amd/chausie/Kconfig: Add EC FW to RO_REGION_ONLYFred Reitberger
Include chausie EC and EFS only in the RO region when building with vboot. Without this, the EC is also added to the FW_MAIN_A and FW_MAIN_B regions. Change-Id: I78de8bd639232b9fb6d775b77ecd892f28514614 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-25mb/amd/chausie/devicetree: add i2c_scl_resetFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I23ec6bcb6a2b3627866165972fd6ba1c75367533 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62188 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25mb/amd/chausie/devicetree: enable I2C controllersFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I97f37c45ffe945e6bb071c8205343943edc524ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/61871 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-21mb/amd/chausie/chromeos.fmd: resize EC size in FMAP to 4kByteFelix Held
Only the info about the location of the EC firmware will be stored right at the beginning of the flash, so the size can be reduced to 4kByte which is the erase block size of the flash. The CHAUSIE_MCHP_SIG_FILE file itself is smaller than this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icde5f7071183cd8423fc022caf49e2c9ee288527 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62189 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-21mb/amd/chausie/Kconfig: Move EC firmware image in CBFSFred Reitberger
Move the EC to a location that does not conflict with where the main CBFS is in the chromeos FMAP Change-Id: I28c84cbe2ff10d45383d896ae4f942ee49eb15c0 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62190 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-19mb/amd/chausie: increase RW_MRC_CACHE size in FMAPFelix Held
On Sabrina SoCs the size of the APOB has increased, so the size of the RW_MRC_CACHE FMAP sections needs to be increased in order for the data to still fit in the corresponding FMAP partition. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib31b918aba90dd507b47aec9e1f75c138857cd02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62155 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17mb/amd/chausie: Add EC blob into CBFSFred Reitberger
Add chausie EC blob into CBFS at specified location Change-Id: I48de08a18054efbda655e1563a539ff2ba7a38a6 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-15mb/amd/chausie: initialize KBRST and EC flash sharing pins in bootblockFelix Held
The SPI ROM REQ/GNT pins are used in systems where the EC and the APU share one flash chip to make sure that not both devices will try to access the flash at the same time. The firmware running before the x86 cores are released from reset has likely already done this, but do it again in bootblock just to be sure. The KBRST_L pin can be used to reset the APU from the EC. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5af285ac222ed6625f498d82360f2d1cc522df2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-13mb/amd/chausie: update GPIO for chausieFred Reitberger
Add/update initial GPIO pin descriptions and initialization types for chausie mainboard. Change-Id: I14ea0e1086f626398a867896ee81ce07cf530182 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-12mb/amd/majolica/mainboard: add initial IRQ routingFelix Held
This IRQ routing info is taken from mb/google/guybrush. The IRQ routing on Chausie that was a 1:1 copy caused some issues with the I2C driver, so port the Chausie IRQ mapping change back to Majolica. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ieb958639dd8aef7c60c050ad107dde7d1cd6a8bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/61867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-12mb/amd/chausie/mainboard: add initial IRQ routingFelix Held
This IRQ routing info is taken from mb/google/guybrush. This should fix these errors: [ 0.655051] i2c_designware AMDI0010:00: IRQ index 0 not found [ 0.659239] i2c_designware AMDI0010:01: IRQ index 0 not found [ 0.663198] i2c_designware AMDI0010:02: IRQ index 0 not found [ 0.667200] i2c_designware AMDI0010:03: IRQ index 0 not found Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8c85c8e4b1c860d6ca25060353355f703a49e1e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-02-04soc/amd/sabrina/include/amd_pci_int_defs.h: remove PIRQ_SATAFelix Held
Sabrina has no SATA controller, so remove the corresponding PIRQ mapping. This was verified with PPR #57243 Rev 1.53. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I98ffa3675c361e8a74c50ebfc37e79ae63dacc85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-03mb/amd/chausie/devicetree: update I2C RX levels to match board designFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie5d5f5441132e5b0d8991d07d4dde994fc17ab64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-03soc/amd/*/i2c: factor out common I2C pad configurationFelix Held
The I2C pad control registers of Picasso and Cezanne are identical and the one of Sabrina is a superset of it, so factor out the functionality. To avoid having devicetree settings that contain raw register bits, the i2c_pad_control struct is introduced and used. The old Picasso code for this had the RX level hard-coded for 3.3V I2C interfaces, so keep it this way in this patch but add a TODO for future improvements. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-31mb/amd/majolica: Add variant to disable HDMIZheng Bao
For one specific type of APU, it doesn't have HDMI. When we detect this APU, we need to explicitly disable HDMI in DDI settings, otherwise the system would freeze. Please refer src/mainboard/google/guybrush/variants/dewatt/variant.c Change-Id: I8d7637467d2f16377d3c3064cdb0934d1658fdf7 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-27soc/amd/sabrina/chipset.cb: update USB portsFelix Held
The corresponding mainboard design guide was used as a reference here. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie61af7dab35b560d2eec1ea62058f3a4dad5cb0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-27soc/amd/sabrina: update PCI devices in devicetree.cbFelix Held
Also update mb/amd/chausie accordingly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idb4dcffa48c3dbdcffb66f1398b99ee96562efb9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-25mb/amd/chausie: add mainboard as copy of mb/amd/majolicaFelix Held
To have the new AMD Sabrina SoC code tested, add the AMD Chausie mainboard as a copy of Majolica. This patch also changes the name from Majolica to Chausie, selects the Sabrina SoC instead of the Cezanne SoC and comments out the APCB_SOURCES since those aren't available in the 3rdparty/blobs repository yet. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic7b18f7a6ae5b8365234dd1227e0b1f7f37279da Reviewed-on: https://review.coreboot.org/c/coreboot/+/61079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-10src/mainboard/amd: Remove unused <console/console.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: Ie06cfa598f40a734994abb2bc2eb8f01f9331f7f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-10src/mainboard/{amd,roda}: Remove unused <acpi/acpi.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <acpi/acpi.h>' -- src/) <(git grep -l 'SLP_EN\|SLP_TYP_SHIFT\|SLP_TYP\|SLP_TYP_S\|ACPI_TABLE_CREATOR\|OEM_ID\|ACPI_DSDT_REV_\|acpi_device_sleep_states\|ACPI_DEVICE_SLEEP\|RSDP_SIG\|ASLC\|ACPI_NAME_BUFFER_SIZE\|COREBOOT_ACPI_ID\|acpi_tables\|acpi_rsdp\|acpi_gen_regaddr\|ACPI_ADDRESS_SPACE\|ACPI_FFIXEDHW_\|ACPI_ACCESS_SIZE_\|ACPI_REG_MSR\|ACPI_REG_UNSUPPORTED\|ACPI_HID_\|acpi_table_header\|MAX_ACPI_TABLES\|acpi_rsdt\|acpi_xsdt\|acpi_hpet\|acpi_mcfg\|acpi_tcpa\|acpi_tpm2\|acpi_mcfg_mmconfig\|acpi_hmat\|acpi_hmat_mpda\|acpi_hmat_sllbi\|acpi_hmat_msci\|acpi_srat\|ACPI_SRAT_STRUCTURE_\|acpi_srat_lapic\|acpi_srat_mem\|acpi_srat_gia\|CPI_SRAT_GIA_DEV_HANDLE_\|acpi_slit\|acpi_madt\|acpi_lpit\|acpi_lpi_flags\|acpi_lpi_desc_type\|ACPI_LPI_DESC_TYPE_\|acpi_lpi_desc_hdr\|ACPI_LPIT_CTR_FREQ_TSC\|acpi_lpi_desc_ncst\|acpi_vfct_image_hdr\|acpi_vfct\|acpi_ivrs_info\|acpi_ivrs_ivhd\|acpi_ivrs\|acpi_crat_header\|ivhd11_iommu_attr\|acpi_ivrs_ivhd_11\|dev_scope_type\|SCOPE_PCI_\|SCOPE_IOAPIC\|SCOPE_MSI_HPET\|SCOPE_ACPI_NAMESPACE_DEVICE\|dev_scope\|dmar_type\|DMAR_\|DRHD_INCLUDE_PCI_ALL\|ATC_REQUIRED\|DMA_CTRL_PLATFORM_OPT_IN_FLAG\|dmar_entry\|dmar_rmrr_entry\|dmar_atsr_entry\|dmar_rhsa_entry\|dmar_andd_entry\|dmar_satc_entry\|acpi_dmar\|acpi_apic_types\|LOCAL_APIC,\|IO_APIC\|IRQ_SOURCE_OVERRIDE\|NMI_TYPE\|LOCAL_APIC_NMI\|LAPIC_ADDRESS_\|IO_SAPIC\|LOCAL_SAPIC\|PLATFORM_IRQ_SOURCES\|LOCAL_X2APIC\|GICC\|GICD\|GIC_MSI_FRAME\|GICR\|GIC_ITS\|acpi_madt_lapic\|acpi_madt_lapic_nmi\|ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS\|acpi_madt_ioapic\|acpi_madt_irqoverride\|acpi_madt_lx2apic\|acpi_madt_lx2apic_nmi\|ACPI_DBG2_PORT_\|acpi_dbg2_header\|acpi_dbg2_device\|acpi_fadt\|ACPI_FADT_\|PM_UNSPECIFIED\|PM_DESKTOP\|PM_MOBILE\|PM_WORKSTATION\|PM_ENTERPRISE_SERVER\|PM_SOHO_SERVER\|PM_APPLIANCE_PC\|PM_PERFORMANCE_SERVER\|PM_TABLET\|acpi_facs\|ACPI_FACS_\|acpi_ecdt\|acpi_hest\|acpi_hest_esd\|acpi_hest_hen\|acpi_bert\|acpi_hest_generic_data\|acpi_hest_generic_data_v300\|HEST_GENERIC_ENTRY_V300\|ACPI_GENERROR_\|acpi_generic_error_status\|GENERIC_ERR_STS_\|acpi_cstate\|acpi_sw_pstate\|acpi_xpss_sw_pstate\|acpi_tstate\|acpi_lpi_state_flags\|ACPI_LPI_STATE_\|acpi_lpi_state\|acpi_upc_type\|UPC_TYPE_\|acpi_ipmi_interface_type\|IPMI_INTERFACE_\|ACPI_IPMI_\|acpi_spmi\|ACPI_EINJ_\|ACTION_COUNT\|BEGIN_INJECT_OP\|GET_TRIGGER_ACTION_TABLE\|SET_ERROR_TYPE\|GET_ERROR_TYPE\|END_INJECT_OP\|EXECUTE_INJECT_OP\|CHECK_BUSY_STATUS\|GET_CMD_STATUS\|SET_ERROR_TYPE_WITH_ADDRESS\|TRIGGER_ERROR\|READ_REGISTER\|READ_REGISTER_VALUE\|WRITE_REGISTER\|WRITE_REGISTER_VALUE\|NO_OP\|acpi_gen_regaddr1\|acpi_einj_action_table\|acpi_injection_header\|acpi_einj_trigger_table\|set_error_type\|EINJ_PARAM_NUM\|acpi_einj_smi\|EINJ_DEF_TRIGGER_PORT\|FLAG_PRESERVE\|FLAG_IGNORE\|EINJ_REG_MEMORY\|EINJ_REG_IO\|acpi_einj\|acpi_create_einj\|fw_cfg_acpi_tables\|preload_acpi_dsdt\|write_acpi_tables\|acpi_fill_madt\|acpi_fill_ivrs_ioapic\|acpi_create_ssdt_generator\|acpi_write_bert\|acpi_create_fadt\|acpi_fill_fadt\|arch_fill_fadt\|soc_fill_fadt\|mainboard_fill_fadt\|acpi_fill_gnvs\|acpi_fill_cnvs\|update_ssdt\|update_ssdtx\|acpi_fill_lpit\|acpi_checksum\|acpi_add_table\|acpi_create_madt_lapic\|acpi_create_madt_ioapic\|acpi_create_madt_irqoverride\|acpi_create_madt_lapic_nmi\|acpi_create_madt\|acpi_create_madt_lapics\|acpi_create_madt_lapic_nmis\|acpi_create_madt_lx2apic\|acpi_create_srat_lapic\|acpi_create_srat_mem\|acpi_create_srat_gia_pci\|acpi_create_mcfg_mmconfig\|acpi_create_srat_lapics\|acpi_create_srat\|acpi_create_slit\|acpi_create_hmat_mpda\|acpi_create_hmat\|acpi_create_vfct\|acpi_create_ipmi\|acpi_create_ivrs\|acpi_create_crat\|acpi_create_hpet\|acpi_write_hpet\|generate_cpu_entries\|acpi_create_mcfg\|acpi_create_facs\|acpi_create_dbg2\|acpi_write_dbg2_pci_uart\|acpi_create_dmar\|acpi_create_dmar_drhd\|acpi_create_dmar_rmrr\|acpi_create_dmar_atsr\|acpi_create_dmar_rhsa\|acpi_create_dmar_andd\|acpi_create_dmar_satc\|cpi_dmar_\|acpi_create_\|acpi_write_hest\|acpi_soc_get_bert_region\|acpi_resume\|mainboard_suspend_resume\|acpi_find_wakeup_vector\|ACPI_S\|acpi_sleep_from_pm1\|acpi_get_preferred_pm_profile\|acpi_get_sleep_type\|acpi_get_gpe\|permanent_smi_handler\|acpi_s3_resume_allowed\|acpi_is_wakeup_s3\|acpi_align_current\|get_acpi_table_revision' -- src/) |grep "<" Change-Id: Icb90c70b0fb53175b9aaeabf067485a15fe71457 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-23ChromeOS: Refactor ACPI CNVS generationKyösti Mälkki
Remove chromeos_dsdt_generator() calls under mainboard, it is possible to make the single call to fill \CNVS and \OIPG without leveraging device operations. Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 07:36:30 +0000