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2023-06-12acpi/acpi.c: Reduce scope of functions used locallyArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ieca5d8d175923f690ebfa3108e393e029ea97c80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-06-09acpi: Add struct for SPCR tableArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I46d5caa0af95ec27fd49b0cf8fa704d656c89e7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75684 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07soc/amd/common/block/cpu/noncar: add get_usable_physical_address_bits()Felix Held
In case the secure memory encryption is enabled, some of the upper usable address bits of the host can't be used any more. Bits 11..6 in CPUID_EBX_MEM_ENCRYPT indicate how many of the address bits are taken away from the usable address bits in the case the secure memory encryption is enabled. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia810b0984972216095da2ad8f9c19e37684f2a2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75623 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-04cpu/x86/smm: Drop fxsave/fxrstor logicArthur Heymans
Since we now explicitly compile both ramstage and smihandler code without floating point operations and associated registers we don't need to save/restore floating point registers. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I180b9781bf5849111501ae8e9806554a7851c0da Reviewed-on: https://review.coreboot.org/c/coreboot/+/75317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-06-04lib: Support localized text of memory_training_desc in ux_locales.cHsuan Ting Chen
To support the localized text, we need to get the locale id by vboot APIs and read raw string content file: preram_locales located at either RO or RW. The preram_locales file follows the format: [string_name_1] [\x00] [locale_id_1] [\x00] [localized_string_1] [\x00] [locale_id_2] [\x00] [localized_string_2] ... [string_name_2] [\x00] ... This code will search for the correct localized string that its string name is `memory_training_desc` and its locale ID matches the ID vb2api returns. If no valid string found, we will try to display in English (locale ID 0). BUG=b:264666392 BRANCH=brya TEST=emerge-brya coreboot chromeos-bmpblk chromeos-bootimage Change-Id: I7e3c8d103c938a11b397c32c9228e44e31c3f01d Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-06-02device/pci_rom: Add simple pci_rom_free()Grzegorz Bernacki
It adds simple function, which frees the memory which could be allocated by pci_rom_probe(). In the next step it will be modified to free only memory, which was mapped from CBFS. BUG=b:278264488 TEST=Build and run with additional debug prints added to confirm that data are correctly unmapped Change-Id: Ibc9aad34b6bf101a3a0c06b92ed2dc6f2d7b9b33 Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74778 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-02soc/amd/common/block/cpu: Refactor ucode allocationGrzegorz Bernacki
Move microcode load/unload to pre_mp_init and post_mp_init callbacks. It allows to make sure that ucode is freed only if all APs updated microcode. BUG=b:278264488 TEST=Build and run with additional debug prints added to confirm that data are correctly unmapped Change-Id: I200d24df6157cc6d06bade34809faefea9f0090a Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-06-02include/cpu/x86: Simplify en/dis cache functionsHimanshu Sahdev
Implementation of enable/disable cache functions aren't complex, simply drop cr0 variable usage, still maintains good readablity. Signed-off-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Change-Id: I81688e8bbb073e1d09ecf63f3f33e1651dbd778e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75552 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-01include/cpu/x86: Skip `wbinvd` on CPUs with cache self-snooping (SS)Subrata Banik
This patch refers and backport some of previous work from Linux Kernel (https://lore.kernel.org/all/1561689337-19390-3-git-send-email-ricardo. neri-calderon@linux.intel.com/T/#u) that optimizes the MTRR register programming in multi-processor systems by relying on the CPUID (self-snoop feature supported). Refer to the details below: Programming MTRR registers in multi-processor systems is a rather lengthy process as it involves flushing caches. As a result, the process may take a considerable amount of time. Furthermore, all processors must program these registers serially. `wbinvd` instruction is used to invalidate the cache line to ensure that all modified data is written back to memory. All logical processors are stopped from executing until after the write-back and invalidate operation is completed. The amount of time or cycles for WBINVD to complete will vary due to the size of different cache hierarchies and other factors. As a consequence, the use of the WBINVD instruction can have an impact on response time. As per measurements, around 98% of the time needed by the procedure to program MTRRs in multi-processor systems is spent flushing caches with wbinvd(). As per the Section 11.11.8 of the Intel 64 and IA 32 Architectures Software Developer's Manual, it is not necessary to flush caches if the CPU supports cache self-snooping (ss). "Flush all caches using the WBINVD instructions. Note on a processor that supports self-snooping, CPUID feature flag bit 27, this step is unnecessary." Thus, skipping the cache flushes can reduce by several tens of milliseconds the time needed to complete the programming of the MTRR registers: Platform Before After 12-core (14 Threads) MeteorLake 35ms 1ms BUG=b:260455826 TEST=Able to build and boot google/rex. Change-Id: I83cac2b1e1707bbb1bc1bba82cf3073984e9768f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-01cpu/x86/cache: Call wbinvd only once CR0.CD is setJeremy Compostella
This patch removes the wbinvd call preceding CR0.CD setting in disable_cache() to improve the boot time performances. According to some experimental measurements, the wbinvd execution takes between 1.6 up and 6 milliseconds to complete so it is preferable to call it only when necessary. According to Intel Software Developer Manual Vol 3.A - 12.5.3 Preventing Caching section there is no need to flush and invalidate the cache before settings CR0.CD. The documented sequence consists in setting CR0.CD and then call wbinvd. We also could not find any extra requirements in the AMD64 Architecture Programmer’s Manual - Volume 2 - Memory System chapter. This extra wbinvd in coreboot disable_cache() function does not seem documented and looking into the history of the project got us all the way back to original commit 8ca8d7665d67 ("- Initial checkin of the freebios2 tree") from April 2003. Even the original disable_cache() implementation (see below) is a bit curious as the comment list two actions: 1. Disable cache cover by line 74, 75 and 77 2. Write back the cache and flush TLB - Line 78 But it does not provide any explanation for the wbinvd call line 76. 68 static inline void disable_cache(void) 69 { 70 unsigned int tmp; 71 /* Disable cache */ 72 /* Write back the cache and flush TLB */ 73 asm volatile ( 74 "movl %%cr0, %0\n\t" 75 "orl $0x40000000, %0\n\t" 76 "wbinvd\n\t" 77 "movl %0, %%cr0\n\t" 78 "wbinvd\n\t" 79 :"=r" (tmp) 80 ::"memory"); 81 } BUG=b/260455826 TEST=Successful boot on Skolas and Rex board Change-Id: I08c6486dc93c4d70cadc22a760d1b7e536e85bfa Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
2023-05-31cpu/x86/mp_init: Use clflush to write SIPI data back to RAMJeremy Compostella
Improve boot time performances by replacing the wbinvd instruction with multiple clflush to ensure that the SIPI data is written back to RAM. According to some experimental measurements, the wbinvd execution takes between 1.6 up and 6 milliseconds to complete. In the case of the SIPI data, wbinvd unnecessarily flushes and invalidates the entire cache. Indeed, the SIPI module is quite small (about 400 bytes) and cflush'ing the associated cache lines is almost instantaneous, typically less than 100 microseconds. BUG=b/260455826 TEST=Successful boot on Skolas and Rex board Change-Id: I0e00db8eaa6a3cb41bec3422572c8f2a9bec4057 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Suggested-by: Erin Park <erin.park@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75391 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-30acpi/acpigen: rename and clarify bus/IO/MMIO resource producer functionsFelix Held
The acpigen_resource_[bus_number,io,mmio*] functions didn't make it very clear that they are generating resource producer ranges and not resource consumer ranges. To clarify this, change the function names to acpigen_resource_producer_[bus_number,io,mmio*] and explicitly add the ADDR_SPACE_GENERAL_FLAG_PRODUCER flag which evaluates to 0, so this doesn't change the functionality. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I334f38aa8ab418d5577f92b980ff750504e2bb4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-05-26acpi/acpigen: add acpigen_resource_mmio to generate MMIO resourceFelix Held
Add the acpigen_resource_mmio helper function to generate an MMIO range resource. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I38d55dfcc2892bcb5d253a3aef6ed993cfdba0a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-26treewide: Remove 'extern' from functions declarationElyes Haouas
"extern" is automatically implied with function declaration. Change-Id: Ic40218acab5a009621b6882faacfcac800aaf0b9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71890 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-05-25drivers/soundwire/cs42l42: Support CS42L42 SoundWire deviceKapil Porwal
The CS42L42 low power audio codec can be connected over SoundWire and be configured for mainboards to use: - Data Port 0 and Bulk Register Access - Data Port 1 is the 64bit data output for the headset - Data Port 2 is the 64bit data input for the headset - Data Port 3 is the 64bit data input for the headset The data port and audio mode properties are filled out as best as possible with the datasheet as a reference. The ACPI address for the codec is calculated with the information in the codec driver combined with the devicetree.cb hierarchy where the link and unique IDs are extracted from the device path. For example this device is connected to master link ID 0 and has strap settings configuring it for unique ID 0. chip drivers/soundwire/cs42l42 register "desc" = ""Headset Codec"" device generic 0.0 on end end This driver was tested with the rex0 reference design by booting and disassembling the runtime SSDT to ensure that the devices have the expected address and properties. Device (SW00) { Name (_ADR, 0x00001001FA424200) // _ADR: Address Name (_DDN, "Headset Codec") // _DDN: DOS Device Name Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { GpioInt (Edge, ActiveBoth, Exclusive, PullDefault, 0x0000, "\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, , ) { // Pin list 0x0166 } GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, , ) { // Pin list 0x0167 } }) Name (_DSD, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "irq-gpios", Package () { \_SB.PCI0.HDAS.SNDW.SW00, Zero, Zero, Zero } }, Package () { "reset-gpios", Package () { \_SB.PCI0.HDAS.SNDW.SW00, One, Zero, Zero } }, Package () { "cirrus,ts-inv", One }, Package () { "cirrus,ts-dbnc-rise", 0x05 }, Package () { "cirrus,ts-dbnc-fall", Zero }, Package () { "cirrus,btn-det-init-dbnce", 0x64 }, Package () { "cirrus,btn-det-event-dbnce", 0x0A }, Package () { "cirrus,bias-lvls", Package () { 0x0F, 0x08, 0x04, One } }, Package () { "cirrus,hs-bias-ramp-rate", 0x02 }, Package () { "cirrus,hs-bias-sense-disable", One }, Package () { "mipi-sdw-sw-interface-revision", 0x00010000 }, [...] Package () { "mipi-sdw-source-port-list", 0x02 }, Package () { "mipi-sdw-sink-port-list", 0x0C } }, ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package () { Package () { "mipi-sdw-port-bra-mode-0", "BRA0" }, Package () { "mipi-sdw-dp-0-subproperties", "DP0" }, Package () { "mipi-sdw-port-audio-mode-0", "MOD0" }, Package () { "mipi-sdw-dp-1-source-subproperties", "SRC1" }, Package () { "mipi-sdw-dp-2-sink-subproperties", "SNK2" }, Package () { "mipi-sdw-dp-3-sink-subproperties", "SNK3"} } }) Name (BRA0, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-bra-mode-bus-frequency-configs", Package () { 0x00AC4400, ... } }, Package () { "mipi-sdw-bra-mode-max-data-per-frame", 0x1000 }, Package () { "mipi-sdw-bra-mode-min-us-between-transactions", Zero } } }) Name (DP0, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-port-max-wordlength", 0x40 }, [...] }, ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package () { Package () { "mipi-sdw-port-bra-mode-0", "BRA0" } } }) Name (MOD0, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-audio-mode-bus-frequency-configs", Package () { 0x00AC4400, ... } }, Package () { "mipi-sdw-audio-mode-max-sampling-frequency", 0x0002EE00 }, Package () { "mipi-sdw-audio-mode-min-sampling-frequency", 0x1F40 }, [...] } }) Name (SRC1, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-data-port-type", Zero }, [...] }, ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package () { Package () { "mipi-sdw-port-audio-mode-0", "MOD0" } } }) Name (SNK2, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-data-port-type", Zero }, [...] }, ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package () { Package () { "mipi-sdw-port-audio-mode-0", "MOD0" } } }) Name (SNK3, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-data-port-type", Zero }, [...] }, ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package () { Package () { "mipi-sdw-port-audio-mode-0", "MOD0" } } }) } BUG=b:269497731 TEST=Verified SSDT for SNDW in the OS Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ic7cfe2a21c76ba01ad3dea2a5017b28743aeb9f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73279 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-25drivers/soundwire/max98363: Support MAX98363 SoundWire deviceKapil Porwal
The MAX98363 smart speaker amp can be connected over SoundWire and be configured for mainboards to use: - Data Port 0 and Bulk Register Access is not supported - Data Port 1 is the 32bit data input for the speaker path The data port and audio mode properties are filled out as best as possible with the datasheet as a reference. The ACPI address for the codec is calculated with the information in the codec driver combined with the devicetree.cb hierarchy where the link and unique IDs are extracted from the device path. For example this device is connected to master link ID 2 and has strap settings configuring it for unique ID 0. chip drivers/soundwire/max98363 register "desc" = ""Left Speaker Amp"" device generic 2.0 on end end This driver was tested with the rex0 reference design by booting and disassembling the runtime SSDT to ensure that the devices have the expected address and properties. Device (SW20) { Name (_ADR, 0x000230019F836300) // _ADR: Address Name (_DDN, "Left Speaker Amp") // _DDN: DOS Device Name Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Name (_DSD, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-sw-interface-revision", 0x00010000 }, [...] Package () { "mipi-sdw-source-port-list", Zero }, Package () { "mipi-sdw-sink-port-list", 0x02 } }, ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package () { Package () { "mipi-sdw-port-audio-mode-0", "MOD0" }, Package () { "mipi-sdw-dp-1-sink-subproperties", "SNK1" } } }) Name (MOD0, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-audio-mode-bus-frequency-configs", Package () { 0x00927C00, ... } }, Package () { "mipi-sdw-audio-mode-sampling-frequency-configs", Package () { 0x3E80, ... } }, [...] } }) Name (SNK1, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-data-port-type", Zero }, [...] }, ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package () { Package () { "mipi-sdw-port-audio-mode-0", "MOD0" } } }) } BUG=b:269497731 TEST=Verified SSDT for SNDW in the OS Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ie56109d615759e3e5e32782c8782cb2f47014ec4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73278 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-23soc/intel/common: Add RPP-S PCI IDsJeremy Soller
Add PCI IDs to support Raptor Point PCH. Ref: Intel 700 Series PCH Datasheet, Volume 1 (#743835, rev 2) Change-Id: Iee410ed3179260b08d45f50e8126fb815c686324 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73437 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-17console: Add format-checking __printf() to die()Nico Huber
Code changes are necessary because `-Wformat` warns about empty format strings by default. Change-Id: Ic8021b70f4cd4875b06f196f88b84940c9a79fe0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75147 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-16acpigen: Add printf-like function for debug stringCliff Huang
Generate formatted string and ACPI code to print debug string. For example (with pcie_rp = 1): acpigen_write_debug_sprintf("calling _ON for RP: %u", pcie_rp); generates the following ACPI code: Debug = "calling _ON for RP: 1" With this new function, the following functions are not needed anymore and therefore are removed by this patch. - acpigen_concatenate_string_string() - acpigen_concatenate_string_int() - acpigen_write_debug_concatenate_string_string() - acpigen_write_debug_concatenate_string_int() BRANCH=firmware-brya-14505.B TEST=Add above functions in the acpigen code and check the generated SSDT table after OS boot. Check the debug messages is in the kernel log when /sys/modules/acpi/parameters/aml_debug_output is set to '1'. Change-Id: Id4a42e5854516a22b7bc4559c2ed08680722c5ba Signed-off-by: Cliff Huang <cliff.huang@intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Zhixing Ma <zhixing.ma@intel.com> Reviewed-by: Musse Abdullahi <musse.abdullahi@intel.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-11acpi/acpigen: add acpigen_resource_io to generate I/O resourceFelix Held
Add the acpigen_resource_io helper function to generate an I/O range resource. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I177f59b52d4dbbff0a3ceeef5fc8c7455cef9ff8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-05-11acpi/acpigen: add acpigen_resource_bus_number to generate bus numberFelix Held
Add the acpigen_resource_bus_number helper function to generate a bus number range resource. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ib1f1da3dbe823c6bc4fc30c0622653410cfbf301 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-05-08drivers/pc80/rtc/mc146818rtc.c: Add Kconfig for RTC CMOS base addressesJonathon Hall
Configure the CMOS bank I/O base addresses with PC_CMOS_BASE_PORT_BANK* rather than hard-coding as 0x70, 0x72. The defaults remain the same. Change-Id: Ie44e5f5191c66f44e2df8ea0ff58a860be88bfcf Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74903 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-08acpi/acpigen: add acpigen_write_BBN to generate base bus number methodFelix Held
Introduce acpigen_write_BBN to generate the ACPI method object that returns the base bus number for a PCI(e) host bridge. When called, the base_bus_number argument must be the first PCI bus number that got assigned to the corresponding host bridge. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib67bf42b9c77c262d8a02d8f28ac5cb8482136b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-05-01acpigen: Add a runtime method to override exposed _Sx sleep statesArthur Heymans
This allows mainboards to override available sleep states at runtime. This is done by adding a IntObj in SSDT that DSDT consumes to override the available _Sx states. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ic21830c1ef9c183b1e3005cc1f8b7daf7e9ea998 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74762 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-29ACPI: Make FADT entries for RTC/CMOS architecturalKyösti Mälkki
For AMD, replace name RTC_ALT_CENTURY with RTC_CLK_ALTCENTURY that points to same offset. Since the century field inside RTC falls within the NVRAM space, and could interfere with OPTION_TABLE, it is now guarded with config USE_PC_CMOS_ALTCENTURY. There were no reference for the use of offset 0x48 for century. Change-Id: I965a83dc8daaa02ad0935bdde5ca50110adb014a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74601 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-28vga: Change the arguments of vga_write_text to support extended ASCIIHsuan Ting Chen
VGA defined the extended ASCII set based on CP437, but the function vga_write_text() accepts a signed char array. This will cause unnecessary confusion that if we want to print u with umlaut (code=129 in CP437), we need to explicitly cast it to -127 in signed char. Since we still want to leverage the built-in string utilities which only accepts const char*, we still need to cast it to signed char while processing, and cast it back to unsigned once we write into the frame buffer. BRANCH=brya BUG=b:264666392 TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: If555bbc05f40ce3f02339c0468afff6dda8b7ded Reviewed-on: https://review.coreboot.org/c/coreboot/+/73099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-26arch/x86/ioapic: Promote ioapic_get_sci_pin()Kyösti Mälkki
Platform needs to implement this to provide information about SCI IRQ pin and polarity, to be used for filling in ACPI FADT and MADT entries. Change-Id: Icea7e9ca4abf3997c01617d2f78f25036d85a52f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26soc/intel: Introduce ioapic_get_sci_pin()Kyösti Mälkki
According to ACPI Release 6.5 systems supporting PIC (i8259) interrupt mechanism need to report IRQ vector for the SCI_INT field. In PIC mode only IRQ0..15 are allowed hardware vectors. This change should cover section 5.2.9 to not pass SCI_INT larger than IRQ15. Section 5.2.15.5 needs follow-up work. Care should be taken that ioapic_get_sci_pin() is called after platform code has potentially changed the routing from the default. It appears touched all platforms except siemens/mc_aplX currently program SCI as IRQ9. Change-Id: I723c207f1dcbba5e6fc0452fe1dbd087fad290ee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26ACPI: Add acpigen_write_PTC()Kyösti Mälkki
Change-Id: Ibaf2d7105e7a5da8a50ef32b682978ff55fe31e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26acpi/acpi.c: Reduce scope of some functionsArthur Heymans
These functions are only used in one compilation unit. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I6f8282f308506a68b14ce3101f11078cb13709f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74756 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-23include/cpu/amd/mtrr: fix typo in get_top_of_mem_above_4gbFelix Held
Add the missing 'b' to the 4gb so that get_top_of_mem_above_4gb is in line with get_top_of_mem_below_4gb. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic9170372d8b0c27d7de3bd04d822c95e2015cb10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-04-22lib/version: Move board identification stringsKyösti Mälkki
These strings are now only expanded in lib/identity.c. This improves ccache hit rates slightly, as one built object file lib/version.o is used for all variants of a board. Also one built object file lib/identity.o can become a ccache hit for successive builds of a variant, while the commit hash changes. Change-Id: Ia7d5454d95c8698ab1c1744e63ea4c04d615bb3b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-21include/cpu/amd/mtrr: return uint32_t from get_top_of_mem_below_4gbFelix Held
The top of memory below 4GB will always fit into 32 bits, so change the return type accordingly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b463a17f2db3b7a99ff3572f318c9c22aac7431 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-21include/cpu/amd/mtrr: rename functions to get top of memory regionsFelix Held
Rename amd_topmem and amd_topmem2 to get_top_of_mem_below_4gb and get_top_of_mem_above_4g to make it clearer what those functions return. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic6e98d94c731af74aea0ce276a9a7e4867e3986f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-18src/cpu/power9: move part of scom.h to scom.cSergii Dmytruk
Reset function, constants and include are not used outside of scom.c and not going to be. Change-Id: Iff4e98ae52c7099954f0c20fcb639eb87af15534 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2023-04-15soc/intel/meteorlake: Add B0 stepping CPU IDMusse Abdullahi
This patch adds CPU ID for B0 stepping (aka ES2). DOC=#723567 TEST=Able to boot on B0 rvp and get correct CPU Name in coreboot log. Signed-off-by: Musse Abdullahi <musse.abdullahi@intel.com> Change-Id: I8b939ccc8b05e3648c55f8f2a0a391cb08f04184 Signed-off-by: Musse Abdullahi <musse.abdullahi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74300 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-12Reland "drivers/intel/dptf: Add multiple fan support under dptf"Sumeet Pawnikar
This reverts commit 4dba71fd25c91a9e610287c61238a8fe24452e4e. Add multiple fan support for dptf policies. This also fixes the Google Meet resolution drop issue as per b:246535768 comment#12. When system starts Google Meet video call, it uses the hardware accelerated encoder as expected. But, as soon as another system connects to the call, an immediate fallback is observed from hardware to software encoder. Due to this, Google Meet resolution dropped from 720p to 180p. This issue is observed on Alder Lake-N SoC based fanless platforms. This same issue was not seen on fan based systems. With the fix in dptf driver where fan configures appropriate setting for only fan participant, not for other device participants, able to see consistent 720p resolution. BUG=b:246535768,b:235254828 BRANCH=None TEST=Built and tested on Alder Lake-P Redrix system for two fans support and on Alder Lake-N fanless systems. With this code change Google Meet resolution drop not observed. Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Change-Id: Id07d279ff962253c22be9d395ed7be0d732aeaa7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73249 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-11ACPI: Add helper for MADT LAPICsKyösti Mälkki
This avoids some code duplication related to X2APIC mode. Change-Id: I592c69e0f52687924fe41189b082c86913999136 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-04-11ACPI: Add helper for MADT LAPIC NMIsKyösti Mälkki
This avoids some code duplication related to X2APIC mode. Change-Id: I2cb8676efc1aba1b154fd04c49e53b2530239b4c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-04-11binaryPI: Use common code for LAPIC NMIsKyösti Mälkki
Change-Id: I1a39f355733d10ecd43a1da541ab2e66ba13db15 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-04-11util/sconfig: Remove unused ioapic and irq keywordsArthur Heymans
Ioapic information in the devicetree was only used to set up mptables but this generic driver was removed (ca5a793 drivers/generic/ioapic: Drop poor implementation). This removes the unused remainders from mainboard devicetrees. Remove ioapic setup from sconfig. Change-Id: Ib3fef0bf923ab3f02f3aeed2e55cf662a3dc3a1b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-06cpu/x86/topology: Add code to fill in topology on struct pathArthur Heymans
This is needed to generate MADT and SRAT where lapicid for threads need to be added last. When CPUID leaf '0xB' is not present assume some defaults that would result in identical ACPI code generation. Change-Id: I2210eb9b663dd90941a64132aa7154440dc7e5a9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69222 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-06cpu/smm_module_loader.c: Fix up CPU index locallyArthur Heymans
Don't pass the stub params to the mp_init code. Change-Id: I070bc00ae5e5bceb6c5b90ea833cc057dd41f6cc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64802 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-06cpu/x86/mp_init.c: Generate a C header to get start32 offsetArthur Heymans
In the current design the relocatable parameters are used to know the offset of the 32bit startpoint. This requires back and forward interaction between the stub, the loader and the mp init code. This makes the code hard to read. This is static information known at buildtime, so a better way to deal with this is to generate a header that contains this offset. Change-Id: Ic01badd2af11a6e1dbc27c8e928916fedf104b5b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64625 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-06cpu/x86/mp_init.c: Keep track of initial lapic ID inside device_pathArthur Heymans
It's quite confusing to keep track of lapic ID inside the device struct and initial lapic ID inside an array. Change-Id: I4d9f8d23c0b0e5c142f6907593428d8509e4e7bb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64342 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-31soc/intel/common: Add core_type member to 'struct apic_path'Sridhar Siricilla
The patch adds new member 'core_type' to the 'struct apic_path' and updates core type information. TEST=Build the code for MTL Change-Id: I1d34068fd5ef43f8408301bf3effa9febf85f683 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74088 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-29soc/intel/common: Add Intel Trace Hub driverPratikkumar Prajapati
From Meteor Lake onwards Intel FSP will generate the Trace Hub related HOB if the Trace Hub is configured to save data in DRAM. This memory region is used by Trace Hub to store the traces for debugging purpose. This driver locates the HOB and marks the memory region reserved so that OS does not use it. Intel Trace Hub developer manual can be found via document #671536 on Intel's website. Change-Id: Ie5a348071b6c6a35e8be3efd1b2b658a991aed0e Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-03-24cpu/intel: Remove redefined SAPPHIRERAPIDS_SP CPUID to fix build errorJohnny Lin
This reverts pieces of commit 08135332dd "soc/intel/xeon_sp: Report platform cpu info" Reason for revert: Due to duplicated definitions this breaks the tree. Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: I7bcffe99e4f049e38d9a13c82d38464c64250ee1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74002 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-23soc/amd/common/block/acpi/cpu_power_state: use pstate_msr unionFelix Held
Use the pstate_msr union in get_pstate_info to check if the P state enable bit is set. Also drop the now unused PSTATE_DEF_HI_ENABLE_SHIFT and PSTATE_DEF_HI_ENABLE_MASK definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I79119e09af79a4bb680a18e93b4a61a049f0080e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-03-23soc/intel/xeon_sp: Report platform cpu infoNaresh Solanki
Add platform cpu info for known microcode, print cpuid & processor branding string. This will print as in the following example: CPU: Intel(R) Xeon(R) Platinum 8468H CPU: ID 806f6, Sapphire Rapids E3, ucode: 2b000130 CPU: AES supported, TXT supported, VT supported Change-Id: I9c08fb924aad81608f554523432ab6a549b1b75f Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-03-19soc/intel/xeon_sp/spr: Add header files and romstage codeJonathan Zhang
Several FSP HOBs processing codes are similar to Intel Cooperlake-SP codes in soc/intel/xeon_sp/cpx. Register datasheet please reference Sapphire Rapids EDS Vol2 Doc#612246 and Emmitsburg PCH EDS Doc#606161. Change-Id: Ia022534e5206dbeec946d3e5f3c66bcb5628748f Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-13cpu/x86/cache: CLFLUSH programs to memory before runningArthur Heymans
When cbmem is initialized in romstage and postcar placed in the stage cache + cbmem where it is run, the assumption is made that these are all in UC memory such that calling INVD in postcar is OK. For performance reasons (e.g. postcar decompression) it is desirable to cache cbmem and the stage cache during romstage. Another reason is that AGESA sets up MTRR during romstage to cache all dram, which is currently worked around by using additional MTRR's to make that UC. TESTED on asus/p5ql-em, up/squared on both regular and S3 resume bootpath. Sometimes there are minimal performance improvements when cbmem is cached (few ms). Change-Id: I7ff2a57aee620908b71829457ea0f5a0c410ec5b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37196 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-08soc/amd/include/msr: factor out P state MSR enable bit to cpu/amd/msr.hFelix Held
The bit position of the P state enable bit in the 8 P state MSRs is identical for all AMD chips including the family 16h model 30h APU that lives outside of soc/amd. The other bits in those 8 MSRs are more or less family- and model-specific. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia69c33e28e2a91ff9a9bfe95859c1fd454921b77 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-07device/xhci: Add struct for capability registersRobert Zieba
The XHCI code does not currently contain a structure that corresponds to the XHCI capability registers. These registers contain various useful information about the controller. Create a`xhci_capability_regs` struct to address this. BRANCH=guybrush BUG=b:186792595 TEST=builds Change-Id: If38bfde726bd4e5dd314456f25a2b08acd3cd20c Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-05device/xhci: Add functions to work with resource pointersRobert Zieba
The XHCI device functions currently use functions that require a access to the device tree. Create variant of these functions that can operate with a resource* as an argument and refactor the existing device*-based functions to operate by calling the resource*-based variants. This is useful for stages like SMM that may not have access to the device tree. BRANCH=guybrush BUG=b:186792595 TEST=Ran on skyrim device, verified that XHCI ACPI tables are still generated correctly. Change-Id: If5a74f9529d5dc6031ec968ef5f40a9cad5ffbc4 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-05cpu/x86/smm: Add PCI resource store functionalityRobert Zieba
In certain cases data within protected memmory areas like SMRAM could be leaked or modified if an attacker remaps PCI BARs to point within that area. Add support to the existing SMM runtime to allow storing PCI resources in SMRAM and then later retrieving them. BRANCH=guybrush BUG=b:186792595 TEST=builds Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I23fb1e935dd1b89f1cc5c834cc2025f0fe5fda37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-03acpi: Add SRAT x2APIC table supportNaresh Solanki
For platforms using X2APIC mode add SRAT x2APIC table generation. This allows to setup proper SRAT tables. Change-Id: If78c423884b7ce9330f0f46998ac83da334ee26d Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-03lib: set up specific purpose memory as LB_MEM_SOFT_RESERVEDJonathan Zhang
CXL (Compute Express Link) [1] is a cache-coherent interconnect standard for processors, memory expansion and accelerators. CXL memory is provided through CXL device which is connected through CXL/PCIe link, while regular system memory is provided through DIMMs plugged into DIMM slots which are connected to memory controllers of processor. With CXL memory, the server's memory capacity is increased. CXL memory is in its own NUMA domain, with longer latency and added bandwidth, comparing to regular system memory. Host firmware may present CXL memory as specific purpose memory. Linux kernel dax driver provides direct access to such differentiated memory. In particular, hmem dax driver provides direct access to specific purpose memory. Specific purpose memory needs to be represented in e820 table as soft reserved, as described in [2]. Add IORESOURCE_SOFT_RESERVE resource property to indicate (memory) resource that needs to be soft reserved. Add soft_reserved_ram_resource macro to allow soc/mb code to add memory resource as soft reserved. [1] https://www.computeexpresslink.org/ [2] https://web.archive.org/web/20230130233752/https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.32&id=262b45ae3ab4bf8e2caf1fcfd0d8307897519630 Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ie70795bcb8c97e9dd5fb772adc060e1606f9bab0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52585 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-28soc/amd: introduce and use PSTATE_MSR macroFelix Held
Instead of adding the P-state number to the PSTATE_0_MSR number to get the P-state MSR number for the rdmsr call, provide a macro that directly calculates the MSR number for a given power state. Also drop the unused PSTATE_[1..4]_MSR definitions which also didn't cover all P-state MSRs available in the hardware. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If85acf556efe82c209e1608e56c05f7a2a748403 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-02-28include/device/pci_def.h: Fix typo in commentWerner Zeh
Fix typo in the comment for Common Clock Configuration. Change-Id: Idd01e787458a9090d53b9a57547b8158480dcc16 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2023-02-15cpu/x86/smm: Enable setting SMM console log level from mainboardJohnny Lin
Add a Kconfig RUNTIME_CONFIGURABLE_SMM_LOGLEVEL that enables mainboard to override mainboard_set_smm_log_level for SMM log level. This can let SMM have different log level than other stages for more flexibility. Another reason is that getting certain data that requires searching from flash VPD or CMOS is not very ideal to be done in SMM, so in this change the value can be passed via the member variable in struct smm_runtime and be referenced directly in SMM. One example is that mainboard can get the desired SMM log level from VPD/CMOS, and pass SMM console log level via the variable and in SMM it can be referenced in get_console_loglevel() override function directly. Tested=On OCP Delta Lake, verified SMM log level can be overridden. Change-Id: I81722a4f1bf75ec942cc06e403ad702dfe938e71 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49460 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2023-02-15pc80/i8254: Add speaker beep functionMichał Żygowski
Some platforms have an onboard speaker which could be used as an indicator of successful boot or critical error, e.g. in die_notify function. The function assumes that SPKR GPIO is properly configured by the platform code. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I8189b3462bb5140af352fa786db3a6a2a45076f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-02-12drivers/smmstore: Expose region devicePatrick Rudolph
Allow other drivers to use the SMMSTORE region device. Change-Id: I6316b703829590bd6f41c3d4013b4a4660b9cbab Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-10acpi/acpigen: add acpigen_write_store_namestr_to_namestrFelix Held
acpigen_write_rom open-codes this functionality, so add a function for this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ief25dd854d1639a295c021e9d02c05b4cc61109c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-10soc/intel/{common, meteorlake}: Add support for new MCHSridhar Siricilla
The patch adds support for new Meteor Lake MCH (ID:0x7d16). TEST=Build and boot the system having MCH ID:0x7d16. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ib0c9ce5c58e4bdec5e7245840f0892d651922cd9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com>
2023-02-09sb/intel/lynxpoint: Add PCI DIDs for 9 series PCHsAngel Pons
The desktop 9 series PCHs should be the same as the 8 series PCHs. Change-Id: Iee93fee4f28b88a72c537944159fb7cbb2796235 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-09src/acpi: add function gen: if_lgreater_ and namestr assignmentCliff Huang
1. add functions to generate if greater than conditions: acpigen_write_if_lgreater_op_op: if (op1 > op2) acpigen_write_if_lgreater_op_int: if (op > val) acpigen_write_if_lgreater_namestr_int: if (namestr > val) 2. add function to assignal value to a namestr acpigen_write_store_namestr_to_op: namestr = val TEST=Use above functions and check the generated SSDT table after OS boot. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Iffe1b23362a7ab58bdc2aa8daf45cd6f086ee818 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72825 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-09console: Add SimNow console loggingFred Reitberger
The AMD SimNow tool supports fast logging through an IO port. Add a new console to support SimNow logging through port 80. TEST=observe significant speed improvements on SimNow console log Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I42a431f48ea14ba4adacbd4a32e15abe7c5e4951 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-08acpi/acpigen.h: Fix EVENT_OP valueElyes Haouas
Fix EVENT_OP value according to ACPI specs: https://uefi.org/specs/ACPI/6.5/20_AML_Specification.html?highlight=aml%20byte%20stream%20byte%20values#aml-byte-stream-byte-values Change-Id: I8c531e95f4fc741926bc883d869816f534ff3b7f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-07src: Move POST_BOOTBLOCK_CAR to common postcodes and use itMartin Roth
This moves the definition for POST_BOOTBLOCK_CAR from the intel-specific postcodes into the common postcode list, and uses it for the cache-as-RAM init as needed. Because POST_BOOTBLOCK_CAR was set to 0x20 in some spots and 0x21 in most of the others, the values were consolidated into 0x21. This will change the value on some platforms. Any conflicts should get sorted out later in the conversion process. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8527334e679a23006b77a5645f919aea76dd4926 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-07tree: Drop repeated wordsAlexander Goncharov
Found-by: linter Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72795 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-06inc/device: Add extended capability ID for ATSTim Chu
Add extended capability ID for Address Translation Services. This definition can be found in PCI Express Base Specification rev6.0 9.3.7. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I777070ea223fc7e83c510c8eadbe4e028825eef6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71929 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-06device/pci_device.c: Add way to limit max bus numbersArthur Heymans
By default this limits PCI buses to CONFIG_MMCONF_BUS_NUMBER. Some platforms have multiple PCI root busses (e.g. xeon_sp), where bus numbers are limited. This provides a basic check. On some platforms it looks like programming 0xff to the subordinate bus number confuses and hangs the hardware. Change-Id: I0582b156df1a5f76119a3687886c4d58f2d3ad6f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-02-04include/bootstate.h: Fail compilation on invalid bootstate hooksArthur Heymans
No BS_ON_EXIT hooks are run on BS_PAYLOAD_BOOT or BS_OS_RESUME, so don't allow these hooks. Change-Id: I318165f0bd510aed3138d3612dd3e264901aba96 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-02-02include/cpu/amd/mtrr: drop unused TOP_MEM_MASK definitionsFelix Held
Neither TOP_MEM_MASK nor TOP_MEM_MASK_KB is used, so drop the two definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0b2dfb7be27884dffb948876aabb73f99834c281 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-31acpi/acpigen: introduce acpigen_write_processor_deviceFelix Held
The ACPI PROCESSOR_OP has been deprecated in ACPI 6.0 and dropped in ACPI 6.4 and is now permanently reserved. As a replacement, DEVICE_OP with the special HID ACPI0007 should be used instead. This special HID was introduced in version 3 of the ACPI spec. To have a function to generate this, acpigen_write_processor_device is introduced. The CPU index is used as UID which can be assumed to be unique. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifb0da903a972be134bb3b9071f81b441f60917d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72469 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-31console: Print architecturePatrick Rudolph
Useful to see which architecture x86_32 or x86_64 coreboot was built for. Change-Id: I34eec64ac32254c270dcbb97e20a7e6be0f478fc Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-01-28acpi/acpigen: factor out acpigen_write_processor_namestringFelix Held
This functionality is used in multiple places, so factor it out into a function. Compared to acpigen_write_processor_cnot, the buffer size is decreased from 40 to 16 bytes, but the format string specified by CONFIG_ACPI_CPU_STRING results in 9 chars and a NULL byte which will fit into the buffer without any issue. I've seen the CPU devices being put into another scope within \_SB, but even in that case that would be 14 chars and a NULL byte whist still fits into the 16 byte buffer. For acpigen_write_processor and acpigen_write_processor_package this doesn't change any edge case behavior. In the unrealistic case of the format string resulting in a longer CPU device string, this would have been a problem before this patch too. Also drop the curly braces of the for loop in acpigen_write_processor_package. This makes the code a bit harder to read and isn't a very good idea, but with the curly braces in place, the linter breaks the build :( Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5d8291a2aaae2011cb185d72c7f7864b6e2220ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/72452 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-27src/acpi: add debug message with concatenated stringCliff Huang
add functions for concatenate OP add debug message containing concatenated string with string, value, or OPs Ex1: to print string with another string provided from C side: acpigen_write_debug_concatenate_string_string("Wait loop Timeout! var=", name, LOCAL6_OP); will generate: Concatenate ("Wait loop Timeout! var=", "L23E", Local6) Debug = Local6 Ex2: to print string with a value: acpigen_write_debug_concatenate_string_int("ModPHY enabling for RP:", pcie_rp, LOCAL0_OP); will generate: Concatenate ("ModPHY enabling for RP:", 0x05, Local0) Debug = Local0 Ex3: to print string with an ACPI OP: acpigen_write_debug_concatenate_string_op("while Loop count: ", LOCAL7_OP, LOCAL6_OP) will generate: Concatenate ("while Loop count: ", Local7, Local6) Debug = Local6 TEST=Add above functions in the acpigen code and check the generated SSDT table after OS boot Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I370745efe3d6b513ec2c5376248362a3eb4b3d21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72126 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2023-01-25soc/intel/common/gpio: Add function to read GPIO TX valueCliff Huang
This function reads out the current value set to output for a GPIO pin. Ex: GPP_E0 is set to output int e0_val; e0_val = gpio_tx_get(GPP_E0); Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ib02b9ab50d378eb163d91aed1576428b49cec2cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/72127 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2023-01-24soc/intel/cmn/block: Add smbus/p2sb device ids for SPR-SPTim Chu
Intel SPR-SP (Sapphire Rapids Scalable Processor) was product launched on Jan. 10, 2023. The chipset includes Emmitsburg PCH. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I05ed8f753bf63b6cb3035e973eb6a7974edfd673 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-01-19drivers/usb/acpi: Add USB _DSM method to enable/disable USB LPM per portKane Chen
This patch supports projects to use _DSM to control USB3 U1/U2 transition per port. More details can be found in https://web.archive.org/web/20230116084819/https://learn.microsoft.com/en-us/windows-hardware/drivers/bringup/usb-device-specific-method---dsm- The ACPI and USB driver of linux kernel need corresponding functions to support this feature. Please see https://git.kernel.org/pub/scm/linux/kernel/git/mnyman/xhci.git/log/?h=port_check_acpi_dsm BUG=b:253402457 TEST=tested on felwinter and found _DSM method is created. Change-Id: Iffb2498e26352a3f120c097c50587324e311e8ba Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71924 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-19tree: Drop Intel Ice Lake supportFelix Singer
Intel Ice Lake is unmaintained and the only user of this platform ever was the Intel CRB (Customer Reference Board). As it looks like, it was never ready for production as only engineering sample CPUIDs are supported. As announced in the 4.19 release notes, remove support for Intel Icelake code and move any maintenance on the 4.19 branch. This affects the following components and their related code: * Intel Ice Lake SoC * Intel Ice Lake CRB mainboard * Documentation Change-Id: Ia796d4dc217bbcc3bbd9522809ccff5a46938094 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72008 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11treewide: stop calling custom TPM log "TCPA"Sergii Dmytruk
TCPA usually refers to log described by TPM 1.2 specification. Change-Id: I896bd94f18b34d6c4b280f58b011d704df3d4022 Ticket: https://ticket.coreboot.org/issues/423 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-01-09security/intel/txt: Add helper function to disable TXTSubrata Banik
Add a function to disable TXT as per TXT BIOS spec Section 6.2.5. AP firmware can disable TXT if TXT fails or TPM is already enabled. On platforms with TXT disabled, the memory can be unlocked using MSR 0x2e6. TEST=Able to perform disable_txt on SoC SKUs with TXT enabled. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I27f613428e82a1dd924172eab853d2ce9c32b473 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-08include/memory_info.h: Add soc_num to dimm_info structTim Chu
Sometimes, server platforms may have more than one socket on server board. However, there's no field to store information about which socket the DIMM comes from in dimm_info structure. This patch adds soc_num field in dimm_info structure to store socket ID of the DIMM. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I1b9e2b87fda2d7c32ecb8ce9d989795c8b869cea Reviewed-on: https://review.coreboot.org/c/coreboot/+/70662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2023-01-08arch/x86/smbios: Replace SMBIOS type4 processor upgrade fieldsLi, Jincheng
values by macros Macro definitions are from DMTF System Management BIOS (SMBIOS) Reference Specification (DSP0134) Chapter 7.5.5. Change-Id: Ifed1d773b0b349f878648b8172fd770a397e9686 Signed-off-by: Li, Jincheng <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-04spd.h: Move enum ddr3_module_type to ddr3.hElyes Haouas
Move specific enum ddr3_module_type to <device/dram/ddr3.h>. Change-Id: I8fd7892dda26158a5bdd6cd4972c7859a252153e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71547 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04spd.h: Move enum ddr2_module_type to ddr2.hElyes Haouas
Move specific enum ddr2_module_type to <device/dram/ddr2.h>. Change-Id: I748658f9b349bff9b1ebe2c0a6acf71bf2a221ce Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71546 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-02drivers/pc80/vga: Add API to write multi-line video messageSubrata Banik
This patch provides an API to allow users to output multi-line messages using VGA framebuffer. The current limitation with multiline message is that, vga_line_write() function is unable to understand newline character hence, eventually output multiple lines separated with a newline character with a single line statement. This patch ensures to parse the entire string and split it into multiple lines based on the newline character and print each line separately to the VFG framebuffer. User can choose to align the output video message as per given choice between left/center/right of the screen (i.e. enum VGA_TEXT_ALIGNMENT ). Additionally, added macros to define the horizontal screen alignment as well. Ideally if user would like to print the video message at the middle of the screen then the vertical alignment would be `VGA_TEXT_CENTER` and horizontal alignment would be `VGA_TEXT_HORIZONTAL_MIDDLE`. TEST=Able to build and boot Google/Taeko. While output a video message such as : "Your device is finishing an update. This may take 1-2 minutes.\nPlease do not turn off your device." Without this patch: Your device is finishing an update. This may take 1-2 minutes. nPlease do not turn off your device. With this patch: (in Left Alignment): Your device is finishing an update. This may take 1-2 minutes. Please do not turn off your device. (in Right Alignment): Your device is finishing an update. This may take 1-2 minutes. Please do not turn off your device. (in Center Alignment): Your device is finishing an update. This may take 1-2 minutes. Please do not turn off your device. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib837e4deeba9b84038a91c93a68f03cee3474f9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-12-28coding_style: Add more guidelines on error handling, die() and assert()Julius Werner
This patch adds a new section to the coding style which codifies existing practices about how to handle errors and how to use the die() and assert() macros. Also clean up some references to Linux-specific facilities that do not exist in coreboot in the adjacent function return type guidelines, and add a small blurb of documentation to the definition of the assert() macro itself. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ice37ed9f995a56d69476e95a352209041b337284 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70775 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-12-27drivers/intel/ish: Add ADL-P ISH DIDSubrata Banik
This patch adds ISH ID for ADL-P to ensure dynamic ASL code is added into SSDT. With this patch: Scope (\_SB.PCI0.ISHB) { Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"), Package (0x01) { Package (0x02) { "DmaProperty", One } } }) } Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I48dc6056155824239bb88eda2b0ff5bcd36ced15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71262 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyle Lin <kylelinck@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-25arch/x86: Use 'enum cb_err'Elyes Haouas
Change-Id: I38e4b8c6adfaaa45377b2fbe0644285d21841cd1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-24vc/google/chromeos: use fw_config field to return sar filenameEric Lai
Use fw_config field to return sar filename instead of fw_config probe. Return filename unconditionly because the sar_id must be valid in CBI. If invalid sar_id, the file won't exist in CBFS by design. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I7b75c5d4fd3c459ad7232bb16c6218a6218f1f77 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-24lib: add stub for fw_config_get_fieldEric Lai
Return UNDEFINED_FW_CONFIG with disabled fw_config. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I0d31ff3ba7706039c622bd1ec825d216a0f21fe4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-22inc/dev/pci_def.h: add definitions for RCEC EA Ext. CapbilityJonathan Zhang
Root Complex Event Collector Endpoint Association Extended Capability is defined in section 7.9.10 of PCIe 5.0 spec. Add its Extended Capability ID, association bitmap for RCiEPs register, and RCEC associated bus numbers register. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I7bede8ed88304a2925e6e1e4128bcdd625ee0e53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22soc/intel/alderlake: Add Raptor Lake device IDsMarx Wang
Add system agent ID for RPL QDF#Q2MB/Q2PS TEST=able to build coreboot successfully Signed-off-by: Marx Wang <marx.wang@intel.com> Change-Id: I169c8bc51cdf7fbfcdb1996d93afa4a352e2fddf Reviewed-on: https://review.coreboot.org/c/coreboot/+/71121 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-21treewide: Remove duplicated includesElyes Haouas
<types.h> provides <commonlib/bsd/cb_err.h>, <stdint.h> and <stddef.h>. Change-Id: I966303336e604b1b945df77e5d4c3cccbf045c56 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-12-21lib/nhlt, soc/intel/skl: Update NHLT to program feedback configMatt DeVillier
Adapted from WIP (and abandoned) patch CB:25334, this patch: 1. Ensures SSP endpoint InstanceId is 0 2. Adds capability_size parameter at the end of the nhlt 3. Adsd more config_type enum values to accommodate feedback stream 4. Programs virtual_slot values for max98373, max98927, and rt5514 nhlt files 5. Adds NHLT feedback_config parameters Default feedback configs are added here to the max98373, max98927, and rt5514 codecs; in a follow-on patch, these will be overridden at the board level. TEST=tested with subsequent patch Change-Id: I59285e332de09bb448b0d67ad56c72a208588d47 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com>
2022-12-20soc/intel/cmn/block/cnvi: Add missing CNVI IDs for ADLKapil Porwal
Add missing CNVI IDs for ADL - ADL-P: 0x51f2, 0x51f3 ADL-S: 0x7af1, 0x7af2, 0x7af3 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I189be9a8c8895a93d98886e6591e771bbce5f564 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>