diff options
| author | Jonathan Zhang <jonzhang@meta.com> | 2023-01-25 11:33:16 -0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-03-19 09:49:03 +0000 |
| commit | 15fc45982b9b8303978ab87ea6c93d423834e6e8 (patch) | |
| tree | e0d4f9203e1cee49ba992f36a20d849362fef06e /src/include | |
| parent | ecb4a24eaa720b4c7be506b0986f7797a3d8dbf6 (diff) | |
soc/intel/xeon_sp/spr: Add header files and romstage code
Several FSP HOBs processing codes are similar to Intel Cooperlake-SP
codes in soc/intel/xeon_sp/cpx.
Register datasheet please reference Sapphire Rapids EDS Vol2 Doc#612246
and Emmitsburg PCH EDS Doc#606161.
Change-Id: Ia022534e5206dbeec946d3e5f3c66bcb5628748f
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/cpu/intel/cpu_ids.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index 4e23c5bb30..863dc8b3a5 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -11,6 +11,12 @@ #define CPUID_SKYLAKE_SP_A0_A1 0x506f0 #define CPUID_SKYLAKE_SP_B0 0x506f1 #define CPUID_SKYLAKE_SP_4 0x50654 +#define CPUID_SAPPHIRERAPIDS_SP_D 0x0806f3 +#define CPUID_SAPPHIRERAPIDS_SP_E0 0x0806f4 +#define CPUID_SAPPHIRERAPIDS_SP_E2 0x0806f5 +#define CPUID_SAPPHIRERAPIDS_SP_E3 0x0806f6 +#define CPUID_SAPPHIRERAPIDS_SP_E4 0x0806f7 +#define CPUID_SAPPHIRERAPIDS_SP_Ex 0x0806f8 #define CPUID_SKYLAKE_C0 0x406e2 #define CPUID_SKYLAKE_D0 0x406e3 #define CPUID_SKYLAKE_HQ0 0x506e1 |