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path: root/src/cpu
AgeCommit message (Expand)Author
2012-07-02remove CONFIG_SERIAL_CPU_INITSven Schnelle
2012-07-02Use broadcast SIPI to startup siblingsSven Schnelle
2012-07-02Intel CPUs: execute microcode update only once per coreKyösti Mälkki
2012-06-19Enable Intel PECI on Model 6fx CPUsSven Schnelle
2012-06-12udelay: add missing bus frequencySven Schnelle
2012-05-30Fix the location of "Setting variable MTRR" printk.Denis 'GNUtoo' Carikli
2012-05-29Drop config variable CPU_MODEL_INDEXStefan Reinauer
2012-05-08Some more #if cleanupPatrick Georgi
2012-05-08Clean up #ifsPatrick Georgi
2012-05-03Fix register corruption during Intel Microcode updateStefan Reinauer
2012-05-02Don't include console.h in microcode.c when compiling with ROMCCStefan Reinauer
2012-05-01Drop CONFIG_MAX_PHYSICAL_CPUS on non-AMD boardsStefan Reinauer
2012-05-01Move VSA support from x86 to GeodePatrick Georgi
2012-05-01Make geode_lx use the vsa from blobs repositoryPatrick Georgi
2012-04-30Fix up Sandybridge C state generation codeStefan Reinauer
2012-04-30Rework ACPI CST table generationStefan Reinauer
2012-04-27Move top level pc80 directory to drivers/Stefan Reinauer
2012-04-26microcode: print date of microcode and unify outputStefan Reinauer
2012-04-26Revamp Intel microcode update codeStefan Reinauer
2012-04-25Replace cache control magic numbers with symbolsPatrick Georgi
2012-04-22amd: Fix unused variable warningVikram Narayanan
2012-04-20Revert wbind added to the reset_vectorMarc Jones
2012-04-16S3 code in coreboot public folder.zbao
2012-04-12S3 code in vendorcode folder.zbao
2012-04-11Remove obsolete empy macro definitionRon Minnich
2012-04-06Fixes and Sandybridge support for lapic cpu initStefan Reinauer
2012-04-06Fix support for RAM-less multi-processor initKyösti Mälkki
2012-04-06Add Sandybridge/Cougar Point support to SMM relocation handlerStefan Reinauer
2012-04-06Cache 8MB flash instead of 4MBStefan Reinauer
2012-04-05Fix timer frequency detection on SandybridgeStefan Reinauer
2012-04-05Invalidate cache before first jumpStefan Reinauer
2012-04-05Update documentation in smmrelocate.S to mention TSEGStefan Reinauer
2012-04-05Add support for Intel Sandybridge CPUStefan Reinauer
2012-04-04Add support to run SMM handler in TSEG instead of ASEGStefan Reinauer
2012-04-03Add support for Intel Turbo Boost featureStefan Reinauer
2012-04-02Apply cache-as-ram conditionally on socket mPGA604Kyösti Mälkki
2012-04-02S3 code whitespaces changes.zbao
2012-03-31Whitespace fixesPatrick Georgi
2012-03-31Intel cpus: get MAXPHYADDR at runtime for new CARKyösti Mälkki
2012-03-31Intel cpus: add hyper-threading CPU support to new CARKyösti Mälkki
2012-03-31Intel cpus: improve CPU compatibility of new CARKyösti Mälkki
2012-03-31Add support for RAM-less multi-processor initKyösti Mälkki
2012-03-31Intel cpus: apply some good programming practices in new CARKyösti Mälkki
2012-03-31Intel cpus: cache actual size of the Flash ROM deviceKyösti Mälkki
2012-03-31Intel cpus: copy model_6ex CAR codeKyösti Mälkki
2012-03-30Make MTRR min hole alignment 64MBDuncan Laurie
2012-03-30Fix MB calculation in the reporting of the MTRR holeDuncan Laurie
2012-03-30MTRR: add alternate allocation method for odd memory mapsDuncan Laurie
2012-03-30Add Kconfig options to enable TSEG and set a sizeDuncan Laurie
2012-03-30drop use of MAX_PHYSICAL_CPUS and MAX_CPUS where not neededStefan Reinauer
2012-03-30Add an option to keep the ROM cached after romstageStefan Reinauer
2012-03-25Fix possible deadlock on SMP stop_this_cpuKyösti Mälkki
2012-03-25Intel cpus: Fix deadlock on hyper-threading initKyösti Mälkki
2012-03-17Intel cpus: Include CAR from socketKyösti Mälkki
2012-03-16Rename AMD_AGESA to CPU_AMD_AGESAKyösti Mälkki
2012-03-16Fix AMD Agesa leaking KconfigKyösti Mälkki
2012-03-16ROMCC boards have no XIP limitPatrick Georgi
2012-03-16Via Epia-N and C3: Set ioapic delivery type in KconfigPatrick Georgi
2012-03-16Fix address of IDT in real-mode entryKyösti Mälkki
2012-03-09move console includes to central console/console.hStefan Reinauer
2012-03-07Move C labels to start-of-linePatrick Georgi
2012-02-20Fix MTRR TOM2 WB cache setup for AMD CPUs > revF.Marc Jones
2012-02-17Remove whitespace.Patrick Georgi
2012-02-16AGESA F15: AGESA family15 model 00-0fh cpu wrapperKerry Sheh
2012-02-16Intel cpus: use CPU_PHYSMASK_HI define in CARKyösti Mälkki
2012-02-15Intel model_106cx: Use symbolic names for MTRR bitsKyösti Mälkki
2012-02-13AMD Geode cpus: apply un-written naming rulesKyösti Mälkki
2012-02-10Intel cpus: apply un-written naming rulesKyösti Mälkki
2012-02-09Add Intel Socket LGA771Sven Schnelle
2012-02-09VIA cpus: apply un-written naming rulesKyösti Mälkki
2012-01-23post code: Replaced hard-coded post code with macroVikram Narayanan
2012-01-21trivial: spelling fixes in commentsVikram Narayanan
2012-01-20Leave SSE and MMX instructions enabled in corebootStefan Reinauer
2012-01-10MTRR: get physical address size from CPUIDSven Schnelle
2012-01-09Fix Geode GX2 + LX caching for tiny bootblock.Nils Jacobs
2012-01-09ACPI: mark empty get_cst_entries() weakSven Schnelle
2011-12-26Fix Fam10 MMCONF_SUPPORT_DEFAULT setting.Marc Jones
2011-12-13Use MMCONF for all AMD family 10 CPUs.Marc Jones
2011-12-05Bootblock does not need a unique boot_cpu()Kyösti Mälkki
2011-11-24Remove unused code files and cosmetic changesKyösti Mälkki
2011-11-22k8 raminit: add workaround for erratum #181 on non-fam-fFlorian Zumbiehl
2011-11-22Fix post_code in 16bit entryKyösti Mälkki
2011-11-01remove trailing whitespaceStefan Reinauer
2011-11-01Remove XIP_ROM_BASEPatrick Georgi
2011-10-30Fix slow CAR execution introduced by 7c7d87182feb78cb2bc02fb3558bef56a41682c9Rudolf Marek
2011-10-28Get rid of the old romstage-as-bootblock ROM layoutPatrick Georgi
2011-10-28Get rid of AUTO_XIP_ROM_BASEPatrick Georgi
2011-10-25SPEEDSTEP: write _CST tablesSven Schnelle
2011-10-18Activate older Xeon P4 microcodesKyösti Mälkki
2011-10-17Fixes several issues with amd k8 SSDT P-state generationOskar Enoksson
2011-10-15SMM: Move wbinvd after pmode jumpStefan Reinauer
2011-10-13Load an IDT with NULL limitStefan Reinauer
2011-10-11Fixed broken MTRR for >4GB memory on AMD K8 fam 0fh rev <=EOskar Enoksson
2011-09-24Add AMD Family 10h PH-E0 supportQingPei Wang
2011-09-12Miscellaneous AMD F14 warning fixesefdesign98
2011-09-09Crank up CPU speed on Intel Core and Core2 CPUsPatrick Georgi
2011-09-07AMD F14 Rev C0 updateKerry She
2011-08-06Update AMD F14 Agesa to support Rev C0 cpusefdesign98
2011-08-04cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.Keith Hui
2011-07-22Add SSE3 dependent codeefdesign98
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