AGESA F15: AGESA family15 model 00-0fh cpu wrapper

Change-Id: I7580bc063c09d99d3fca8b20cd39df2384a6ad44
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/555
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

7 files changed, 330 insertions, 2 deletions

diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index 60bb74b70f..631724b04a 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -1,7 +1,7 @@
 #
 # This file is part of the coreboot project.
 #
-# Copyright (C) 2011 Advanced Micro Devices, Inc.
+# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -17,6 +17,26 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
 
+config AMD_AGESA
+        bool
+        default n
+
+config XIP_ROM_BASE
+	hex
+	default 0xfff00000
+
+config XIP_ROM_SIZE
+	hex
+	default 0x100000
+	help
+	  Overwride the default write through caching size as 1M Bytes.
+	  On some AMD paltform, one socket support 2 or more kinds of
+	  processor family, compiling several cpu families agesa code
+	  will increase the romstage size.
+	  In order to execute romstage in place on the flash rom,
+	  more space is required to be set as write through caching.
+
 source src/cpu/amd/agesa/family10/Kconfig
 source src/cpu/amd/agesa/family12/Kconfig
 source src/cpu/amd/agesa/family14/Kconfig
+source src/cpu/amd/agesa/family15/Kconfig
diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc
index 4331435b7a..fb536ddc53 100644
--- a/src/cpu/amd/agesa/Makefile.inc
+++ b/src/cpu/amd/agesa/Makefile.inc
@@ -1,7 +1,7 @@
 #
 # This file is part of the coreboot project.
 #
-# Copyright (C) 2011 Advanced Micro Devices, Inc.
+# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -19,6 +19,7 @@
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += family10
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += family12
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14
+subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15
 
 ramstage-y += apic_timer.c
 cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc
diff --git a/src/cpu/amd/agesa/family15/Kconfig b/src/cpu/amd/agesa/family15/Kconfig
new file mode 100644
index 0000000000..0f2f920256
--- /dev/null
+++ b/src/cpu/amd/agesa/family15/Kconfig
@@ -0,0 +1,82 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+config CPU_AMD_AGESA_FAMILY15
+	bool
+	select PCI_IO_CFG_EXT
+	select AMD_AGESA
+
+if CPU_AMD_AGESA_FAMILY15
+
+config CPU_AMD_SOCKET_G34
+	bool
+	default n
+	help
+	  AMD G34 Socket
+
+config CPU_AMD_SOCKET_C32
+	bool
+	default n
+	help
+	  AMD C32 Socket
+
+config CPU_AMD_SOCKET_AM3R2
+	bool
+	default n
+	help
+	  AMD AM3r2 Socket
+
+config EXT_RT_TBL_SUPPORT
+	bool
+	default n
+
+config EXT_CONF_SUPPORT
+	bool
+	default n
+
+config CBB
+	hex
+	default 0x0
+
+config CDB
+	hex
+	default 0x18
+
+config XIP_ROM_BASE
+	hex
+	default 0xfff80000
+
+config XIP_ROM_SIZE
+	hex
+	default 0x80000
+
+config HAVE_INIT_TIMER
+	bool
+	default y
+
+config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL
+        bool "Redirect AGESA IDS_HDT_CONSOLE to serial console"
+        default n
+        depends on CPU_AMD_AGESA_FAMILY15
+        help
+          This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console.
+
+          Warning: Only enable this option when debuging or tracing AMD AGESA code.
+
+endif #CPU_AMD_AGESA_FAMILY15
diff --git a/src/cpu/amd/agesa/family15/Makefile.inc b/src/cpu/amd/agesa/family15/Makefile.inc
new file mode 100644
index 0000000000..936d3c82ca
--- /dev/null
+++ b/src/cpu/amd/agesa/family15/Makefile.inc
@@ -0,0 +1,30 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+subdirs-y += ../../mtrr
+subdirs-y += ../../../x86/tsc
+subdirs-y += ../../../x86/lapic
+subdirs-y += ../../../x86/cache
+subdirs-y += ../../../x86/mtrr
+subdirs-y += ../../../x86/pae
+subdirs-y += ../../../x86/smm
+
+ramstage-y += chip_name.c
+driver-y += model_15_init.c
+
diff --git a/src/cpu/amd/agesa/family15/chip.h b/src/cpu/amd/agesa/family15/chip.h
new file mode 100644
index 0000000000..0171e7fcd0
--- /dev/null
+++ b/src/cpu/amd/agesa/family15/chip.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations cpu_amd_agesa_family15_ops;
+
+struct cpu_amd_agesa_family15_config {
+};
diff --git a/src/cpu/amd/agesa/family15/chip_name.c b/src/cpu/amd/agesa/family15/chip_name.c
new file mode 100644
index 0000000000..963a423df1
--- /dev/null
+++ b/src/cpu/amd/agesa/family15/chip_name.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations cpu_amd_agesa_family15_ops = {
+	CHIP_NAME("AMD CPU Family 15h")
+};
diff --git a/src/cpu/amd/agesa/family15/model_15_init.c b/src/cpu/amd/agesa/family15/model_15_init.c
new file mode 100644
index 0000000000..d100338170
--- /dev/null
+++ b/src/cpu/amd/agesa/family15/model_15_init.c
@@ -0,0 +1,147 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/pae.h>
+
+#include <cpu/cpu.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/amd/amdfam15.h>
+
+static msr_t rdmsr_amd(u32 index)
+{
+	msr_t result;
+	__asm__ __volatile__(
+			"rdmsr"
+			:"=a"(result.lo), "=d"(result.hi)
+			:"c"(index), "D"(0x9c5a203a)
+			);
+	return result;
+}
+
+static void wrmsr_amd(u32 index, msr_t msr)
+{
+	__asm__ __volatile__(
+			"wrmsr"
+			: /* No outputs */
+			:"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a)
+			);
+}
+
+static void model_15_init(device_t dev)
+{
+	printk(BIOS_DEBUG, "Model 15 Init.\n");
+
+	u8 i;
+	msr_t msr;
+	int msrno;
+#if CONFIG_LOGICAL_CPUS == 1
+	u32 siblings;
+#endif
+
+	disable_cache ();
+	/* Enable access to AMD RdDram and WrDram extension bits */
+	msr = rdmsr(SYSCFG_MSR);
+	msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
+	wrmsr(SYSCFG_MSR, msr);
+
+	// BSP: make a0000-bffff UC, c0000-fffff WB, same as ApMtrrSettingsList for APs
+	msr.lo = msr.hi = 0;
+	wrmsr (0x259, msr);
+	msr.lo = msr.hi = 0x1e1e1e1e;
+	for (msrno = 0x268; msrno <= 0x26f; msrno++)
+		wrmsr (msrno, msr);
+
+	msr.lo = 0x04040404; msr.hi = 0x04040404;
+	wrmsr(0x259, msr);
+
+	/* disable access to AMD RdDram and WrDram extension bits */
+	msr = rdmsr(SYSCFG_MSR);
+	msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
+	wrmsr(SYSCFG_MSR, msr);
+	enable_cache ();
+
+	/* zero the machine check error status registers */
+	msr.lo = 0;
+	msr.hi = 0;
+	for (i = 0; i < 6; i++) {
+		wrmsr(MCI_STATUS + (i * 4), msr);
+	}
+
+	/* Enable the local cpu apics */
+	setup_lapic();
+
+#if CONFIG_LOGICAL_CPUS == 1
+	siblings = cpuid_ecx(0x80000008) & 0xff;
+
+	if (siblings > 0) {
+		msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
+		msr.lo |= 1 << 28;
+		wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
+
+		msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
+		msr.hi |= 1 << (33 - 32);
+		wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
+	}
+	printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
+#endif
+
+	/* DisableCf8ExtCfg */
+	msr = rdmsr(NB_CFG_MSR);
+	msr.hi &= ~(1 << (46 - 32));
+	wrmsr(NB_CFG_MSR, msr);
+
+
+	/* Write protect SMM space with SMMLOCK. */
+	msr = rdmsr(HWCR_MSR);
+	msr.lo |= (1 << 0);
+	wrmsr(HWCR_MSR, msr);
+}
+
+static struct device_operations cpu_dev_ops = {
+	.init = model_15_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_AMD, 0x100F80},    /* HY-D0 */
+	{ X86_VENDOR_AMD, 0x100F90},    /* HY-D0 */
+	{ X86_VENDOR_AMD, 0x100F81},    /* HY-D1 */
+	{ X86_VENDOR_AMD, 0x100F91},    /* HY-D1 */
+	{ X86_VENDOR_AMD, 0x600f00 },   /* OR_A0x */
+	{ X86_VENDOR_AMD, 0x600f01 },   /* OR_A0x */
+	{ X86_VENDOR_AMD, 0x600f10 },   /* OR_B0x */
+	{ X86_VENDOR_AMD, 0x600f11 },   /* OR_B1x */
+	{ X86_VENDOR_AMD, 0x600f12 },   /* OR_B2x */
+	{ X86_VENDOR_AMD, 0x600f13 },   /* OR_B3x */
+	{ X86_VENDOR_AMD, 0x600f20 },   /* OR_C0x */
+	{ 0, 0 },
+};
+
+static const struct cpu_driver model_15 __cpu_driver = {
+	.ops      = &cpu_dev_ops,
+	.id_table = cpu_table,
+};