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Diffstat (limited to 'src/cpu/amd/agesa/Kconfig')
| -rw-r--r-- | src/cpu/amd/agesa/Kconfig | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 60bb74b70f..631724b04a 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -17,6 +17,26 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +config AMD_AGESA + bool + default n + +config XIP_ROM_BASE + hex + default 0xfff00000 + +config XIP_ROM_SIZE + hex + default 0x100000 + help + Overwride the default write through caching size as 1M Bytes. + On some AMD paltform, one socket support 2 or more kinds of + processor family, compiling several cpu families agesa code + will increase the romstage size. + In order to execute romstage in place on the flash rom, + more space is required to be set as write through caching. + source src/cpu/amd/agesa/family10/Kconfig source src/cpu/amd/agesa/family12/Kconfig source src/cpu/amd/agesa/family14/Kconfig +source src/cpu/amd/agesa/family15/Kconfig |