index
:
coreboot.git
macbookair5_2
macbookpro10_1
main
master
mbp101_medisable
mbp101_medisable_1
mbp82
x230
my copy of coreboot
gitea
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
cpu
Age
Commit message (
Expand
)
Author
2012-07-02
Use broadcast SIPI to startup siblings
Sven Schnelle
2012-07-02
Intel CPUs: execute microcode update only once per core
Kyösti Mälkki
2012-06-19
Enable Intel PECI on Model 6fx CPUs
Sven Schnelle
2012-06-12
udelay: add missing bus frequency
Sven Schnelle
2012-05-30
Fix the location of "Setting variable MTRR" printk.
Denis 'GNUtoo' Carikli
2012-05-29
Drop config variable CPU_MODEL_INDEX
Stefan Reinauer
2012-05-08
Some more #if cleanup
Patrick Georgi
2012-05-08
Clean up #ifs
Patrick Georgi
2012-05-03
Fix register corruption during Intel Microcode update
Stefan Reinauer
2012-05-02
Don't include console.h in microcode.c when compiling with ROMCC
Stefan Reinauer
2012-05-01
Drop CONFIG_MAX_PHYSICAL_CPUS on non-AMD boards
Stefan Reinauer
2012-05-01
Move VSA support from x86 to Geode
Patrick Georgi
2012-05-01
Make geode_lx use the vsa from blobs repository
Patrick Georgi
2012-04-30
Fix up Sandybridge C state generation code
Stefan Reinauer
2012-04-30
Rework ACPI CST table generation
Stefan Reinauer
2012-04-27
Move top level pc80 directory to drivers/
Stefan Reinauer
2012-04-26
microcode: print date of microcode and unify output
Stefan Reinauer
2012-04-26
Revamp Intel microcode update code
Stefan Reinauer
2012-04-25
Replace cache control magic numbers with symbols
Patrick Georgi
2012-04-22
amd: Fix unused variable warning
Vikram Narayanan
2012-04-20
Revert wbind added to the reset_vector
Marc Jones
2012-04-16
S3 code in coreboot public folder.
zbao
2012-04-12
S3 code in vendorcode folder.
zbao
2012-04-11
Remove obsolete empy macro definition
Ron Minnich
2012-04-06
Fixes and Sandybridge support for lapic cpu init
Stefan Reinauer
2012-04-06
Fix support for RAM-less multi-processor init
Kyösti Mälkki
2012-04-06
Add Sandybridge/Cougar Point support to SMM relocation handler
Stefan Reinauer
2012-04-06
Cache 8MB flash instead of 4MB
Stefan Reinauer
2012-04-05
Fix timer frequency detection on Sandybridge
Stefan Reinauer
2012-04-05
Invalidate cache before first jump
Stefan Reinauer
2012-04-05
Update documentation in smmrelocate.S to mention TSEG
Stefan Reinauer
2012-04-05
Add support for Intel Sandybridge CPU
Stefan Reinauer
2012-04-04
Add support to run SMM handler in TSEG instead of ASEG
Stefan Reinauer
2012-04-03
Add support for Intel Turbo Boost feature
Stefan Reinauer
2012-04-02
Apply cache-as-ram conditionally on socket mPGA604
Kyösti Mälkki
2012-04-02
S3 code whitespaces changes.
zbao
2012-03-31
Whitespace fixes
Patrick Georgi
2012-03-31
Intel cpus: get MAXPHYADDR at runtime for new CAR
Kyösti Mälkki
2012-03-31
Intel cpus: add hyper-threading CPU support to new CAR
Kyösti Mälkki
2012-03-31
Intel cpus: improve CPU compatibility of new CAR
Kyösti Mälkki
2012-03-31
Add support for RAM-less multi-processor init
Kyösti Mälkki
2012-03-31
Intel cpus: apply some good programming practices in new CAR
Kyösti Mälkki
2012-03-31
Intel cpus: cache actual size of the Flash ROM device
Kyösti Mälkki
2012-03-31
Intel cpus: copy model_6ex CAR code
Kyösti Mälkki
2012-03-30
Make MTRR min hole alignment 64MB
Duncan Laurie
2012-03-30
Fix MB calculation in the reporting of the MTRR hole
Duncan Laurie
2012-03-30
MTRR: add alternate allocation method for odd memory maps
Duncan Laurie
2012-03-30
Add Kconfig options to enable TSEG and set a size
Duncan Laurie
2012-03-30
drop use of MAX_PHYSICAL_CPUS and MAX_CPUS where not needed
Stefan Reinauer
2012-03-30
Add an option to keep the ROM cached after romstage
Stefan Reinauer
2012-03-25
Fix possible deadlock on SMP stop_this_cpu
Kyösti Mälkki
2012-03-25
Intel cpus: Fix deadlock on hyper-threading init
Kyösti Mälkki
2012-03-17
Intel cpus: Include CAR from socket
Kyösti Mälkki
2012-03-16
Rename AMD_AGESA to CPU_AMD_AGESA
Kyösti Mälkki
2012-03-16
Fix AMD Agesa leaking Kconfig
Kyösti Mälkki
2012-03-16
ROMCC boards have no XIP limit
Patrick Georgi
2012-03-16
Via Epia-N and C3: Set ioapic delivery type in Kconfig
Patrick Georgi
2012-03-16
Fix address of IDT in real-mode entry
Kyösti Mälkki
2012-03-09
move console includes to central console/console.h
Stefan Reinauer
2012-03-07
Move C labels to start-of-line
Patrick Georgi
2012-02-20
Fix MTRR TOM2 WB cache setup for AMD CPUs > revF.
Marc Jones
2012-02-17
Remove whitespace.
Patrick Georgi
2012-02-16
AGESA F15: AGESA family15 model 00-0fh cpu wrapper
Kerry Sheh
2012-02-16
Intel cpus: use CPU_PHYSMASK_HI define in CAR
Kyösti Mälkki
2012-02-15
Intel model_106cx: Use symbolic names for MTRR bits
Kyösti Mälkki
2012-02-13
AMD Geode cpus: apply un-written naming rules
Kyösti Mälkki
2012-02-10
Intel cpus: apply un-written naming rules
Kyösti Mälkki
2012-02-09
Add Intel Socket LGA771
Sven Schnelle
2012-02-09
VIA cpus: apply un-written naming rules
Kyösti Mälkki
2012-01-23
post code: Replaced hard-coded post code with macro
Vikram Narayanan
2012-01-21
trivial: spelling fixes in comments
Vikram Narayanan
2012-01-20
Leave SSE and MMX instructions enabled in coreboot
Stefan Reinauer
2012-01-10
MTRR: get physical address size from CPUID
Sven Schnelle
2012-01-09
Fix Geode GX2 + LX caching for tiny bootblock.
Nils Jacobs
2012-01-09
ACPI: mark empty get_cst_entries() weak
Sven Schnelle
2011-12-26
Fix Fam10 MMCONF_SUPPORT_DEFAULT setting.
Marc Jones
2011-12-13
Use MMCONF for all AMD family 10 CPUs.
Marc Jones
2011-12-05
Bootblock does not need a unique boot_cpu()
Kyösti Mälkki
2011-11-24
Remove unused code files and cosmetic changes
Kyösti Mälkki
2011-11-22
k8 raminit: add workaround for erratum #181 on non-fam-f
Florian Zumbiehl
2011-11-22
Fix post_code in 16bit entry
Kyösti Mälkki
2011-11-01
remove trailing whitespace
Stefan Reinauer
2011-11-01
Remove XIP_ROM_BASE
Patrick Georgi
2011-10-30
Fix slow CAR execution introduced by 7c7d87182feb78cb2bc02fb3558bef56a41682c9
Rudolf Marek
2011-10-28
Get rid of the old romstage-as-bootblock ROM layout
Patrick Georgi
2011-10-28
Get rid of AUTO_XIP_ROM_BASE
Patrick Georgi
2011-10-25
SPEEDSTEP: write _CST tables
Sven Schnelle
2011-10-18
Activate older Xeon P4 microcodes
Kyösti Mälkki
2011-10-17
Fixes several issues with amd k8 SSDT P-state generation
Oskar Enoksson
2011-10-15
SMM: Move wbinvd after pmode jump
Stefan Reinauer
2011-10-13
Load an IDT with NULL limit
Stefan Reinauer
2011-10-11
Fixed broken MTRR for >4GB memory on AMD K8 fam 0fh rev <=E
Oskar Enoksson
2011-09-24
Add AMD Family 10h PH-E0 support
QingPei Wang
2011-09-12
Miscellaneous AMD F14 warning fixes
efdesign98
2011-09-09
Crank up CPU speed on Intel Core and Core2 CPUs
Patrick Georgi
2011-09-07
AMD F14 Rev C0 update
Kerry She
2011-08-06
Update AMD F14 Agesa to support Rev C0 cpus
efdesign98
2011-08-04
cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.
Keith Hui
2011-07-22
Add SSE3 dependent code
efdesign98
2011-07-22
Update AMD SR5650 and SB700
efdesign98
[next]